blob: 16be97116087998c6df10c2de5d573e04798075a [file] [log] [blame]
Dan Handley9df48042015-03-19 18:58:55 +00001/*
Manish V Badarkhe5a4f9b82023-04-30 09:25:15 +01002 * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01006#ifndef ARM_DEF_H
7#define ARM_DEF_H
Dan Handley9df48042015-03-19 18:58:55 +00008
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009#include <arch.h>
10#include <common/interrupt_props.h>
11#include <common/tbbr/tbbr_img_def.h>
12#include <drivers/arm/gic_common.h>
13#include <lib/utils_def.h>
14#include <lib/xlat_tables/xlat_tables_defs.h>
Manish V Badarkhe55861512020-03-27 13:25:51 +000015#include <plat/arm/common/smccc_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <plat/common/common_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000017
18/******************************************************************************
19 * Definitions common to all ARM standard platforms
20 *****************************************************************************/
21
Max Shvetsov06dba292019-12-06 11:50:12 +000022/*
laurenw-arm055199b2022-10-28 11:26:32 -050023 * Root of trust key lengths
Max Shvetsov06dba292019-12-06 11:50:12 +000024 */
25#define ARM_ROTPK_HEADER_LEN 19
26#define ARM_ROTPK_HASH_LEN 32
laurenw-arm055199b2022-10-28 11:26:32 -050027/* ARM_ROTPK_KEY_LEN includes DER header + raw key material */
28#define ARM_ROTPK_KEY_LEN 294
Max Shvetsov06dba292019-12-06 11:50:12 +000029
Juan Castillo7d199412015-12-14 09:35:25 +000030/* Special value used to verify platform parameters from BL2 to BL31 */
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +000031#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978)
Dan Handley9df48042015-03-19 18:58:55 +000032
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -060033#define ARM_SYSTEM_COUNT U(1)
Dan Handley9df48042015-03-19 18:58:55 +000034
35#define ARM_CACHE_WRITEBACK_SHIFT 6
36
Soby Mathewfec4eb72015-07-01 16:16:20 +010037/*
38 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
39 * power levels have a 1:1 mapping with the MPIDR affinity levels.
40 */
41#define ARM_PWR_LVL0 MPIDR_AFFLVL0
42#define ARM_PWR_LVL1 MPIDR_AFFLVL1
Soby Mathewa869de12015-05-08 10:18:59 +010043#define ARM_PWR_LVL2 MPIDR_AFFLVL2
Chandni Cherukuri9ec4a112018-10-16 14:42:19 +053044#define ARM_PWR_LVL3 MPIDR_AFFLVL3
Soby Mathewfec4eb72015-07-01 16:16:20 +010045
46/*
47 * Macros for local power states in ARM platforms encoded by State-ID field
48 * within the power-state parameter.
49 */
50/* Local power state for power domains in Run state. */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010051#define ARM_LOCAL_STATE_RUN U(0)
Soby Mathewfec4eb72015-07-01 16:16:20 +010052/* Local power state for retention. Valid only for CPU power domains */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010053#define ARM_LOCAL_STATE_RET U(1)
Soby Mathewfec4eb72015-07-01 16:16:20 +010054/* Local power state for OFF/power-down. Valid for CPU and cluster power
55 domains */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010056#define ARM_LOCAL_STATE_OFF U(2)
Soby Mathewfec4eb72015-07-01 16:16:20 +010057
Dan Handley9df48042015-03-19 18:58:55 +000058/* Memory location options for TSP */
59#define ARM_TRUSTED_SRAM_ID 0
60#define ARM_TRUSTED_DRAM_ID 1
61#define ARM_DRAM_ID 2
62
Gary Morrison3d7f6542021-01-27 13:08:47 -060063#ifdef PLAT_ARM_TRUSTED_SRAM_BASE
laurenw-arm7c7b1982020-10-21 13:34:40 -050064#define ARM_TRUSTED_SRAM_BASE PLAT_ARM_TRUSTED_SRAM_BASE
65#else
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010066#define ARM_TRUSTED_SRAM_BASE UL(0x04000000)
Gary Morrison3d7f6542021-01-27 13:08:47 -060067#endif /* PLAT_ARM_TRUSTED_SRAM_BASE */
laurenw-arm7c7b1982020-10-21 13:34:40 -050068
Dan Handley9df48042015-03-19 18:58:55 +000069#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010070#define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */
Dan Handley9df48042015-03-19 18:58:55 +000071
72/* The remaining Trusted SRAM is used to load the BL images */
73#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \
74 ARM_SHARED_RAM_SIZE)
75#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
76 ARM_SHARED_RAM_SIZE)
77
78/*
Zelalem Awekec43c5632021-07-12 23:41:05 -050079 * The top 16MB (or 64MB if RME is enabled) of DRAM1 is configured as
80 * follows:
Dan Handley9df48042015-03-19 18:58:55 +000081 * - SCP TZC DRAM: If present, DRAM reserved for SCP use
Zelalem Awekec43c5632021-07-12 23:41:05 -050082 * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled
83 * - REALM DRAM: Reserved for Realm world if RME is enabled
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +000084 * - TF-A <-> RMM SHARED: Area shared for communication between TF-A and RMM
Manish V Badarkheb65ae4e2022-12-12 10:14:25 +000085 * - Event Log: Area for Event Log if MEASURED_BOOT feature is enabled
Dan Handley9df48042015-03-19 18:58:55 +000086 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use
Zelalem Awekec43c5632021-07-12 23:41:05 -050087 *
johpow019d134022021-06-16 17:57:28 -050088 * RME enabled(64MB) RME not enabled(16MB)
89 * -------------------- -------------------
90 * | | | |
91 * | AP TZC (~28MB) | | AP TZC (~14MB) |
92 * -------------------- -------------------
Manish V Badarkheb65ae4e2022-12-12 10:14:25 +000093 * | Event Log | | Event Log |
94 * | (4KB) | | (4KB) |
95 * -------------------- -------------------
96 * | REALM (RMM) | | |
97 * | (32MB - 4KB) | | EL3 TZC (2MB) |
98 * -------------------- -------------------
johpow019d134022021-06-16 17:57:28 -050099 * | | | |
Manish V Badarkheb65ae4e2022-12-12 10:14:25 +0000100 * | TF-A <-> RMM | | SCP TZC |
101 * | SHARED (4KB) | 0xFFFF_FFFF-------------------
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +0000102 * --------------------
103 * | |
104 * | EL3 TZC (3MB) |
105 * --------------------
johpow019d134022021-06-16 17:57:28 -0500106 * | L1 GPT + SCP TZC |
107 * | (~1MB) |
Zelalem Awekec43c5632021-07-12 23:41:05 -0500108 * 0xFFFF_FFFF --------------------
Dan Handley9df48042015-03-19 18:58:55 +0000109 */
Zelalem Awekec43c5632021-07-12 23:41:05 -0500110#if ENABLE_RME
111#define ARM_TZC_DRAM1_SIZE UL(0x04000000) /* 64MB */
112/*
113 * Define a region within the TZC secured DRAM for use by EL3 runtime
114 * firmware. This region is meant to be NOLOAD and will not be zero
Chris Kay33bfc5e2023-02-14 11:30:04 +0000115 * initialized. Data sections with the attribute `.arm_el3_tzc_dram` will be
Zelalem Awekec43c5632021-07-12 23:41:05 -0500116 * placed here. 3MB region is reserved if RME is enabled, 2MB otherwise.
117 */
118#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00300000) /* 3MB */
119#define ARM_L1_GPT_SIZE UL(0x00100000) /* 1MB */
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +0000120/* 32MB - ARM_EL3_RMM_SHARED_SIZE */
121#define ARM_REALM_SIZE (UL(0x02000000) - \
122 ARM_EL3_RMM_SHARED_SIZE)
123#define ARM_EL3_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */
Zelalem Awekec43c5632021-07-12 23:41:05 -0500124#else
125#define ARM_TZC_DRAM1_SIZE UL(0x01000000) /* 16MB */
126#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2MB */
127#define ARM_L1_GPT_SIZE UL(0)
128#define ARM_REALM_SIZE UL(0)
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +0000129#define ARM_EL3_RMM_SHARED_SIZE UL(0)
Zelalem Awekec43c5632021-07-12 23:41:05 -0500130#endif /* ENABLE_RME */
Dan Handley9df48042015-03-19 18:58:55 +0000131
132#define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
Zelalem Awekec43c5632021-07-12 23:41:05 -0500133 ARM_DRAM1_SIZE - \
134 (ARM_SCP_TZC_DRAM1_SIZE + \
135 ARM_L1_GPT_SIZE))
Dan Handley9df48042015-03-19 18:58:55 +0000136#define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE
137#define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \
Zelalem Awekec43c5632021-07-12 23:41:05 -0500138 ARM_SCP_TZC_DRAM1_SIZE - 1U)
Manish V Badarkheb65ae4e2022-12-12 10:14:25 +0000139
140# if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \
141MEASURED_BOOT
142#define ARM_EVENT_LOG_DRAM1_SIZE UL(0x00001000) /* 4KB */
143
144#if ENABLE_RME
145#define ARM_EVENT_LOG_DRAM1_BASE (ARM_REALM_BASE - \
146 ARM_EVENT_LOG_DRAM1_SIZE)
147#else
148#define ARM_EVENT_LOG_DRAM1_BASE (ARM_EL3_TZC_DRAM1_BASE - \
149 ARM_EVENT_LOG_DRAM1_SIZE)
150#endif /* ENABLE_RME */
151#define ARM_EVENT_LOG_DRAM1_END (ARM_EVENT_LOG_DRAM1_BASE + \
152 ARM_EVENT_LOG_DRAM1_SIZE - \
153 1U)
154#else
155#define ARM_EVENT_LOG_DRAM1_SIZE UL(0)
156#endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */
157
Zelalem Awekec43c5632021-07-12 23:41:05 -0500158#if ENABLE_RME
159#define ARM_L1_GPT_ADDR_BASE (ARM_DRAM1_BASE + \
160 ARM_DRAM1_SIZE - \
161 ARM_L1_GPT_SIZE)
162#define ARM_L1_GPT_END (ARM_L1_GPT_ADDR_BASE + \
163 ARM_L1_GPT_SIZE - 1U)
Dan Handley9df48042015-03-19 18:58:55 +0000164
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +0000165#define ARM_REALM_BASE (ARM_EL3_RMM_SHARED_BASE - \
166 ARM_REALM_SIZE)
167
Zelalem Awekec43c5632021-07-12 23:41:05 -0500168#define ARM_REALM_END (ARM_REALM_BASE + ARM_REALM_SIZE - 1U)
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +0000169
170#define ARM_EL3_RMM_SHARED_BASE (ARM_DRAM1_BASE + \
171 ARM_DRAM1_SIZE - \
172 (ARM_SCP_TZC_DRAM1_SIZE + \
173 ARM_L1_GPT_SIZE + \
174 ARM_EL3_RMM_SHARED_SIZE + \
175 ARM_EL3_TZC_DRAM1_SIZE))
176
177#define ARM_EL3_RMM_SHARED_END (ARM_EL3_RMM_SHARED_BASE + \
178 ARM_EL3_RMM_SHARED_SIZE - 1U)
Zelalem Awekec43c5632021-07-12 23:41:05 -0500179#endif /* ENABLE_RME */
180
181#define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \
182 ARM_EL3_TZC_DRAM1_SIZE)
Soby Mathew3b5156e2017-10-05 12:27:33 +0100183#define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \
Alexei Fedorovc7176172020-07-13 12:11:05 +0100184 ARM_EL3_TZC_DRAM1_SIZE - 1U)
Soby Mathew3b5156e2017-10-05 12:27:33 +0100185
Dan Handley9df48042015-03-19 18:58:55 +0000186#define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
Zelalem Awekec43c5632021-07-12 23:41:05 -0500187 ARM_DRAM1_SIZE - \
188 ARM_TZC_DRAM1_SIZE)
Dan Handley9df48042015-03-19 18:58:55 +0000189#define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \
Zelalem Awekec43c5632021-07-12 23:41:05 -0500190 (ARM_SCP_TZC_DRAM1_SIZE + \
191 ARM_EL3_TZC_DRAM1_SIZE + \
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +0000192 ARM_EL3_RMM_SHARED_SIZE + \
Zelalem Awekec43c5632021-07-12 23:41:05 -0500193 ARM_REALM_SIZE + \
Manish V Badarkheb65ae4e2022-12-12 10:14:25 +0000194 ARM_L1_GPT_SIZE + \
195 ARM_EVENT_LOG_DRAM1_SIZE))
196
Dan Handley9df48042015-03-19 18:58:55 +0000197#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \
Zelalem Awekec43c5632021-07-12 23:41:05 -0500198 ARM_AP_TZC_DRAM1_SIZE - 1U)
Dan Handley9df48042015-03-19 18:58:55 +0000199
Soby Mathew7e4d6652017-05-10 11:50:30 +0100200/* Define the Access permissions for Secure peripherals to NS_DRAM */
201#if ARM_CRYPTOCELL_INTEG
202/*
203 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell.
204 * This is required by CryptoCell to authenticate BL33 which is loaded
205 * into the Non Secure DDR.
206 */
207#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD
208#else
209#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE
210#endif
211
Summer Qin9db8f2e2017-04-24 16:49:28 +0100212#ifdef SPD_opteed
213/*
Jens Wiklanderae73b162017-08-24 15:39:09 +0200214 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to
215 * load/authenticate the trusted os extra image. The first 512KB of
216 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading
217 * for OPTEE is paged image which only include the paging part using
218 * virtual memory but without "init" data. OPTEE will copy the "init" data
219 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the
220 * extra image behind the "init" data.
Summer Qin9db8f2e2017-04-24 16:49:28 +0100221 */
Jens Wiklanderae73b162017-08-24 15:39:09 +0200222#define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \
223 ARM_AP_TZC_DRAM1_SIZE - \
224 ARM_OPTEE_PAGEABLE_LOAD_SIZE)
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100225#define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000)
Summer Qin9db8f2e2017-04-24 16:49:28 +0100226#define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \
227 ARM_OPTEE_PAGEABLE_LOAD_BASE, \
228 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \
229 MT_MEMORY | MT_RW | MT_SECURE)
Soby Mathew874fc9e2017-09-01 13:43:50 +0100230
231/*
232 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging
233 * support is enabled).
234 */
235#define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \
236 BL32_BASE, \
237 BL32_LIMIT - BL32_BASE, \
238 MT_MEMORY | MT_RW | MT_SECURE)
Summer Qin9db8f2e2017-04-24 16:49:28 +0100239#endif /* SPD_opteed */
Dan Handley9df48042015-03-19 18:58:55 +0000240
241#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
242#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
243 ARM_TZC_DRAM1_SIZE)
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +0000244
Dan Handley9df48042015-03-19 18:58:55 +0000245#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
Alexei Fedorovc7176172020-07-13 12:11:05 +0100246 ARM_NS_DRAM1_SIZE - 1U)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600247#ifdef PLAT_ARM_DRAM1_BASE
laurenw-arm7c7b1982020-10-21 13:34:40 -0500248#define ARM_DRAM1_BASE PLAT_ARM_DRAM1_BASE
249#else
Sandrine Bailleux6c32fc72018-10-31 14:28:17 +0100250#define ARM_DRAM1_BASE ULL(0x80000000)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600251#endif /* PLAT_ARM_DRAM1_BASE */
laurenw-arm7c7b1982020-10-21 13:34:40 -0500252
Sandrine Bailleux6c32fc72018-10-31 14:28:17 +0100253#define ARM_DRAM1_SIZE ULL(0x80000000)
Dan Handley9df48042015-03-19 18:58:55 +0000254#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
Alexei Fedorovc7176172020-07-13 12:11:05 +0100255 ARM_DRAM1_SIZE - 1U)
Dan Handley9df48042015-03-19 18:58:55 +0000256
Sami Mujawara43ae7c2019-05-09 13:35:02 +0100257#define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE
Dan Handley9df48042015-03-19 18:58:55 +0000258#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE
259#define ARM_DRAM2_END (ARM_DRAM2_BASE + \
Alexei Fedorovc7176172020-07-13 12:11:05 +0100260 ARM_DRAM2_SIZE - 1U)
AlexeiFedorov8e754f92022-12-14 17:28:11 +0000261/* Number of DRAM banks */
AlexeiFedorov334d2352022-12-29 15:57:40 +0000262#define ARM_DRAM_NUM_BANKS 2UL
Dan Handley9df48042015-03-19 18:58:55 +0000263
264#define ARM_IRQ_SEC_PHY_TIMER 29
265
266#define ARM_IRQ_SEC_SGI_0 8
267#define ARM_IRQ_SEC_SGI_1 9
268#define ARM_IRQ_SEC_SGI_2 10
269#define ARM_IRQ_SEC_SGI_3 11
270#define ARM_IRQ_SEC_SGI_4 12
271#define ARM_IRQ_SEC_SGI_5 13
272#define ARM_IRQ_SEC_SGI_6 14
273#define ARM_IRQ_SEC_SGI_7 15
274
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000275/*
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100276 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
277 * terminology. On a GICv2 system or mode, the lists will be merged and treated
278 * as Group 0 interrupts.
279 */
280#define ARM_G1S_IRQ_PROPS(grp) \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100281 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100282 GIC_INTR_CFG_LEVEL), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100283 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100284 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100285 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100286 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100287 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100288 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100289 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100290 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100291 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100292 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100293 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100294 GIC_INTR_CFG_EDGE)
295
296#define ARM_G0_IRQ_PROPS(grp) \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100297 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100298 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100299 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100300 GIC_INTR_CFG_EDGE)
301
johpow019d134022021-06-16 17:57:28 -0500302#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
303 ARM_SHARED_RAM_BASE, \
304 ARM_SHARED_RAM_SIZE, \
305 MT_DEVICE | MT_RW | EL3_PAS)
Dan Handley9df48042015-03-19 18:58:55 +0000306
johpow019d134022021-06-16 17:57:28 -0500307#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
308 ARM_NS_DRAM1_BASE, \
309 ARM_NS_DRAM1_SIZE, \
310 MT_MEMORY | MT_RW | MT_NS)
Dan Handley9df48042015-03-19 18:58:55 +0000311
johpow019d134022021-06-16 17:57:28 -0500312#define ARM_MAP_DRAM2 MAP_REGION_FLAT( \
313 ARM_DRAM2_BASE, \
314 ARM_DRAM2_SIZE, \
315 MT_MEMORY | MT_RW | MT_NS)
Roberto Vargasf8fda102017-08-08 11:27:20 +0100316
johpow019d134022021-06-16 17:57:28 -0500317#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \
318 TSP_SEC_MEM_BASE, \
319 TSP_SEC_MEM_SIZE, \
320 MT_MEMORY | MT_RW | MT_SECURE)
Dan Handley9df48042015-03-19 18:58:55 +0000321
David Wang0ba499f2016-03-07 11:02:57 +0800322#if ARM_BL31_IN_DRAM
johpow019d134022021-06-16 17:57:28 -0500323#define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \
324 BL31_BASE, \
325 PLAT_ARM_MAX_BL31_SIZE, \
326 MT_MEMORY | MT_RW | MT_SECURE)
David Wang0ba499f2016-03-07 11:02:57 +0800327#endif
Dan Handley9df48042015-03-19 18:58:55 +0000328
johpow019d134022021-06-16 17:57:28 -0500329#define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \
330 ARM_EL3_TZC_DRAM1_BASE, \
331 ARM_EL3_TZC_DRAM1_SIZE, \
332 MT_MEMORY | MT_RW | EL3_PAS)
Soby Mathew3b5156e2017-10-05 12:27:33 +0100333
johpow019d134022021-06-16 17:57:28 -0500334#define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \
335 PLAT_ARM_TRUSTED_DRAM_BASE, \
336 PLAT_ARM_TRUSTED_DRAM_SIZE, \
337 MT_MEMORY | MT_RW | MT_SECURE)
Manish V Badarkheb65ae4e2022-12-12 10:14:25 +0000338
339# if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \
340MEASURED_BOOT
341#define ARM_MAP_EVENT_LOG_DRAM1 \
342 MAP_REGION_FLAT( \
343 ARM_EVENT_LOG_DRAM1_BASE, \
344 ARM_EVENT_LOG_DRAM1_SIZE, \
345 MT_MEMORY | MT_RW | MT_SECURE)
346#endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */
Achin Guptae97351d2019-10-11 15:15:19 +0100347
Zelalem Awekec43c5632021-07-12 23:41:05 -0500348#if ENABLE_RME
Soby Mathew0338e9e2022-07-06 16:01:40 +0100349/*
350 * We add the EL3_RMM_SHARED size to RMM mapping to map the region as a block.
351 * Else we end up requiring more pagetables in BL2 for ROMLIB build.
352 */
johpow019d134022021-06-16 17:57:28 -0500353#define ARM_MAP_RMM_DRAM MAP_REGION_FLAT( \
354 PLAT_ARM_RMM_BASE, \
Soby Mathew0338e9e2022-07-06 16:01:40 +0100355 (PLAT_ARM_RMM_SIZE + \
356 ARM_EL3_RMM_SHARED_SIZE), \
johpow019d134022021-06-16 17:57:28 -0500357 MT_MEMORY | MT_RW | MT_REALM)
Zelalem Awekec43c5632021-07-12 23:41:05 -0500358
359
johpow019d134022021-06-16 17:57:28 -0500360#define ARM_MAP_GPT_L1_DRAM MAP_REGION_FLAT( \
361 ARM_L1_GPT_ADDR_BASE, \
362 ARM_L1_GPT_SIZE, \
363 MT_MEMORY | MT_RW | EL3_PAS)
Zelalem Awekec43c5632021-07-12 23:41:05 -0500364
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +0000365#define ARM_MAP_EL3_RMM_SHARED_MEM \
366 MAP_REGION_FLAT( \
367 ARM_EL3_RMM_SHARED_BASE, \
368 ARM_EL3_RMM_SHARED_SIZE, \
369 MT_MEMORY | MT_RW | MT_REALM)
370
Zelalem Awekec43c5632021-07-12 23:41:05 -0500371#endif /* ENABLE_RME */
Achin Guptae97351d2019-10-11 15:15:19 +0100372
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100373/*
John Tsichritzisc34341a2018-07-30 13:41:52 +0100374 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to
375 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides
376 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order
377 * to be able to access the heap.
378 */
379#define ARM_MAP_BL1_RW MAP_REGION_FLAT( \
380 BL1_RW_BASE, \
381 BL1_RW_LIMIT - BL1_RW_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -0500382 MT_MEMORY | MT_RW | EL3_PAS)
John Tsichritzisc34341a2018-07-30 13:41:52 +0100383
384/*
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100385 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
386 * otherwise one region is defined containing both.
387 */
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100388#if SEPARATE_CODE_AND_RODATA
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100389#define ARM_MAP_BL_RO MAP_REGION_FLAT( \
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100390 BL_CODE_BASE, \
391 BL_CODE_END - BL_CODE_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -0500392 MT_CODE | EL3_PAS), \
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100393 MAP_REGION_FLAT( \
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100394 BL_RO_DATA_BASE, \
395 BL_RO_DATA_END \
396 - BL_RO_DATA_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -0500397 MT_RO_DATA | EL3_PAS)
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100398#else
399#define ARM_MAP_BL_RO MAP_REGION_FLAT( \
400 BL_CODE_BASE, \
401 BL_CODE_END - BL_CODE_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -0500402 MT_CODE | EL3_PAS)
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100403#endif
404#if USE_COHERENT_MEM
405#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
406 BL_COHERENT_RAM_BASE, \
407 BL_COHERENT_RAM_END \
408 - BL_COHERENT_RAM_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -0500409 MT_DEVICE | MT_RW | EL3_PAS)
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100410#endif
Roberto Vargase3adc372018-05-23 09:27:06 +0100411#if USE_ROMLIB
412#define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \
413 ROMLIB_RO_BASE, \
414 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\
Zelalem Aweke65e92632021-07-12 22:33:55 -0500415 MT_CODE | EL3_PAS)
Roberto Vargase3adc372018-05-23 09:27:06 +0100416
417#define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \
418 ROMLIB_RW_BASE, \
419 ROMLIB_RW_END - ROMLIB_RW_BASE,\
Zelalem Aweke65e92632021-07-12 22:33:55 -0500420 MT_MEMORY | MT_RW | EL3_PAS)
Roberto Vargase3adc372018-05-23 09:27:06 +0100421#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100422
Dan Handley9df48042015-03-19 18:58:55 +0000423/*
Antonio Nino Diaz48bfb542018-10-11 13:02:34 +0100424 * Map mem_protect flash region with read and write permissions
425 */
426#define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \
427 V2M_FLASH_BLOCK_SIZE, \
428 MT_DEVICE | MT_RW | MT_SECURE)
Manish V Badarkhe5e3ef6c2020-07-16 05:45:25 +0100429/*
430 * Map the region for device tree configuration with read and write permissions
431 */
432#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \
433 (ARM_FW_CONFIGS_LIMIT \
434 - ARM_BL_RAM_BASE), \
Zelalem Aweke65e92632021-07-12 22:33:55 -0500435 MT_MEMORY | MT_RW | EL3_PAS)
Zelalem Awekec43c5632021-07-12 23:41:05 -0500436/*
437 * Map L0_GPT with read and write permissions
438 */
439#if ENABLE_RME
440#define ARM_MAP_L0_GPT_REGION MAP_REGION_FLAT(ARM_L0_GPT_ADDR_BASE, \
441 ARM_L0_GPT_SIZE, \
442 MT_MEMORY | MT_RW | MT_ROOT)
443#endif
Antonio Nino Diaz48bfb542018-10-11 13:02:34 +0100444
445/*
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100446 * The max number of regions like RO(code), coherent and data required by
Dan Handley9df48042015-03-19 18:58:55 +0000447 * different BL stages which need to be mapped in the MMU.
448 */
Manish V Badarkhefc0b8532022-02-22 14:45:43 +0000449#define ARM_BL_REGIONS 7
Dan Handley9df48042015-03-19 18:58:55 +0000450
451#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
452 ARM_BL_REGIONS)
453
454/* Memory mapped Generic timer interfaces */
Gary Morrison3d7f6542021-01-27 13:08:47 -0600455#ifdef PLAT_ARM_SYS_CNTCTL_BASE
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600456#define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE
Gary Morrison3d7f6542021-01-27 13:08:47 -0600457#else
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100458#define ARM_SYS_CNTCTL_BASE UL(0x2a430000)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600459#endif
460
461#ifdef PLAT_ARM_SYS_CNTREAD_BASE
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600462#define ARM_SYS_CNTREAD_BASE PLAT_ARM_SYS_CNTREAD_BASE
Gary Morrison3d7f6542021-01-27 13:08:47 -0600463#else
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100464#define ARM_SYS_CNTREAD_BASE UL(0x2a800000)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600465#endif
466
467#ifdef PLAT_ARM_SYS_TIMCTL_BASE
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600468#define ARM_SYS_TIMCTL_BASE PLAT_ARM_SYS_TIMCTL_BASE
Gary Morrison3d7f6542021-01-27 13:08:47 -0600469#else
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100470#define ARM_SYS_TIMCTL_BASE UL(0x2a810000)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600471#endif
472
473#ifdef PLAT_ARM_SYS_CNT_BASE_S
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600474#define ARM_SYS_CNT_BASE_S PLAT_ARM_SYS_CNT_BASE_S
Gary Morrison3d7f6542021-01-27 13:08:47 -0600475#else
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100476#define ARM_SYS_CNT_BASE_S UL(0x2a820000)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600477#endif
478
479#ifdef PLAT_ARM_SYS_CNT_BASE_NS
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600480#define ARM_SYS_CNT_BASE_NS PLAT_ARM_SYS_CNT_BASE_NS
Gary Morrison3d7f6542021-01-27 13:08:47 -0600481#else
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100482#define ARM_SYS_CNT_BASE_NS UL(0x2a830000)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600483#endif
Dan Handley9df48042015-03-19 18:58:55 +0000484
485#define ARM_CONSOLE_BAUDRATE 115200
486
Juan Castillob6132f12015-10-06 14:01:35 +0100487/* Trusted Watchdog constants */
Gary Morrison3d7f6542021-01-27 13:08:47 -0600488#ifdef PLAT_ARM_SP805_TWDG_BASE
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600489#define ARM_SP805_TWDG_BASE PLAT_ARM_SP805_TWDG_BASE
Gary Morrison3d7f6542021-01-27 13:08:47 -0600490#else
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100491#define ARM_SP805_TWDG_BASE UL(0x2a490000)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600492#endif
Juan Castillob6132f12015-10-06 14:01:35 +0100493#define ARM_SP805_TWDG_CLK_HZ 32768
494/* The TBBR document specifies a watchdog timeout of 256 seconds. SP805
495 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */
496#define ARM_TWDG_TIMEOUT_SEC 128
497#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \
498 ARM_TWDG_TIMEOUT_SEC)
499
Dan Handley9df48042015-03-19 18:58:55 +0000500/******************************************************************************
501 * Required platform porting definitions common to all ARM standard platforms
502 *****************************************************************************/
503
Roberto Vargasf8fda102017-08-08 11:27:20 +0100504/*
Soby Mathewfec4eb72015-07-01 16:16:20 +0100505 * This macro defines the deepest retention state possible. A higher state
506 * id will represent an invalid or a power down state.
507 */
508#define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET
509
510/*
511 * This macro defines the deepest power down states possible. Any state ID
512 * higher than this is invalid.
513 */
514#define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF
515
Dan Handley9df48042015-03-19 18:58:55 +0000516/*
517 * Some data must be aligned on the biggest cache line size in the platform.
518 * This is known only to the platform as it might have a combination of
519 * integrated and external caches.
520 */
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100521#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT)
Dan Handley9df48042015-03-19 18:58:55 +0000522
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000523/*
Manish V Badarkhe1da211a2020-05-31 10:17:59 +0100524 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000525 * and limit. Leave enough space of BL2 meminfo.
526 */
Manish V Badarkhe1da211a2020-05-31 10:17:59 +0100527#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
Manish V Badarkhe0bafa822020-06-29 11:14:07 +0100528#define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \
529 + (PAGE_SIZE / 2U))
Sathees Balya90950092018-11-15 14:22:30 +0000530
531/*
532 * Boot parameters passed from BL2 to BL31/BL32 are stored here
533 */
Manish V Badarkhe0bafa822020-06-29 11:14:07 +0100534#define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT)
535#define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \
536 + (PAGE_SIZE / 2U))
Sathees Balya90950092018-11-15 14:22:30 +0000537
538/*
539 * Define limit of firmware configuration memory:
Manish V Badarkhe1da211a2020-05-31 10:17:59 +0100540 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory
Sathees Balya90950092018-11-15 14:22:30 +0000541 */
Manish V Badarkhefbf1fd22020-06-09 11:31:17 +0100542#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2))
Dan Handley9df48042015-03-19 18:58:55 +0000543
Zelalem Awekec43c5632021-07-12 23:41:05 -0500544#if ENABLE_RME
545/*
546 * Store the L0 GPT on Trusted SRAM next to firmware
547 * configuration memory, 4KB aligned.
548 */
549#define ARM_L0_GPT_SIZE (PAGE_SIZE)
550#define ARM_L0_GPT_ADDR_BASE (ARM_FW_CONFIGS_LIMIT)
551#define ARM_L0_GPT_LIMIT (ARM_L0_GPT_ADDR_BASE + ARM_L0_GPT_SIZE)
552#else
553#define ARM_L0_GPT_SIZE U(0)
554#endif
555
Dan Handley9df48042015-03-19 18:58:55 +0000556/*******************************************************************************
557 * BL1 specific defines.
558 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
559 * addresses.
560 ******************************************************************************/
561#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600562#ifdef PLAT_BL1_RO_LIMIT
563#define BL1_RO_LIMIT PLAT_BL1_RO_LIMIT
564#else
Dan Handley9df48042015-03-19 18:58:55 +0000565#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \
Roberto Vargase3adc372018-05-23 09:27:06 +0100566 + (PLAT_ARM_TRUSTED_ROM_SIZE - \
567 PLAT_ARM_MAX_ROMLIB_RO_SIZE))
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600568#endif
569
Dan Handley9df48042015-03-19 18:58:55 +0000570/*
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000571 * Put BL1 RW at the top of the Trusted SRAM.
Dan Handley9df48042015-03-19 18:58:55 +0000572 */
Dan Handley9df48042015-03-19 18:58:55 +0000573#define BL1_RW_BASE (ARM_BL_RAM_BASE + \
574 ARM_BL_RAM_SIZE - \
Roberto Vargase3adc372018-05-23 09:27:06 +0100575 (PLAT_ARM_MAX_BL1_RW_SIZE +\
576 PLAT_ARM_MAX_ROMLIB_RW_SIZE))
577#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \
578 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE))
579
580#define ROMLIB_RO_BASE BL1_RO_LIMIT
581#define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE)
582
583#define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE)
584#define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE)
Dan Handley9df48042015-03-19 18:58:55 +0000585
586/*******************************************************************************
587 * BL2 specific defines.
588 ******************************************************************************/
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600589#if RESET_TO_BL2
Manish V Badarkhe103569f2022-06-13 18:23:01 +0100590#if ENABLE_PIE
591/*
592 * As the BL31 image size appears to be increased when built with the ENABLE_PIE
593 * option, set BL2 base address to have enough space for BL31 in Trusted SRAM.
594 */
595#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \
596 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \
597 0x3000)
598#else
Dimitris Papastamos25836492018-06-11 11:07:58 +0100599/* Put BL2 towards the middle of the Trusted SRAM */
Soby Mathewaf14b462018-06-01 16:53:38 +0100600#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \
Manish V Badarkhe103569f2022-06-13 18:23:01 +0100601 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \
602 0x2000)
603#endif /* ENABLE_PIE */
Roberto Vargas52207802017-11-17 13:22:18 +0000604#define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
605
David Wang0ba499f2016-03-07 11:02:57 +0800606#else
Dan Handley9df48042015-03-19 18:58:55 +0000607/*
Soby Mathewaf14b462018-06-01 16:53:38 +0100608 * Put BL2 just below BL1.
Dan Handley9df48042015-03-19 18:58:55 +0000609 */
Soby Mathewaf14b462018-06-01 16:53:38 +0100610#define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
611#define BL2_LIMIT BL1_RW_BASE
David Wang0ba499f2016-03-07 11:02:57 +0800612#endif
Dan Handley9df48042015-03-19 18:58:55 +0000613
614/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000615 * BL31 specific defines.
Dan Handley9df48042015-03-19 18:58:55 +0000616 ******************************************************************************/
Madhukar Pappireddyd7419442020-01-27 15:38:26 -0600617#if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION
David Wang0ba499f2016-03-07 11:02:57 +0800618/*
619 * Put BL31 at the bottom of TZC secured DRAM
620 */
621#define BL31_BASE ARM_AP_TZC_DRAM1_BASE
622#define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
623 PLAT_ARM_MAX_BL31_SIZE)
Madhukar Pappireddyd7419442020-01-27 15:38:26 -0600624/*
625 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM.
626 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten.
627 */
628#if SEPARATE_NOBITS_REGION
629#define BL31_NOBITS_BASE BL2_BASE
630#define BL31_NOBITS_LIMIT BL2_LIMIT
631#endif /* SEPARATE_NOBITS_REGION */
Qixiang Xua5f72812017-08-31 11:45:32 +0800632#elif (RESET_TO_BL31)
Manish Pandey2207e932019-11-06 13:17:46 +0000633/* Ensure Position Independent support (PIE) is enabled for this config.*/
634# if !ENABLE_PIE
635# error "BL31 must be a PIE if RESET_TO_BL31=1."
636#endif
Qixiang Xua5f72812017-08-31 11:45:32 +0800637/*
Soby Mathew68e69282018-12-12 14:13:52 +0000638 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely
Soby Mathewc5e17452019-01-07 14:07:58 +0000639 * used for building BL31 and not used for loading BL31.
Qixiang Xua5f72812017-08-31 11:45:32 +0800640 */
Soby Mathewc5e17452019-01-07 14:07:58 +0000641# define BL31_BASE 0x0
642# define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE
David Wang0ba499f2016-03-07 11:02:57 +0800643#else
Soby Mathewaf14b462018-06-01 16:53:38 +0100644/* Put BL31 below BL2 in the Trusted SRAM.*/
645#define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
646 - PLAT_ARM_MAX_BL31_SIZE)
647#define BL31_PROGBITS_LIMIT BL2_BASE
Dimitris Papastamos25836492018-06-11 11:07:58 +0100648/*
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600649 * For RESET_TO_BL2 make sure the BL31 can grow up until BL2_BASE.
650 * This is because in the RESET_TO_BL2 configuration,
651 * BL2 is always resident.
Dimitris Papastamos25836492018-06-11 11:07:58 +0100652 */
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600653#if RESET_TO_BL2
Dimitris Papastamos25836492018-06-11 11:07:58 +0100654#define BL31_LIMIT BL2_BASE
655#else
Dan Handley9df48042015-03-19 18:58:55 +0000656#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
David Wang0ba499f2016-03-07 11:02:57 +0800657#endif
Zelalem Awekec43c5632021-07-12 23:41:05 -0500658#endif
659
660/******************************************************************************
661 * RMM specific defines
662 *****************************************************************************/
663#if ENABLE_RME
664#define RMM_BASE (ARM_REALM_BASE)
665#define RMM_LIMIT (RMM_BASE + ARM_REALM_SIZE)
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +0000666#define RMM_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE)
667#define RMM_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE)
Dimitris Papastamos25836492018-06-11 11:07:58 +0100668#endif
Dan Handley9df48042015-03-19 18:58:55 +0000669
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700670#if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME
Dan Handley9df48042015-03-19 18:58:55 +0000671/*******************************************************************************
Soby Mathewbf169232017-11-14 14:10:10 +0000672 * BL32 specific defines for EL3 runtime in AArch32 mode
673 ******************************************************************************/
674# if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME
Manish Pandey928da862021-06-10 15:22:48 +0100675/* Ensure Position Independent support (PIE) is enabled for this config.*/
676# if !ENABLE_PIE
677# error "BL32 must be a PIE if RESET_TO_SP_MIN=1."
678#endif
Soby Mathewaf14b462018-06-01 16:53:38 +0100679/*
Manish Pandey928da862021-06-10 15:22:48 +0100680 * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely
681 * used for building BL32 and not used for loading BL32.
Soby Mathewaf14b462018-06-01 16:53:38 +0100682 */
Manish Pandey928da862021-06-10 15:22:48 +0100683# define BL32_BASE 0x0
684# define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE
Soby Mathewbf169232017-11-14 14:10:10 +0000685# else
Soby Mathewaf14b462018-06-01 16:53:38 +0100686/* Put BL32 below BL2 in the Trusted SRAM.*/
687# define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
688 - PLAT_ARM_MAX_BL32_SIZE)
689# define BL32_PROGBITS_LIMIT BL2_BASE
Soby Mathewbf169232017-11-14 14:10:10 +0000690# define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
691# endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */
692
693#else
694/*******************************************************************************
695 * BL32 specific defines for EL3 runtime in AArch64 mode
Dan Handley9df48042015-03-19 18:58:55 +0000696 ******************************************************************************/
697/*
698 * On ARM standard platforms, the TSP can execute from Trusted SRAM,
699 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone
700 * controller.
701 */
Marc Bonnicif5867002021-12-20 10:53:52 +0000702# if SPM_MM || SPMC_AT_EL3
Soby Mathewbf169232017-11-14 14:10:10 +0000703# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
704# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000))
705# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
706# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000707 ARM_AP_TZC_DRAM1_SIZE)
Achin Guptae97351d2019-10-11 15:15:19 +0100708# elif defined(SPD_spmd)
709# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
710# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000))
Arunachalam Ganapathy40618cf2020-07-27 13:51:30 +0100711# define BL32_BASE PLAT_ARM_SPMC_BASE
712# define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \
713 PLAT_ARM_SPMC_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000714# elif ARM_BL31_IN_DRAM
715# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \
David Wang0ba499f2016-03-07 11:02:57 +0800716 PLAT_ARM_MAX_BL31_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000717# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \
David Wang0ba499f2016-03-07 11:02:57 +0800718 PLAT_ARM_MAX_BL31_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000719# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \
David Wang0ba499f2016-03-07 11:02:57 +0800720 PLAT_ARM_MAX_BL31_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000721# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
David Wang0ba499f2016-03-07 11:02:57 +0800722 ARM_AP_TZC_DRAM1_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000723# elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID
724# define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE
725# define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE
Soby Mathewaf14b462018-06-01 16:53:38 +0100726# define TSP_PROGBITS_LIMIT BL31_BASE
Manish V Badarkhe1da211a2020-05-31 10:17:59 +0100727# define BL32_BASE ARM_FW_CONFIGS_LIMIT
Soby Mathewbf169232017-11-14 14:10:10 +0000728# define BL32_LIMIT BL31_BASE
729# elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID
730# define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE
731# define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE
732# define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE
733# define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \
Manish V Badarkhe5a4f9b82023-04-30 09:25:15 +0100734 + SZ_4M)
Soby Mathewbf169232017-11-14 14:10:10 +0000735# elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
736# define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE
737# define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE
738# define BL32_BASE ARM_AP_TZC_DRAM1_BASE
739# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
Dan Handley9df48042015-03-19 18:58:55 +0000740 ARM_AP_TZC_DRAM1_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000741# else
742# error "Unsupported ARM_TSP_RAM_LOCATION_ID value"
743# endif
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700744#endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */
Dan Handley9df48042015-03-19 18:58:55 +0000745
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000746/*
747 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no
Marc Bonnicif5867002021-12-20 10:53:52 +0000748 * SPD and no SPM-MM and no SPMC-AT-EL3, as they are the only ones that can be
749 * used as BL32.
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000750 */
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700751#if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME
Marc Bonnicif5867002021-12-20 10:53:52 +0000752# if defined(SPD_none) && !SPM_MM && !SPMC_AT_EL3
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000753# undef BL32_BASE
Marc Bonnicif5867002021-12-20 10:53:52 +0000754# endif /* defined(SPD_none) && !SPM_MM || !SPMC_AT_EL3 */
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700755#endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100756
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100757/*******************************************************************************
758 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines.
759 ******************************************************************************/
760#define BL2U_BASE BL2_BASE
Soby Mathewbf169232017-11-14 14:10:10 +0000761#define BL2U_LIMIT BL2_LIMIT
762
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100763#define NS_BL2U_BASE ARM_NS_DRAM1_BASE
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +0000764#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000))
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100765
Dan Handley9df48042015-03-19 18:58:55 +0000766/*
767 * ID of the secure physical generic timer interrupt used by the TSP.
768 */
769#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
770
771
Vikram Kanigirid79214c2015-09-09 10:52:13 +0100772/*
773 * One cache line needed for bakery locks on ARM platforms
774 */
775#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
776
Jeenu Viswambharanb1837452017-10-24 11:47:13 +0100777/* Priority levels for ARM platforms */
Jeenu Viswambharana5b5b8d2018-02-06 12:21:39 +0000778#define PLAT_RAS_PRI 0x10
Jeenu Viswambharanb1837452017-10-24 11:47:13 +0100779#define PLAT_SDEI_CRITICAL_PRI 0x60
780#define PLAT_SDEI_NORMAL_PRI 0x70
781
782/* ARM platforms use 3 upper bits of secure interrupt priority */
Sandeep Tripathy1c478392020-08-12 18:42:13 +0530783#define PLAT_PRI_BITS 3
Vikram Kanigirid79214c2015-09-09 10:52:13 +0100784
Jeenu Viswambharana5acc0a2017-09-22 08:32:10 +0100785/* SGI used for SDEI signalling */
786#define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0
787
Balint Dobszayd0dbd5e2019-12-18 15:28:00 +0100788#if SDEI_IN_FCONF
789/* ARM SDEI dynamic private event max count */
790#define ARM_SDEI_DP_EVENT_MAX_CNT 3
791
792/* ARM SDEI dynamic shared event max count */
793#define ARM_SDEI_DS_EVENT_MAX_CNT 3
794#else
Jeenu Viswambharana5acc0a2017-09-22 08:32:10 +0100795/* ARM SDEI dynamic private event numbers */
796#define ARM_SDEI_DP_EVENT_0 1000
797#define ARM_SDEI_DP_EVENT_1 1001
798#define ARM_SDEI_DP_EVENT_2 1002
799
800/* ARM SDEI dynamic shared event numbers */
801#define ARM_SDEI_DS_EVENT_0 2000
802#define ARM_SDEI_DS_EVENT_1 2001
803#define ARM_SDEI_DS_EVENT_2 2002
804
Jeenu Viswambharan6e284462017-12-08 10:38:24 +0000805#define ARM_SDEI_PRIVATE_EVENTS \
806 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \
807 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
808 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
809 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
810
811#define ARM_SDEI_SHARED_EVENTS \
812 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
813 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
814 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
Balint Dobszayd0dbd5e2019-12-18 15:28:00 +0100815#endif /* SDEI_IN_FCONF */
Jeenu Viswambharan6e284462017-12-08 10:38:24 +0000816
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100817#endif /* ARM_DEF_H */