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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Manish V Badarkhefc0b8532022-02-22 14:45:43 +00002 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01006#ifndef ARM_DEF_H
7#define ARM_DEF_H
Dan Handley9df48042015-03-19 18:58:55 +00008
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009#include <arch.h>
10#include <common/interrupt_props.h>
11#include <common/tbbr/tbbr_img_def.h>
12#include <drivers/arm/gic_common.h>
13#include <lib/utils_def.h>
14#include <lib/xlat_tables/xlat_tables_defs.h>
Manish V Badarkhe55861512020-03-27 13:25:51 +000015#include <plat/arm/common/smccc_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <plat/common/common_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000017
18/******************************************************************************
19 * Definitions common to all ARM standard platforms
20 *****************************************************************************/
21
Max Shvetsov06dba292019-12-06 11:50:12 +000022/*
23 * Root of trust key hash lengths
24 */
25#define ARM_ROTPK_HEADER_LEN 19
26#define ARM_ROTPK_HASH_LEN 32
27
Juan Castillo7d199412015-12-14 09:35:25 +000028/* Special value used to verify platform parameters from BL2 to BL31 */
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +000029#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978)
Dan Handley9df48042015-03-19 18:58:55 +000030
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -060031#define ARM_SYSTEM_COUNT U(1)
Dan Handley9df48042015-03-19 18:58:55 +000032
33#define ARM_CACHE_WRITEBACK_SHIFT 6
34
Soby Mathewfec4eb72015-07-01 16:16:20 +010035/*
36 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
37 * power levels have a 1:1 mapping with the MPIDR affinity levels.
38 */
39#define ARM_PWR_LVL0 MPIDR_AFFLVL0
40#define ARM_PWR_LVL1 MPIDR_AFFLVL1
Soby Mathewa869de12015-05-08 10:18:59 +010041#define ARM_PWR_LVL2 MPIDR_AFFLVL2
Chandni Cherukuri9ec4a112018-10-16 14:42:19 +053042#define ARM_PWR_LVL3 MPIDR_AFFLVL3
Soby Mathewfec4eb72015-07-01 16:16:20 +010043
44/*
45 * Macros for local power states in ARM platforms encoded by State-ID field
46 * within the power-state parameter.
47 */
48/* Local power state for power domains in Run state. */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010049#define ARM_LOCAL_STATE_RUN U(0)
Soby Mathewfec4eb72015-07-01 16:16:20 +010050/* Local power state for retention. Valid only for CPU power domains */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010051#define ARM_LOCAL_STATE_RET U(1)
Soby Mathewfec4eb72015-07-01 16:16:20 +010052/* Local power state for OFF/power-down. Valid for CPU and cluster power
53 domains */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010054#define ARM_LOCAL_STATE_OFF U(2)
Soby Mathewfec4eb72015-07-01 16:16:20 +010055
Dan Handley9df48042015-03-19 18:58:55 +000056/* Memory location options for TSP */
57#define ARM_TRUSTED_SRAM_ID 0
58#define ARM_TRUSTED_DRAM_ID 1
59#define ARM_DRAM_ID 2
60
Gary Morrison3d7f6542021-01-27 13:08:47 -060061#ifdef PLAT_ARM_TRUSTED_SRAM_BASE
laurenw-arm7c7b1982020-10-21 13:34:40 -050062#define ARM_TRUSTED_SRAM_BASE PLAT_ARM_TRUSTED_SRAM_BASE
63#else
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010064#define ARM_TRUSTED_SRAM_BASE UL(0x04000000)
Gary Morrison3d7f6542021-01-27 13:08:47 -060065#endif /* PLAT_ARM_TRUSTED_SRAM_BASE */
laurenw-arm7c7b1982020-10-21 13:34:40 -050066
Dan Handley9df48042015-03-19 18:58:55 +000067#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010068#define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */
Dan Handley9df48042015-03-19 18:58:55 +000069
70/* The remaining Trusted SRAM is used to load the BL images */
71#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \
72 ARM_SHARED_RAM_SIZE)
73#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
74 ARM_SHARED_RAM_SIZE)
75
76/*
Zelalem Awekec43c5632021-07-12 23:41:05 -050077 * The top 16MB (or 64MB if RME is enabled) of DRAM1 is configured as
78 * follows:
Dan Handley9df48042015-03-19 18:58:55 +000079 * - SCP TZC DRAM: If present, DRAM reserved for SCP use
Zelalem Awekec43c5632021-07-12 23:41:05 -050080 * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled
81 * - REALM DRAM: Reserved for Realm world if RME is enabled
Dan Handley9df48042015-03-19 18:58:55 +000082 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use
Zelalem Awekec43c5632021-07-12 23:41:05 -050083 *
johpow019d134022021-06-16 17:57:28 -050084 * RME enabled(64MB) RME not enabled(16MB)
85 * -------------------- -------------------
86 * | | | |
87 * | AP TZC (~28MB) | | AP TZC (~14MB) |
88 * -------------------- -------------------
89 * | | | |
90 * | REALM (32MB) | | EL3 TZC (2MB) |
91 * -------------------- -------------------
92 * | | | |
93 * | EL3 TZC (3MB) | | SCP TZC |
94 * -------------------- 0xFFFF_FFFF-------------------
95 * | L1 GPT + SCP TZC |
96 * | (~1MB) |
Zelalem Awekec43c5632021-07-12 23:41:05 -050097 * 0xFFFF_FFFF --------------------
Dan Handley9df48042015-03-19 18:58:55 +000098 */
Zelalem Awekec43c5632021-07-12 23:41:05 -050099#if ENABLE_RME
100#define ARM_TZC_DRAM1_SIZE UL(0x04000000) /* 64MB */
101/*
102 * Define a region within the TZC secured DRAM for use by EL3 runtime
103 * firmware. This region is meant to be NOLOAD and will not be zero
104 * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be
105 * placed here. 3MB region is reserved if RME is enabled, 2MB otherwise.
106 */
107#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00300000) /* 3MB */
108#define ARM_L1_GPT_SIZE UL(0x00100000) /* 1MB */
109#define ARM_REALM_SIZE UL(0x02000000) /* 32MB */
110#else
111#define ARM_TZC_DRAM1_SIZE UL(0x01000000) /* 16MB */
112#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2MB */
113#define ARM_L1_GPT_SIZE UL(0)
114#define ARM_REALM_SIZE UL(0)
115#endif /* ENABLE_RME */
Dan Handley9df48042015-03-19 18:58:55 +0000116
117#define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
Zelalem Awekec43c5632021-07-12 23:41:05 -0500118 ARM_DRAM1_SIZE - \
119 (ARM_SCP_TZC_DRAM1_SIZE + \
120 ARM_L1_GPT_SIZE))
Dan Handley9df48042015-03-19 18:58:55 +0000121#define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE
122#define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \
Zelalem Awekec43c5632021-07-12 23:41:05 -0500123 ARM_SCP_TZC_DRAM1_SIZE - 1U)
124#if ENABLE_RME
125#define ARM_L1_GPT_ADDR_BASE (ARM_DRAM1_BASE + \
126 ARM_DRAM1_SIZE - \
127 ARM_L1_GPT_SIZE)
128#define ARM_L1_GPT_END (ARM_L1_GPT_ADDR_BASE + \
129 ARM_L1_GPT_SIZE - 1U)
Dan Handley9df48042015-03-19 18:58:55 +0000130
Zelalem Awekec43c5632021-07-12 23:41:05 -0500131#define ARM_REALM_BASE (ARM_DRAM1_BASE + \
132 ARM_DRAM1_SIZE - \
133 (ARM_SCP_TZC_DRAM1_SIZE + \
134 ARM_EL3_TZC_DRAM1_SIZE + \
135 ARM_REALM_SIZE + \
136 ARM_L1_GPT_SIZE))
137#define ARM_REALM_END (ARM_REALM_BASE + ARM_REALM_SIZE - 1U)
138#endif /* ENABLE_RME */
139
140#define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \
141 ARM_EL3_TZC_DRAM1_SIZE)
Soby Mathew3b5156e2017-10-05 12:27:33 +0100142#define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \
Alexei Fedorovc7176172020-07-13 12:11:05 +0100143 ARM_EL3_TZC_DRAM1_SIZE - 1U)
Soby Mathew3b5156e2017-10-05 12:27:33 +0100144
Dan Handley9df48042015-03-19 18:58:55 +0000145#define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
Zelalem Awekec43c5632021-07-12 23:41:05 -0500146 ARM_DRAM1_SIZE - \
147 ARM_TZC_DRAM1_SIZE)
Dan Handley9df48042015-03-19 18:58:55 +0000148#define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \
Zelalem Awekec43c5632021-07-12 23:41:05 -0500149 (ARM_SCP_TZC_DRAM1_SIZE + \
150 ARM_EL3_TZC_DRAM1_SIZE + \
151 ARM_REALM_SIZE + \
152 ARM_L1_GPT_SIZE))
Dan Handley9df48042015-03-19 18:58:55 +0000153#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \
Zelalem Awekec43c5632021-07-12 23:41:05 -0500154 ARM_AP_TZC_DRAM1_SIZE - 1U)
Dan Handley9df48042015-03-19 18:58:55 +0000155
Soby Mathew7e4d6652017-05-10 11:50:30 +0100156/* Define the Access permissions for Secure peripherals to NS_DRAM */
157#if ARM_CRYPTOCELL_INTEG
158/*
159 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell.
160 * This is required by CryptoCell to authenticate BL33 which is loaded
161 * into the Non Secure DDR.
162 */
163#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD
164#else
165#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE
166#endif
167
Summer Qin9db8f2e2017-04-24 16:49:28 +0100168#ifdef SPD_opteed
169/*
Jens Wiklanderae73b162017-08-24 15:39:09 +0200170 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to
171 * load/authenticate the trusted os extra image. The first 512KB of
172 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading
173 * for OPTEE is paged image which only include the paging part using
174 * virtual memory but without "init" data. OPTEE will copy the "init" data
175 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the
176 * extra image behind the "init" data.
Summer Qin9db8f2e2017-04-24 16:49:28 +0100177 */
Jens Wiklanderae73b162017-08-24 15:39:09 +0200178#define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \
179 ARM_AP_TZC_DRAM1_SIZE - \
180 ARM_OPTEE_PAGEABLE_LOAD_SIZE)
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100181#define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000)
Summer Qin9db8f2e2017-04-24 16:49:28 +0100182#define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \
183 ARM_OPTEE_PAGEABLE_LOAD_BASE, \
184 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \
185 MT_MEMORY | MT_RW | MT_SECURE)
Soby Mathew874fc9e2017-09-01 13:43:50 +0100186
187/*
188 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging
189 * support is enabled).
190 */
191#define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \
192 BL32_BASE, \
193 BL32_LIMIT - BL32_BASE, \
194 MT_MEMORY | MT_RW | MT_SECURE)
Summer Qin9db8f2e2017-04-24 16:49:28 +0100195#endif /* SPD_opteed */
Dan Handley9df48042015-03-19 18:58:55 +0000196
197#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
198#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
199 ARM_TZC_DRAM1_SIZE)
200#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
Alexei Fedorovc7176172020-07-13 12:11:05 +0100201 ARM_NS_DRAM1_SIZE - 1U)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600202#ifdef PLAT_ARM_DRAM1_BASE
laurenw-arm7c7b1982020-10-21 13:34:40 -0500203#define ARM_DRAM1_BASE PLAT_ARM_DRAM1_BASE
204#else
Sandrine Bailleux6c32fc72018-10-31 14:28:17 +0100205#define ARM_DRAM1_BASE ULL(0x80000000)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600206#endif /* PLAT_ARM_DRAM1_BASE */
laurenw-arm7c7b1982020-10-21 13:34:40 -0500207
Sandrine Bailleux6c32fc72018-10-31 14:28:17 +0100208#define ARM_DRAM1_SIZE ULL(0x80000000)
Dan Handley9df48042015-03-19 18:58:55 +0000209#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
Alexei Fedorovc7176172020-07-13 12:11:05 +0100210 ARM_DRAM1_SIZE - 1U)
Dan Handley9df48042015-03-19 18:58:55 +0000211
Sami Mujawara43ae7c2019-05-09 13:35:02 +0100212#define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE
Dan Handley9df48042015-03-19 18:58:55 +0000213#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE
214#define ARM_DRAM2_END (ARM_DRAM2_BASE + \
Alexei Fedorovc7176172020-07-13 12:11:05 +0100215 ARM_DRAM2_SIZE - 1U)
Dan Handley9df48042015-03-19 18:58:55 +0000216
217#define ARM_IRQ_SEC_PHY_TIMER 29
218
219#define ARM_IRQ_SEC_SGI_0 8
220#define ARM_IRQ_SEC_SGI_1 9
221#define ARM_IRQ_SEC_SGI_2 10
222#define ARM_IRQ_SEC_SGI_3 11
223#define ARM_IRQ_SEC_SGI_4 12
224#define ARM_IRQ_SEC_SGI_5 13
225#define ARM_IRQ_SEC_SGI_6 14
226#define ARM_IRQ_SEC_SGI_7 15
227
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000228/*
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100229 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
230 * terminology. On a GICv2 system or mode, the lists will be merged and treated
231 * as Group 0 interrupts.
232 */
233#define ARM_G1S_IRQ_PROPS(grp) \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100234 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100235 GIC_INTR_CFG_LEVEL), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100236 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100237 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100238 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100239 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100240 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100241 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100242 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100243 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100244 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100245 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100246 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100247 GIC_INTR_CFG_EDGE)
248
249#define ARM_G0_IRQ_PROPS(grp) \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100250 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100251 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100252 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100253 GIC_INTR_CFG_EDGE)
254
johpow019d134022021-06-16 17:57:28 -0500255#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
256 ARM_SHARED_RAM_BASE, \
257 ARM_SHARED_RAM_SIZE, \
258 MT_DEVICE | MT_RW | EL3_PAS)
Dan Handley9df48042015-03-19 18:58:55 +0000259
johpow019d134022021-06-16 17:57:28 -0500260#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
261 ARM_NS_DRAM1_BASE, \
262 ARM_NS_DRAM1_SIZE, \
263 MT_MEMORY | MT_RW | MT_NS)
Dan Handley9df48042015-03-19 18:58:55 +0000264
johpow019d134022021-06-16 17:57:28 -0500265#define ARM_MAP_DRAM2 MAP_REGION_FLAT( \
266 ARM_DRAM2_BASE, \
267 ARM_DRAM2_SIZE, \
268 MT_MEMORY | MT_RW | MT_NS)
Roberto Vargasf8fda102017-08-08 11:27:20 +0100269
johpow019d134022021-06-16 17:57:28 -0500270#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \
271 TSP_SEC_MEM_BASE, \
272 TSP_SEC_MEM_SIZE, \
273 MT_MEMORY | MT_RW | MT_SECURE)
Dan Handley9df48042015-03-19 18:58:55 +0000274
David Wang0ba499f2016-03-07 11:02:57 +0800275#if ARM_BL31_IN_DRAM
johpow019d134022021-06-16 17:57:28 -0500276#define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \
277 BL31_BASE, \
278 PLAT_ARM_MAX_BL31_SIZE, \
279 MT_MEMORY | MT_RW | MT_SECURE)
David Wang0ba499f2016-03-07 11:02:57 +0800280#endif
Dan Handley9df48042015-03-19 18:58:55 +0000281
johpow019d134022021-06-16 17:57:28 -0500282#define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \
283 ARM_EL3_TZC_DRAM1_BASE, \
284 ARM_EL3_TZC_DRAM1_SIZE, \
285 MT_MEMORY | MT_RW | EL3_PAS)
Soby Mathew3b5156e2017-10-05 12:27:33 +0100286
johpow019d134022021-06-16 17:57:28 -0500287#define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \
288 PLAT_ARM_TRUSTED_DRAM_BASE, \
289 PLAT_ARM_TRUSTED_DRAM_SIZE, \
290 MT_MEMORY | MT_RW | MT_SECURE)
Achin Guptae97351d2019-10-11 15:15:19 +0100291
Zelalem Awekec43c5632021-07-12 23:41:05 -0500292#if ENABLE_RME
johpow019d134022021-06-16 17:57:28 -0500293#define ARM_MAP_RMM_DRAM MAP_REGION_FLAT( \
294 PLAT_ARM_RMM_BASE, \
295 PLAT_ARM_RMM_SIZE, \
296 MT_MEMORY | MT_RW | MT_REALM)
Zelalem Awekec43c5632021-07-12 23:41:05 -0500297
298
johpow019d134022021-06-16 17:57:28 -0500299#define ARM_MAP_GPT_L1_DRAM MAP_REGION_FLAT( \
300 ARM_L1_GPT_ADDR_BASE, \
301 ARM_L1_GPT_SIZE, \
302 MT_MEMORY | MT_RW | EL3_PAS)
Zelalem Awekec43c5632021-07-12 23:41:05 -0500303
304#endif /* ENABLE_RME */
Achin Guptae97351d2019-10-11 15:15:19 +0100305
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100306/*
John Tsichritzisc34341a2018-07-30 13:41:52 +0100307 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to
308 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides
309 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order
310 * to be able to access the heap.
311 */
312#define ARM_MAP_BL1_RW MAP_REGION_FLAT( \
313 BL1_RW_BASE, \
314 BL1_RW_LIMIT - BL1_RW_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -0500315 MT_MEMORY | MT_RW | EL3_PAS)
John Tsichritzisc34341a2018-07-30 13:41:52 +0100316
317/*
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100318 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
319 * otherwise one region is defined containing both.
320 */
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100321#if SEPARATE_CODE_AND_RODATA
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100322#define ARM_MAP_BL_RO MAP_REGION_FLAT( \
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100323 BL_CODE_BASE, \
324 BL_CODE_END - BL_CODE_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -0500325 MT_CODE | EL3_PAS), \
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100326 MAP_REGION_FLAT( \
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100327 BL_RO_DATA_BASE, \
328 BL_RO_DATA_END \
329 - BL_RO_DATA_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -0500330 MT_RO_DATA | EL3_PAS)
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100331#else
332#define ARM_MAP_BL_RO MAP_REGION_FLAT( \
333 BL_CODE_BASE, \
334 BL_CODE_END - BL_CODE_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -0500335 MT_CODE | EL3_PAS)
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100336#endif
337#if USE_COHERENT_MEM
338#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
339 BL_COHERENT_RAM_BASE, \
340 BL_COHERENT_RAM_END \
341 - BL_COHERENT_RAM_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -0500342 MT_DEVICE | MT_RW | EL3_PAS)
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100343#endif
Roberto Vargase3adc372018-05-23 09:27:06 +0100344#if USE_ROMLIB
345#define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \
346 ROMLIB_RO_BASE, \
347 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\
Zelalem Aweke65e92632021-07-12 22:33:55 -0500348 MT_CODE | EL3_PAS)
Roberto Vargase3adc372018-05-23 09:27:06 +0100349
350#define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \
351 ROMLIB_RW_BASE, \
352 ROMLIB_RW_END - ROMLIB_RW_BASE,\
Zelalem Aweke65e92632021-07-12 22:33:55 -0500353 MT_MEMORY | MT_RW | EL3_PAS)
Roberto Vargase3adc372018-05-23 09:27:06 +0100354#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100355
Dan Handley9df48042015-03-19 18:58:55 +0000356/*
Antonio Nino Diaz48bfb542018-10-11 13:02:34 +0100357 * Map mem_protect flash region with read and write permissions
358 */
359#define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \
360 V2M_FLASH_BLOCK_SIZE, \
361 MT_DEVICE | MT_RW | MT_SECURE)
Manish V Badarkhe5e3ef6c2020-07-16 05:45:25 +0100362/*
363 * Map the region for device tree configuration with read and write permissions
364 */
365#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \
366 (ARM_FW_CONFIGS_LIMIT \
367 - ARM_BL_RAM_BASE), \
Zelalem Aweke65e92632021-07-12 22:33:55 -0500368 MT_MEMORY | MT_RW | EL3_PAS)
Zelalem Awekec43c5632021-07-12 23:41:05 -0500369/*
370 * Map L0_GPT with read and write permissions
371 */
372#if ENABLE_RME
373#define ARM_MAP_L0_GPT_REGION MAP_REGION_FLAT(ARM_L0_GPT_ADDR_BASE, \
374 ARM_L0_GPT_SIZE, \
375 MT_MEMORY | MT_RW | MT_ROOT)
376#endif
Antonio Nino Diaz48bfb542018-10-11 13:02:34 +0100377
378/*
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100379 * The max number of regions like RO(code), coherent and data required by
Dan Handley9df48042015-03-19 18:58:55 +0000380 * different BL stages which need to be mapped in the MMU.
381 */
Manish V Badarkhefc0b8532022-02-22 14:45:43 +0000382#define ARM_BL_REGIONS 7
Dan Handley9df48042015-03-19 18:58:55 +0000383
384#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
385 ARM_BL_REGIONS)
386
387/* Memory mapped Generic timer interfaces */
Gary Morrison3d7f6542021-01-27 13:08:47 -0600388#ifdef PLAT_ARM_SYS_CNTCTL_BASE
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600389#define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE
Gary Morrison3d7f6542021-01-27 13:08:47 -0600390#else
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100391#define ARM_SYS_CNTCTL_BASE UL(0x2a430000)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600392#endif
393
394#ifdef PLAT_ARM_SYS_CNTREAD_BASE
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600395#define ARM_SYS_CNTREAD_BASE PLAT_ARM_SYS_CNTREAD_BASE
Gary Morrison3d7f6542021-01-27 13:08:47 -0600396#else
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100397#define ARM_SYS_CNTREAD_BASE UL(0x2a800000)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600398#endif
399
400#ifdef PLAT_ARM_SYS_TIMCTL_BASE
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600401#define ARM_SYS_TIMCTL_BASE PLAT_ARM_SYS_TIMCTL_BASE
Gary Morrison3d7f6542021-01-27 13:08:47 -0600402#else
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100403#define ARM_SYS_TIMCTL_BASE UL(0x2a810000)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600404#endif
405
406#ifdef PLAT_ARM_SYS_CNT_BASE_S
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600407#define ARM_SYS_CNT_BASE_S PLAT_ARM_SYS_CNT_BASE_S
Gary Morrison3d7f6542021-01-27 13:08:47 -0600408#else
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100409#define ARM_SYS_CNT_BASE_S UL(0x2a820000)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600410#endif
411
412#ifdef PLAT_ARM_SYS_CNT_BASE_NS
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600413#define ARM_SYS_CNT_BASE_NS PLAT_ARM_SYS_CNT_BASE_NS
Gary Morrison3d7f6542021-01-27 13:08:47 -0600414#else
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100415#define ARM_SYS_CNT_BASE_NS UL(0x2a830000)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600416#endif
Dan Handley9df48042015-03-19 18:58:55 +0000417
418#define ARM_CONSOLE_BAUDRATE 115200
419
Juan Castillob6132f12015-10-06 14:01:35 +0100420/* Trusted Watchdog constants */
Gary Morrison3d7f6542021-01-27 13:08:47 -0600421#ifdef PLAT_ARM_SP805_TWDG_BASE
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600422#define ARM_SP805_TWDG_BASE PLAT_ARM_SP805_TWDG_BASE
Gary Morrison3d7f6542021-01-27 13:08:47 -0600423#else
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100424#define ARM_SP805_TWDG_BASE UL(0x2a490000)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600425#endif
Juan Castillob6132f12015-10-06 14:01:35 +0100426#define ARM_SP805_TWDG_CLK_HZ 32768
427/* The TBBR document specifies a watchdog timeout of 256 seconds. SP805
428 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */
429#define ARM_TWDG_TIMEOUT_SEC 128
430#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \
431 ARM_TWDG_TIMEOUT_SEC)
432
Dan Handley9df48042015-03-19 18:58:55 +0000433/******************************************************************************
434 * Required platform porting definitions common to all ARM standard platforms
435 *****************************************************************************/
436
Roberto Vargasf8fda102017-08-08 11:27:20 +0100437/*
Soby Mathewfec4eb72015-07-01 16:16:20 +0100438 * This macro defines the deepest retention state possible. A higher state
439 * id will represent an invalid or a power down state.
440 */
441#define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET
442
443/*
444 * This macro defines the deepest power down states possible. Any state ID
445 * higher than this is invalid.
446 */
447#define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF
448
Dan Handley9df48042015-03-19 18:58:55 +0000449/*
450 * Some data must be aligned on the biggest cache line size in the platform.
451 * This is known only to the platform as it might have a combination of
452 * integrated and external caches.
453 */
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100454#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT)
Dan Handley9df48042015-03-19 18:58:55 +0000455
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000456/*
Manish V Badarkhe1da211a2020-05-31 10:17:59 +0100457 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000458 * and limit. Leave enough space of BL2 meminfo.
459 */
Manish V Badarkhe1da211a2020-05-31 10:17:59 +0100460#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
Manish V Badarkhe0bafa822020-06-29 11:14:07 +0100461#define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \
462 + (PAGE_SIZE / 2U))
Sathees Balya90950092018-11-15 14:22:30 +0000463
464/*
465 * Boot parameters passed from BL2 to BL31/BL32 are stored here
466 */
Manish V Badarkhe0bafa822020-06-29 11:14:07 +0100467#define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT)
468#define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \
469 + (PAGE_SIZE / 2U))
Sathees Balya90950092018-11-15 14:22:30 +0000470
471/*
472 * Define limit of firmware configuration memory:
Manish V Badarkhe1da211a2020-05-31 10:17:59 +0100473 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory
Sathees Balya90950092018-11-15 14:22:30 +0000474 */
Manish V Badarkhefbf1fd22020-06-09 11:31:17 +0100475#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2))
Dan Handley9df48042015-03-19 18:58:55 +0000476
Zelalem Awekec43c5632021-07-12 23:41:05 -0500477#if ENABLE_RME
478/*
479 * Store the L0 GPT on Trusted SRAM next to firmware
480 * configuration memory, 4KB aligned.
481 */
482#define ARM_L0_GPT_SIZE (PAGE_SIZE)
483#define ARM_L0_GPT_ADDR_BASE (ARM_FW_CONFIGS_LIMIT)
484#define ARM_L0_GPT_LIMIT (ARM_L0_GPT_ADDR_BASE + ARM_L0_GPT_SIZE)
485#else
486#define ARM_L0_GPT_SIZE U(0)
487#endif
488
Dan Handley9df48042015-03-19 18:58:55 +0000489/*******************************************************************************
490 * BL1 specific defines.
491 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
492 * addresses.
493 ******************************************************************************/
494#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600495#ifdef PLAT_BL1_RO_LIMIT
496#define BL1_RO_LIMIT PLAT_BL1_RO_LIMIT
497#else
Dan Handley9df48042015-03-19 18:58:55 +0000498#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \
Roberto Vargase3adc372018-05-23 09:27:06 +0100499 + (PLAT_ARM_TRUSTED_ROM_SIZE - \
500 PLAT_ARM_MAX_ROMLIB_RO_SIZE))
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600501#endif
502
Dan Handley9df48042015-03-19 18:58:55 +0000503/*
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000504 * Put BL1 RW at the top of the Trusted SRAM.
Dan Handley9df48042015-03-19 18:58:55 +0000505 */
Dan Handley9df48042015-03-19 18:58:55 +0000506#define BL1_RW_BASE (ARM_BL_RAM_BASE + \
507 ARM_BL_RAM_SIZE - \
Roberto Vargase3adc372018-05-23 09:27:06 +0100508 (PLAT_ARM_MAX_BL1_RW_SIZE +\
509 PLAT_ARM_MAX_ROMLIB_RW_SIZE))
510#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \
511 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE))
512
513#define ROMLIB_RO_BASE BL1_RO_LIMIT
514#define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE)
515
516#define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE)
517#define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE)
Dan Handley9df48042015-03-19 18:58:55 +0000518
519/*******************************************************************************
520 * BL2 specific defines.
521 ******************************************************************************/
Soby Mathewaf14b462018-06-01 16:53:38 +0100522#if BL2_AT_EL3
Dimitris Papastamos25836492018-06-11 11:07:58 +0100523/* Put BL2 towards the middle of the Trusted SRAM */
Soby Mathewaf14b462018-06-01 16:53:38 +0100524#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \
Dimitris Papastamos25836492018-06-11 11:07:58 +0100525 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000)
Roberto Vargas52207802017-11-17 13:22:18 +0000526#define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
527
David Wang0ba499f2016-03-07 11:02:57 +0800528#else
Dan Handley9df48042015-03-19 18:58:55 +0000529/*
Soby Mathewaf14b462018-06-01 16:53:38 +0100530 * Put BL2 just below BL1.
Dan Handley9df48042015-03-19 18:58:55 +0000531 */
Soby Mathewaf14b462018-06-01 16:53:38 +0100532#define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
533#define BL2_LIMIT BL1_RW_BASE
David Wang0ba499f2016-03-07 11:02:57 +0800534#endif
Dan Handley9df48042015-03-19 18:58:55 +0000535
536/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000537 * BL31 specific defines.
Dan Handley9df48042015-03-19 18:58:55 +0000538 ******************************************************************************/
Madhukar Pappireddyd7419442020-01-27 15:38:26 -0600539#if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION
David Wang0ba499f2016-03-07 11:02:57 +0800540/*
541 * Put BL31 at the bottom of TZC secured DRAM
542 */
543#define BL31_BASE ARM_AP_TZC_DRAM1_BASE
544#define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
545 PLAT_ARM_MAX_BL31_SIZE)
Madhukar Pappireddyd7419442020-01-27 15:38:26 -0600546/*
547 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM.
548 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten.
549 */
550#if SEPARATE_NOBITS_REGION
551#define BL31_NOBITS_BASE BL2_BASE
552#define BL31_NOBITS_LIMIT BL2_LIMIT
553#endif /* SEPARATE_NOBITS_REGION */
Qixiang Xua5f72812017-08-31 11:45:32 +0800554#elif (RESET_TO_BL31)
Manish Pandey2207e932019-11-06 13:17:46 +0000555/* Ensure Position Independent support (PIE) is enabled for this config.*/
556# if !ENABLE_PIE
557# error "BL31 must be a PIE if RESET_TO_BL31=1."
558#endif
Qixiang Xua5f72812017-08-31 11:45:32 +0800559/*
Soby Mathew68e69282018-12-12 14:13:52 +0000560 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely
Soby Mathewc5e17452019-01-07 14:07:58 +0000561 * used for building BL31 and not used for loading BL31.
Qixiang Xua5f72812017-08-31 11:45:32 +0800562 */
Soby Mathewc5e17452019-01-07 14:07:58 +0000563# define BL31_BASE 0x0
564# define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE
David Wang0ba499f2016-03-07 11:02:57 +0800565#else
Soby Mathewaf14b462018-06-01 16:53:38 +0100566/* Put BL31 below BL2 in the Trusted SRAM.*/
567#define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
568 - PLAT_ARM_MAX_BL31_SIZE)
569#define BL31_PROGBITS_LIMIT BL2_BASE
Dimitris Papastamos25836492018-06-11 11:07:58 +0100570/*
571 * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. This is
572 * because in the BL2_AT_EL3 configuration, BL2 is always resident.
573 */
574#if BL2_AT_EL3
575#define BL31_LIMIT BL2_BASE
576#else
Dan Handley9df48042015-03-19 18:58:55 +0000577#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
David Wang0ba499f2016-03-07 11:02:57 +0800578#endif
Zelalem Awekec43c5632021-07-12 23:41:05 -0500579#endif
580
581/******************************************************************************
582 * RMM specific defines
583 *****************************************************************************/
584#if ENABLE_RME
585#define RMM_BASE (ARM_REALM_BASE)
586#define RMM_LIMIT (RMM_BASE + ARM_REALM_SIZE)
Dimitris Papastamos25836492018-06-11 11:07:58 +0100587#endif
Dan Handley9df48042015-03-19 18:58:55 +0000588
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700589#if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME
Dan Handley9df48042015-03-19 18:58:55 +0000590/*******************************************************************************
Soby Mathewbf169232017-11-14 14:10:10 +0000591 * BL32 specific defines for EL3 runtime in AArch32 mode
592 ******************************************************************************/
593# if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME
Manish Pandey928da862021-06-10 15:22:48 +0100594/* Ensure Position Independent support (PIE) is enabled for this config.*/
595# if !ENABLE_PIE
596# error "BL32 must be a PIE if RESET_TO_SP_MIN=1."
597#endif
Soby Mathewaf14b462018-06-01 16:53:38 +0100598/*
Manish Pandey928da862021-06-10 15:22:48 +0100599 * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely
600 * used for building BL32 and not used for loading BL32.
Soby Mathewaf14b462018-06-01 16:53:38 +0100601 */
Manish Pandey928da862021-06-10 15:22:48 +0100602# define BL32_BASE 0x0
603# define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE
Soby Mathewbf169232017-11-14 14:10:10 +0000604# else
Soby Mathewaf14b462018-06-01 16:53:38 +0100605/* Put BL32 below BL2 in the Trusted SRAM.*/
606# define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
607 - PLAT_ARM_MAX_BL32_SIZE)
608# define BL32_PROGBITS_LIMIT BL2_BASE
Soby Mathewbf169232017-11-14 14:10:10 +0000609# define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
610# endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */
611
612#else
613/*******************************************************************************
614 * BL32 specific defines for EL3 runtime in AArch64 mode
Dan Handley9df48042015-03-19 18:58:55 +0000615 ******************************************************************************/
616/*
617 * On ARM standard platforms, the TSP can execute from Trusted SRAM,
618 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone
619 * controller.
620 */
Marc Bonnicif5867002021-12-20 10:53:52 +0000621# if SPM_MM || SPMC_AT_EL3
Soby Mathewbf169232017-11-14 14:10:10 +0000622# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
623# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000))
624# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
625# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000626 ARM_AP_TZC_DRAM1_SIZE)
Achin Guptae97351d2019-10-11 15:15:19 +0100627# elif defined(SPD_spmd)
628# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
629# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000))
Arunachalam Ganapathy40618cf2020-07-27 13:51:30 +0100630# define BL32_BASE PLAT_ARM_SPMC_BASE
631# define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \
632 PLAT_ARM_SPMC_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000633# elif ARM_BL31_IN_DRAM
634# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \
David Wang0ba499f2016-03-07 11:02:57 +0800635 PLAT_ARM_MAX_BL31_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000636# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \
David Wang0ba499f2016-03-07 11:02:57 +0800637 PLAT_ARM_MAX_BL31_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000638# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \
David Wang0ba499f2016-03-07 11:02:57 +0800639 PLAT_ARM_MAX_BL31_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000640# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
David Wang0ba499f2016-03-07 11:02:57 +0800641 ARM_AP_TZC_DRAM1_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000642# elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID
643# define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE
644# define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE
Soby Mathewaf14b462018-06-01 16:53:38 +0100645# define TSP_PROGBITS_LIMIT BL31_BASE
Manish V Badarkhe1da211a2020-05-31 10:17:59 +0100646# define BL32_BASE ARM_FW_CONFIGS_LIMIT
Soby Mathewbf169232017-11-14 14:10:10 +0000647# define BL32_LIMIT BL31_BASE
648# elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID
649# define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE
650# define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE
651# define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE
652# define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +0000653 + (UL(1) << 21))
Soby Mathewbf169232017-11-14 14:10:10 +0000654# elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
655# define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE
656# define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE
657# define BL32_BASE ARM_AP_TZC_DRAM1_BASE
658# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
Dan Handley9df48042015-03-19 18:58:55 +0000659 ARM_AP_TZC_DRAM1_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000660# else
661# error "Unsupported ARM_TSP_RAM_LOCATION_ID value"
662# endif
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700663#endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */
Dan Handley9df48042015-03-19 18:58:55 +0000664
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000665/*
666 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no
Marc Bonnicif5867002021-12-20 10:53:52 +0000667 * SPD and no SPM-MM and no SPMC-AT-EL3, as they are the only ones that can be
668 * used as BL32.
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000669 */
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700670#if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME
Marc Bonnicif5867002021-12-20 10:53:52 +0000671# if defined(SPD_none) && !SPM_MM && !SPMC_AT_EL3
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000672# undef BL32_BASE
Marc Bonnicif5867002021-12-20 10:53:52 +0000673# endif /* defined(SPD_none) && !SPM_MM || !SPMC_AT_EL3 */
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700674#endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100675
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100676/*******************************************************************************
677 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines.
678 ******************************************************************************/
679#define BL2U_BASE BL2_BASE
Soby Mathewbf169232017-11-14 14:10:10 +0000680#define BL2U_LIMIT BL2_LIMIT
681
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100682#define NS_BL2U_BASE ARM_NS_DRAM1_BASE
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +0000683#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000))
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100684
Dan Handley9df48042015-03-19 18:58:55 +0000685/*
686 * ID of the secure physical generic timer interrupt used by the TSP.
687 */
688#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
689
690
Vikram Kanigirid79214c2015-09-09 10:52:13 +0100691/*
692 * One cache line needed for bakery locks on ARM platforms
693 */
694#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
695
Jeenu Viswambharanb1837452017-10-24 11:47:13 +0100696/* Priority levels for ARM platforms */
Jeenu Viswambharana5b5b8d2018-02-06 12:21:39 +0000697#define PLAT_RAS_PRI 0x10
Jeenu Viswambharanb1837452017-10-24 11:47:13 +0100698#define PLAT_SDEI_CRITICAL_PRI 0x60
699#define PLAT_SDEI_NORMAL_PRI 0x70
700
701/* ARM platforms use 3 upper bits of secure interrupt priority */
Sandeep Tripathy1c478392020-08-12 18:42:13 +0530702#define PLAT_PRI_BITS 3
Vikram Kanigirid79214c2015-09-09 10:52:13 +0100703
Jeenu Viswambharana5acc0a2017-09-22 08:32:10 +0100704/* SGI used for SDEI signalling */
705#define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0
706
Balint Dobszayd0dbd5e2019-12-18 15:28:00 +0100707#if SDEI_IN_FCONF
708/* ARM SDEI dynamic private event max count */
709#define ARM_SDEI_DP_EVENT_MAX_CNT 3
710
711/* ARM SDEI dynamic shared event max count */
712#define ARM_SDEI_DS_EVENT_MAX_CNT 3
713#else
Jeenu Viswambharana5acc0a2017-09-22 08:32:10 +0100714/* ARM SDEI dynamic private event numbers */
715#define ARM_SDEI_DP_EVENT_0 1000
716#define ARM_SDEI_DP_EVENT_1 1001
717#define ARM_SDEI_DP_EVENT_2 1002
718
719/* ARM SDEI dynamic shared event numbers */
720#define ARM_SDEI_DS_EVENT_0 2000
721#define ARM_SDEI_DS_EVENT_1 2001
722#define ARM_SDEI_DS_EVENT_2 2002
723
Jeenu Viswambharan6e284462017-12-08 10:38:24 +0000724#define ARM_SDEI_PRIVATE_EVENTS \
725 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \
726 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
727 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
728 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
729
730#define ARM_SDEI_SHARED_EVENTS \
731 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
732 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
733 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
Balint Dobszayd0dbd5e2019-12-18 15:28:00 +0100734#endif /* SDEI_IN_FCONF */
Jeenu Viswambharan6e284462017-12-08 10:38:24 +0000735
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100736#endif /* ARM_DEF_H */