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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Sami Mujawara43ae7c2019-05-09 13:35:02 +01002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01006#ifndef ARM_DEF_H
7#define ARM_DEF_H
Dan Handley9df48042015-03-19 18:58:55 +00008
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009#include <arch.h>
10#include <common/interrupt_props.h>
11#include <common/tbbr/tbbr_img_def.h>
12#include <drivers/arm/gic_common.h>
13#include <lib/utils_def.h>
14#include <lib/xlat_tables/xlat_tables_defs.h>
15#include <plat/common/common_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000016
17/******************************************************************************
18 * Definitions common to all ARM standard platforms
19 *****************************************************************************/
20
Juan Castillo7d199412015-12-14 09:35:25 +000021/* Special value used to verify platform parameters from BL2 to BL31 */
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +000022#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978)
Dan Handley9df48042015-03-19 18:58:55 +000023
Soby Mathewa869de12015-05-08 10:18:59 +010024#define ARM_SYSTEM_COUNT 1
Dan Handley9df48042015-03-19 18:58:55 +000025
26#define ARM_CACHE_WRITEBACK_SHIFT 6
27
Soby Mathewfec4eb72015-07-01 16:16:20 +010028/*
29 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
30 * power levels have a 1:1 mapping with the MPIDR affinity levels.
31 */
32#define ARM_PWR_LVL0 MPIDR_AFFLVL0
33#define ARM_PWR_LVL1 MPIDR_AFFLVL1
Soby Mathewa869de12015-05-08 10:18:59 +010034#define ARM_PWR_LVL2 MPIDR_AFFLVL2
Chandni Cherukuri9ec4a112018-10-16 14:42:19 +053035#define ARM_PWR_LVL3 MPIDR_AFFLVL3
Soby Mathewfec4eb72015-07-01 16:16:20 +010036
37/*
38 * Macros for local power states in ARM platforms encoded by State-ID field
39 * within the power-state parameter.
40 */
41/* Local power state for power domains in Run state. */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010042#define ARM_LOCAL_STATE_RUN U(0)
Soby Mathewfec4eb72015-07-01 16:16:20 +010043/* Local power state for retention. Valid only for CPU power domains */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010044#define ARM_LOCAL_STATE_RET U(1)
Soby Mathewfec4eb72015-07-01 16:16:20 +010045/* Local power state for OFF/power-down. Valid for CPU and cluster power
46 domains */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010047#define ARM_LOCAL_STATE_OFF U(2)
Soby Mathewfec4eb72015-07-01 16:16:20 +010048
Dan Handley9df48042015-03-19 18:58:55 +000049/* Memory location options for TSP */
50#define ARM_TRUSTED_SRAM_ID 0
51#define ARM_TRUSTED_DRAM_ID 1
52#define ARM_DRAM_ID 2
53
54/* The first 4KB of Trusted SRAM are used as shared memory */
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010055#define ARM_TRUSTED_SRAM_BASE UL(0x04000000)
Dan Handley9df48042015-03-19 18:58:55 +000056#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010057#define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */
Dan Handley9df48042015-03-19 18:58:55 +000058
59/* The remaining Trusted SRAM is used to load the BL images */
60#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \
61 ARM_SHARED_RAM_SIZE)
62#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
63 ARM_SHARED_RAM_SIZE)
64
65/*
66 * The top 16MB of DRAM1 is configured as secure access only using the TZC
67 * - SCP TZC DRAM: If present, DRAM reserved for SCP use
68 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use
69 */
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010070#define ARM_TZC_DRAM1_SIZE UL(0x01000000)
Dan Handley9df48042015-03-19 18:58:55 +000071
72#define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
73 ARM_DRAM1_SIZE - \
74 ARM_SCP_TZC_DRAM1_SIZE)
75#define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE
76#define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \
77 ARM_SCP_TZC_DRAM1_SIZE - 1)
78
Soby Mathew3b5156e2017-10-05 12:27:33 +010079/*
80 * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime
81 * firmware. This region is meant to be NOLOAD and will not be zero
82 * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be
83 * placed here.
84 */
85#define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - ARM_EL3_TZC_DRAM1_SIZE)
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010086#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2 MB */
Soby Mathew3b5156e2017-10-05 12:27:33 +010087#define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \
88 ARM_EL3_TZC_DRAM1_SIZE - 1)
89
Dan Handley9df48042015-03-19 18:58:55 +000090#define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
91 ARM_DRAM1_SIZE - \
92 ARM_TZC_DRAM1_SIZE)
93#define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \
Soby Mathew3b5156e2017-10-05 12:27:33 +010094 (ARM_SCP_TZC_DRAM1_SIZE + \
95 ARM_EL3_TZC_DRAM1_SIZE))
Dan Handley9df48042015-03-19 18:58:55 +000096#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \
97 ARM_AP_TZC_DRAM1_SIZE - 1)
98
Soby Mathew7e4d6652017-05-10 11:50:30 +010099/* Define the Access permissions for Secure peripherals to NS_DRAM */
100#if ARM_CRYPTOCELL_INTEG
101/*
102 * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell.
103 * This is required by CryptoCell to authenticate BL33 which is loaded
104 * into the Non Secure DDR.
105 */
106#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD
107#else
108#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE
109#endif
110
Summer Qin9db8f2e2017-04-24 16:49:28 +0100111#ifdef SPD_opteed
112/*
Jens Wiklanderae73b162017-08-24 15:39:09 +0200113 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to
114 * load/authenticate the trusted os extra image. The first 512KB of
115 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading
116 * for OPTEE is paged image which only include the paging part using
117 * virtual memory but without "init" data. OPTEE will copy the "init" data
118 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the
119 * extra image behind the "init" data.
Summer Qin9db8f2e2017-04-24 16:49:28 +0100120 */
Jens Wiklanderae73b162017-08-24 15:39:09 +0200121#define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \
122 ARM_AP_TZC_DRAM1_SIZE - \
123 ARM_OPTEE_PAGEABLE_LOAD_SIZE)
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100124#define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000)
Summer Qin9db8f2e2017-04-24 16:49:28 +0100125#define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \
126 ARM_OPTEE_PAGEABLE_LOAD_BASE, \
127 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \
128 MT_MEMORY | MT_RW | MT_SECURE)
Soby Mathew874fc9e2017-09-01 13:43:50 +0100129
130/*
131 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging
132 * support is enabled).
133 */
134#define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \
135 BL32_BASE, \
136 BL32_LIMIT - BL32_BASE, \
137 MT_MEMORY | MT_RW | MT_SECURE)
Summer Qin9db8f2e2017-04-24 16:49:28 +0100138#endif /* SPD_opteed */
Dan Handley9df48042015-03-19 18:58:55 +0000139
140#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
141#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
142 ARM_TZC_DRAM1_SIZE)
143#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
144 ARM_NS_DRAM1_SIZE - 1)
145
Sandrine Bailleux6c32fc72018-10-31 14:28:17 +0100146#define ARM_DRAM1_BASE ULL(0x80000000)
147#define ARM_DRAM1_SIZE ULL(0x80000000)
Dan Handley9df48042015-03-19 18:58:55 +0000148#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
149 ARM_DRAM1_SIZE - 1)
150
Sami Mujawara43ae7c2019-05-09 13:35:02 +0100151#define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE
Dan Handley9df48042015-03-19 18:58:55 +0000152#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE
153#define ARM_DRAM2_END (ARM_DRAM2_BASE + \
154 ARM_DRAM2_SIZE - 1)
155
156#define ARM_IRQ_SEC_PHY_TIMER 29
157
158#define ARM_IRQ_SEC_SGI_0 8
159#define ARM_IRQ_SEC_SGI_1 9
160#define ARM_IRQ_SEC_SGI_2 10
161#define ARM_IRQ_SEC_SGI_3 11
162#define ARM_IRQ_SEC_SGI_4 12
163#define ARM_IRQ_SEC_SGI_5 13
164#define ARM_IRQ_SEC_SGI_6 14
165#define ARM_IRQ_SEC_SGI_7 15
166
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000167/*
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100168 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
169 * terminology. On a GICv2 system or mode, the lists will be merged and treated
170 * as Group 0 interrupts.
171 */
172#define ARM_G1S_IRQ_PROPS(grp) \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100173 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100174 GIC_INTR_CFG_LEVEL), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100175 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100176 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100177 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100178 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100179 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100180 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100181 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100182 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100183 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100184 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100185 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100186 GIC_INTR_CFG_EDGE)
187
188#define ARM_G0_IRQ_PROPS(grp) \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100189 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100190 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100191 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100192 GIC_INTR_CFG_EDGE)
193
Dan Handley9df48042015-03-19 18:58:55 +0000194#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
195 ARM_SHARED_RAM_BASE, \
196 ARM_SHARED_RAM_SIZE, \
Juan Castillo2e86cb12016-01-13 15:01:09 +0000197 MT_DEVICE | MT_RW | MT_SECURE)
Dan Handley9df48042015-03-19 18:58:55 +0000198
199#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
200 ARM_NS_DRAM1_BASE, \
201 ARM_NS_DRAM1_SIZE, \
202 MT_MEMORY | MT_RW | MT_NS)
203
Roberto Vargasf8fda102017-08-08 11:27:20 +0100204#define ARM_MAP_DRAM2 MAP_REGION_FLAT( \
205 ARM_DRAM2_BASE, \
206 ARM_DRAM2_SIZE, \
207 MT_MEMORY | MT_RW | MT_NS)
Roberto Vargasf8fda102017-08-08 11:27:20 +0100208
Dan Handley9df48042015-03-19 18:58:55 +0000209#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \
210 TSP_SEC_MEM_BASE, \
211 TSP_SEC_MEM_SIZE, \
212 MT_MEMORY | MT_RW | MT_SECURE)
213
David Wang0ba499f2016-03-07 11:02:57 +0800214#if ARM_BL31_IN_DRAM
215#define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \
216 BL31_BASE, \
217 PLAT_ARM_MAX_BL31_SIZE, \
218 MT_MEMORY | MT_RW | MT_SECURE)
219#endif
Dan Handley9df48042015-03-19 18:58:55 +0000220
Soby Mathew3b5156e2017-10-05 12:27:33 +0100221#define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \
222 ARM_EL3_TZC_DRAM1_BASE, \
223 ARM_EL3_TZC_DRAM1_SIZE, \
224 MT_MEMORY | MT_RW | MT_SECURE)
225
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100226/*
John Tsichritzisc34341a2018-07-30 13:41:52 +0100227 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to
228 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides
229 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order
230 * to be able to access the heap.
231 */
232#define ARM_MAP_BL1_RW MAP_REGION_FLAT( \
233 BL1_RW_BASE, \
234 BL1_RW_LIMIT - BL1_RW_BASE, \
235 MT_MEMORY | MT_RW | MT_SECURE)
236
237/*
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100238 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
239 * otherwise one region is defined containing both.
240 */
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100241#if SEPARATE_CODE_AND_RODATA
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100242#define ARM_MAP_BL_RO MAP_REGION_FLAT( \
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100243 BL_CODE_BASE, \
244 BL_CODE_END - BL_CODE_BASE, \
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100245 MT_CODE | MT_SECURE), \
246 MAP_REGION_FLAT( \
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100247 BL_RO_DATA_BASE, \
248 BL_RO_DATA_END \
249 - BL_RO_DATA_BASE, \
250 MT_RO_DATA | MT_SECURE)
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100251#else
252#define ARM_MAP_BL_RO MAP_REGION_FLAT( \
253 BL_CODE_BASE, \
254 BL_CODE_END - BL_CODE_BASE, \
255 MT_CODE | MT_SECURE)
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100256#endif
257#if USE_COHERENT_MEM
258#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
259 BL_COHERENT_RAM_BASE, \
260 BL_COHERENT_RAM_END \
261 - BL_COHERENT_RAM_BASE, \
262 MT_DEVICE | MT_RW | MT_SECURE)
263#endif
Roberto Vargase3adc372018-05-23 09:27:06 +0100264#if USE_ROMLIB
265#define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \
266 ROMLIB_RO_BASE, \
267 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\
268 MT_CODE | MT_SECURE)
269
270#define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \
271 ROMLIB_RW_BASE, \
272 ROMLIB_RW_END - ROMLIB_RW_BASE,\
273 MT_MEMORY | MT_RW | MT_SECURE)
274#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100275
Dan Handley9df48042015-03-19 18:58:55 +0000276/*
Antonio Nino Diaz48bfb542018-10-11 13:02:34 +0100277 * Map mem_protect flash region with read and write permissions
278 */
279#define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \
280 V2M_FLASH_BLOCK_SIZE, \
281 MT_DEVICE | MT_RW | MT_SECURE)
282
283/*
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100284 * The max number of regions like RO(code), coherent and data required by
Dan Handley9df48042015-03-19 18:58:55 +0000285 * different BL stages which need to be mapped in the MMU.
286 */
Daniel Boulbyb1b058d2018-09-18 11:52:49 +0100287#define ARM_BL_REGIONS 5
Dan Handley9df48042015-03-19 18:58:55 +0000288
289#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
290 ARM_BL_REGIONS)
291
292/* Memory mapped Generic timer interfaces */
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100293#define ARM_SYS_CNTCTL_BASE UL(0x2a430000)
294#define ARM_SYS_CNTREAD_BASE UL(0x2a800000)
295#define ARM_SYS_TIMCTL_BASE UL(0x2a810000)
296#define ARM_SYS_CNT_BASE_S UL(0x2a820000)
297#define ARM_SYS_CNT_BASE_NS UL(0x2a830000)
Dan Handley9df48042015-03-19 18:58:55 +0000298
299#define ARM_CONSOLE_BAUDRATE 115200
300
Juan Castillob6132f12015-10-06 14:01:35 +0100301/* Trusted Watchdog constants */
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100302#define ARM_SP805_TWDG_BASE UL(0x2a490000)
Juan Castillob6132f12015-10-06 14:01:35 +0100303#define ARM_SP805_TWDG_CLK_HZ 32768
304/* The TBBR document specifies a watchdog timeout of 256 seconds. SP805
305 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */
306#define ARM_TWDG_TIMEOUT_SEC 128
307#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \
308 ARM_TWDG_TIMEOUT_SEC)
309
Dan Handley9df48042015-03-19 18:58:55 +0000310/******************************************************************************
311 * Required platform porting definitions common to all ARM standard platforms
312 *****************************************************************************/
313
Roberto Vargasf8fda102017-08-08 11:27:20 +0100314/*
Soby Mathewfec4eb72015-07-01 16:16:20 +0100315 * This macro defines the deepest retention state possible. A higher state
316 * id will represent an invalid or a power down state.
317 */
318#define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET
319
320/*
321 * This macro defines the deepest power down states possible. Any state ID
322 * higher than this is invalid.
323 */
324#define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF
325
Dan Handley9df48042015-03-19 18:58:55 +0000326/*
327 * Some data must be aligned on the biggest cache line size in the platform.
328 * This is known only to the platform as it might have a combination of
329 * integrated and external caches.
330 */
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100331#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT)
Dan Handley9df48042015-03-19 18:58:55 +0000332
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000333/*
334 * To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base
335 * and limit. Leave enough space of BL2 meminfo.
336 */
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +0000337#define ARM_TB_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
Sathees Balya90950092018-11-15 14:22:30 +0000338#define ARM_TB_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE / 2U))
339
340/*
341 * Boot parameters passed from BL2 to BL31/BL32 are stored here
342 */
343#define ARM_BL2_MEM_DESC_BASE ARM_TB_FW_CONFIG_LIMIT
344#define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE + \
345 (PAGE_SIZE / 2U))
346
347/*
348 * Define limit of firmware configuration memory:
349 * ARM_TB_FW_CONFIG + ARM_BL2_MEM_DESC memory
350 */
351#define ARM_FW_CONFIG_LIMIT (ARM_BL_RAM_BASE + PAGE_SIZE)
Dan Handley9df48042015-03-19 18:58:55 +0000352
353/*******************************************************************************
354 * BL1 specific defines.
355 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
356 * addresses.
357 ******************************************************************************/
358#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE
359#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \
Roberto Vargase3adc372018-05-23 09:27:06 +0100360 + (PLAT_ARM_TRUSTED_ROM_SIZE - \
361 PLAT_ARM_MAX_ROMLIB_RO_SIZE))
Dan Handley9df48042015-03-19 18:58:55 +0000362/*
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000363 * Put BL1 RW at the top of the Trusted SRAM.
Dan Handley9df48042015-03-19 18:58:55 +0000364 */
Dan Handley9df48042015-03-19 18:58:55 +0000365#define BL1_RW_BASE (ARM_BL_RAM_BASE + \
366 ARM_BL_RAM_SIZE - \
Roberto Vargase3adc372018-05-23 09:27:06 +0100367 (PLAT_ARM_MAX_BL1_RW_SIZE +\
368 PLAT_ARM_MAX_ROMLIB_RW_SIZE))
369#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \
370 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE))
371
372#define ROMLIB_RO_BASE BL1_RO_LIMIT
373#define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE)
374
375#define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE)
376#define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE)
Dan Handley9df48042015-03-19 18:58:55 +0000377
378/*******************************************************************************
379 * BL2 specific defines.
380 ******************************************************************************/
Soby Mathewaf14b462018-06-01 16:53:38 +0100381#if BL2_AT_EL3
Dimitris Papastamos25836492018-06-11 11:07:58 +0100382/* Put BL2 towards the middle of the Trusted SRAM */
Soby Mathewaf14b462018-06-01 16:53:38 +0100383#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \
Dimitris Papastamos25836492018-06-11 11:07:58 +0100384 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000)
Roberto Vargas52207802017-11-17 13:22:18 +0000385#define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
386
David Wang0ba499f2016-03-07 11:02:57 +0800387#else
Dan Handley9df48042015-03-19 18:58:55 +0000388/*
Soby Mathewaf14b462018-06-01 16:53:38 +0100389 * Put BL2 just below BL1.
Dan Handley9df48042015-03-19 18:58:55 +0000390 */
Soby Mathewaf14b462018-06-01 16:53:38 +0100391#define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
392#define BL2_LIMIT BL1_RW_BASE
David Wang0ba499f2016-03-07 11:02:57 +0800393#endif
Dan Handley9df48042015-03-19 18:58:55 +0000394
395/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000396 * BL31 specific defines.
Dan Handley9df48042015-03-19 18:58:55 +0000397 ******************************************************************************/
David Wang0ba499f2016-03-07 11:02:57 +0800398#if ARM_BL31_IN_DRAM
399/*
400 * Put BL31 at the bottom of TZC secured DRAM
401 */
402#define BL31_BASE ARM_AP_TZC_DRAM1_BASE
403#define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
404 PLAT_ARM_MAX_BL31_SIZE)
Qixiang Xua5f72812017-08-31 11:45:32 +0800405#elif (RESET_TO_BL31)
Manish Pandey2207e932019-11-06 13:17:46 +0000406/* Ensure Position Independent support (PIE) is enabled for this config.*/
407# if !ENABLE_PIE
408# error "BL31 must be a PIE if RESET_TO_BL31=1."
409#endif
Qixiang Xua5f72812017-08-31 11:45:32 +0800410/*
Soby Mathew68e69282018-12-12 14:13:52 +0000411 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely
Soby Mathewc5e17452019-01-07 14:07:58 +0000412 * used for building BL31 and not used for loading BL31.
Qixiang Xua5f72812017-08-31 11:45:32 +0800413 */
Soby Mathewc5e17452019-01-07 14:07:58 +0000414# define BL31_BASE 0x0
415# define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE
David Wang0ba499f2016-03-07 11:02:57 +0800416#else
Soby Mathewaf14b462018-06-01 16:53:38 +0100417/* Put BL31 below BL2 in the Trusted SRAM.*/
418#define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
419 - PLAT_ARM_MAX_BL31_SIZE)
420#define BL31_PROGBITS_LIMIT BL2_BASE
Dimitris Papastamos25836492018-06-11 11:07:58 +0100421/*
422 * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. This is
423 * because in the BL2_AT_EL3 configuration, BL2 is always resident.
424 */
425#if BL2_AT_EL3
426#define BL31_LIMIT BL2_BASE
427#else
Dan Handley9df48042015-03-19 18:58:55 +0000428#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
David Wang0ba499f2016-03-07 11:02:57 +0800429#endif
Dimitris Papastamos25836492018-06-11 11:07:58 +0100430#endif
Dan Handley9df48042015-03-19 18:58:55 +0000431
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700432#if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME
Dan Handley9df48042015-03-19 18:58:55 +0000433/*******************************************************************************
Soby Mathewbf169232017-11-14 14:10:10 +0000434 * BL32 specific defines for EL3 runtime in AArch32 mode
435 ******************************************************************************/
436# if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME
Soby Mathewaf14b462018-06-01 16:53:38 +0100437/*
438 * SP_MIN is the only BL image in SRAM. Allocate the whole of SRAM (excluding
439 * the page reserved for fw_configs) to BL32
440 */
Sathees Balya90950092018-11-15 14:22:30 +0000441# define BL32_BASE ARM_FW_CONFIG_LIMIT
Soby Mathewbf169232017-11-14 14:10:10 +0000442# define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
443# else
Soby Mathewaf14b462018-06-01 16:53:38 +0100444/* Put BL32 below BL2 in the Trusted SRAM.*/
445# define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
446 - PLAT_ARM_MAX_BL32_SIZE)
447# define BL32_PROGBITS_LIMIT BL2_BASE
Soby Mathewbf169232017-11-14 14:10:10 +0000448# define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
449# endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */
450
451#else
452/*******************************************************************************
453 * BL32 specific defines for EL3 runtime in AArch64 mode
Dan Handley9df48042015-03-19 18:58:55 +0000454 ******************************************************************************/
455/*
456 * On ARM standard platforms, the TSP can execute from Trusted SRAM,
457 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone
458 * controller.
459 */
Soby Mathewbf169232017-11-14 14:10:10 +0000460# if ENABLE_SPM
461# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
462# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000))
463# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
464# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000465 ARM_AP_TZC_DRAM1_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000466# elif ARM_BL31_IN_DRAM
467# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \
David Wang0ba499f2016-03-07 11:02:57 +0800468 PLAT_ARM_MAX_BL31_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000469# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \
David Wang0ba499f2016-03-07 11:02:57 +0800470 PLAT_ARM_MAX_BL31_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000471# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \
David Wang0ba499f2016-03-07 11:02:57 +0800472 PLAT_ARM_MAX_BL31_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000473# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
David Wang0ba499f2016-03-07 11:02:57 +0800474 ARM_AP_TZC_DRAM1_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000475# elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID
476# define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE
477# define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE
Soby Mathewaf14b462018-06-01 16:53:38 +0100478# define TSP_PROGBITS_LIMIT BL31_BASE
Sathees Balya90950092018-11-15 14:22:30 +0000479# define BL32_BASE ARM_FW_CONFIG_LIMIT
Soby Mathewbf169232017-11-14 14:10:10 +0000480# define BL32_LIMIT BL31_BASE
481# elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID
482# define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE
483# define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE
484# define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE
485# define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +0000486 + (UL(1) << 21))
Soby Mathewbf169232017-11-14 14:10:10 +0000487# elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
488# define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE
489# define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE
490# define BL32_BASE ARM_AP_TZC_DRAM1_BASE
491# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
Dan Handley9df48042015-03-19 18:58:55 +0000492 ARM_AP_TZC_DRAM1_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000493# else
494# error "Unsupported ARM_TSP_RAM_LOCATION_ID value"
495# endif
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700496#endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */
Dan Handley9df48042015-03-19 18:58:55 +0000497
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000498/*
499 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no
500 * SPD and no SPM, as they are the only ones that can be used as BL32.
501 */
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700502#if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000503# if defined(SPD_none) && !ENABLE_SPM
504# undef BL32_BASE
Soby Mathewbf169232017-11-14 14:10:10 +0000505# endif /* defined(SPD_none) && !ENABLE_SPM */
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700506#endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100507
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100508/*******************************************************************************
509 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines.
510 ******************************************************************************/
511#define BL2U_BASE BL2_BASE
Soby Mathewbf169232017-11-14 14:10:10 +0000512#define BL2U_LIMIT BL2_LIMIT
513
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100514#define NS_BL2U_BASE ARM_NS_DRAM1_BASE
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +0000515#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000))
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100516
Dan Handley9df48042015-03-19 18:58:55 +0000517/*
518 * ID of the secure physical generic timer interrupt used by the TSP.
519 */
520#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
521
522
Vikram Kanigirid79214c2015-09-09 10:52:13 +0100523/*
524 * One cache line needed for bakery locks on ARM platforms
525 */
526#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
527
Jeenu Viswambharanb1837452017-10-24 11:47:13 +0100528/* Priority levels for ARM platforms */
Jeenu Viswambharana5b5b8d2018-02-06 12:21:39 +0000529#define PLAT_RAS_PRI 0x10
Jeenu Viswambharanb1837452017-10-24 11:47:13 +0100530#define PLAT_SDEI_CRITICAL_PRI 0x60
531#define PLAT_SDEI_NORMAL_PRI 0x70
532
533/* ARM platforms use 3 upper bits of secure interrupt priority */
534#define ARM_PRI_BITS 3
Vikram Kanigirid79214c2015-09-09 10:52:13 +0100535
Jeenu Viswambharana5acc0a2017-09-22 08:32:10 +0100536/* SGI used for SDEI signalling */
537#define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0
538
539/* ARM SDEI dynamic private event numbers */
540#define ARM_SDEI_DP_EVENT_0 1000
541#define ARM_SDEI_DP_EVENT_1 1001
542#define ARM_SDEI_DP_EVENT_2 1002
543
544/* ARM SDEI dynamic shared event numbers */
545#define ARM_SDEI_DS_EVENT_0 2000
546#define ARM_SDEI_DS_EVENT_1 2001
547#define ARM_SDEI_DS_EVENT_2 2002
548
Jeenu Viswambharan6e284462017-12-08 10:38:24 +0000549#define ARM_SDEI_PRIVATE_EVENTS \
550 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \
551 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
552 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
553 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
554
555#define ARM_SDEI_SHARED_EVENTS \
556 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
557 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
558 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
559
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100560#endif /* ARM_DEF_H */