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Ian Spray84687392014-01-02 16:57:12 +00001/*
Dan Handleyfb42b122014-06-20 09:43:15 +01002 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
Ian Spray84687392014-01-02 16:57:12 +00003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handleyfb42b122014-06-20 09:43:15 +010031#include <arch.h>
Ian Spray84687392014-01-02 16:57:12 +000032#include <arch_helpers.h>
Dan Handleyfb42b122014-06-20 09:43:15 +010033#include <arm_gic.h>
Achin Gupta191e86e2014-05-09 10:03:15 +010034#include <assert.h>
35#include <bl_common.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010036#include <debug.h>
Dan Handley930ee2e2014-04-17 17:48:52 +010037#include <gic_v2.h>
38#include <gic_v3.h>
Achin Gupta191e86e2014-05-09 10:03:15 +010039#include <interrupt_mgmt.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010040#include <platform.h>
41#include <stdint.h>
Dan Handleyfb42b122014-06-20 09:43:15 +010042
Juan Castillo82312952014-10-20 12:27:28 +010043/* Value used to initialize Non-Secure IRQ priorities four at a time */
44#define GICD_IPRIORITYR_DEF_VAL \
45 (GIC_HIGHEST_NS_PRIORITY | \
46 (GIC_HIGHEST_NS_PRIORITY << 8) | \
47 (GIC_HIGHEST_NS_PRIORITY << 16) | \
48 (GIC_HIGHEST_NS_PRIORITY << 24))
Dan Handleyfb42b122014-06-20 09:43:15 +010049
Juan Castillo7f1f0622014-09-09 09:49:23 +010050static uintptr_t g_gicc_base;
51static uintptr_t g_gicd_base;
52static uintptr_t g_gicr_base;
Dan Handleyfb42b122014-06-20 09:43:15 +010053static const unsigned int *g_irq_sec_ptr;
54static unsigned int g_num_irqs;
55
Ian Spray84687392014-01-02 16:57:12 +000056
Ian Spray84687392014-01-02 16:57:12 +000057/*******************************************************************************
58 * This function does some minimal GICv3 configuration. The Firmware itself does
59 * not fully support GICv3 at this time and relies on GICv2 emulation as
60 * provided by GICv3. This function allows software (like Linux) in later stages
61 * to use full GICv3 features.
62 ******************************************************************************/
Dan Handleyfb42b122014-06-20 09:43:15 +010063static void gicv3_cpuif_setup(void)
Ian Spray84687392014-01-02 16:57:12 +000064{
Vikram Kanigiri29f7cbc2015-06-26 10:13:22 +010065 unsigned int val;
Harry Liebeleaec5902013-12-12 13:00:29 +000066 uintptr_t base;
Ian Spray84687392014-01-02 16:57:12 +000067
68 /*
69 * When CPUs come out of reset they have their GICR_WAKER.ProcessorSleep
70 * bit set. In order to allow interrupts to get routed to the CPU we
71 * need to clear this bit if set and wait for GICR_WAKER.ChildrenAsleep
72 * to clear (GICv3 Architecture specification 5.4.23).
73 * GICR_WAKER is NOT banked per CPU, compute the correct base address
74 * per CPU.
Ian Spray84687392014-01-02 16:57:12 +000075 */
Dan Handleyfb42b122014-06-20 09:43:15 +010076 assert(g_gicr_base);
77 base = gicv3_get_rdist(g_gicr_base, read_mpidr());
Harry Liebeleaec5902013-12-12 13:00:29 +000078 if (base == (uintptr_t)NULL) {
79 /* No re-distributor base address. This interface cannot be
80 * configured.
81 */
82 panic();
83 }
84
Ian Spray84687392014-01-02 16:57:12 +000085 val = gicr_read_waker(base);
86
87 val &= ~WAKER_PS;
88 gicr_write_waker(base, val);
89 dsb();
90
91 /* We need to wait for ChildrenAsleep to clear. */
92 val = gicr_read_waker(base);
Dan Handleyfb42b122014-06-20 09:43:15 +010093 while (val & WAKER_CA)
Ian Spray84687392014-01-02 16:57:12 +000094 val = gicr_read_waker(base);
Ian Spray84687392014-01-02 16:57:12 +000095
Ian Spray84687392014-01-02 16:57:12 +000096 val = read_icc_sre_el3();
97 write_icc_sre_el3(val | ICC_SRE_EN | ICC_SRE_SRE);
Vikram Kanigiri29f7cbc2015-06-26 10:13:22 +010098 isb();
Ian Spray84687392014-01-02 16:57:12 +000099}
100
101/*******************************************************************************
102 * This function does some minimal GICv3 configuration when cores go
103 * down.
104 ******************************************************************************/
Dan Handleyfb42b122014-06-20 09:43:15 +0100105static void gicv3_cpuif_deactivate(void)
Ian Spray84687392014-01-02 16:57:12 +0000106{
Harry Liebeleaec5902013-12-12 13:00:29 +0000107 unsigned int val;
108 uintptr_t base;
Ian Spray84687392014-01-02 16:57:12 +0000109
110 /*
111 * When taking CPUs down we need to set GICR_WAKER.ProcessorSleep and
112 * wait for GICR_WAKER.ChildrenAsleep to get set.
113 * (GICv3 Architecture specification 5.4.23).
114 * GICR_WAKER is NOT banked per CPU, compute the correct base address
115 * per CPU.
Ian Spray84687392014-01-02 16:57:12 +0000116 */
Dan Handleyfb42b122014-06-20 09:43:15 +0100117 assert(g_gicr_base);
118 base = gicv3_get_rdist(g_gicr_base, read_mpidr());
Harry Liebeleaec5902013-12-12 13:00:29 +0000119 if (base == (uintptr_t)NULL) {
120 /* No re-distributor base address. This interface cannot be
121 * configured.
122 */
123 panic();
124 }
125
Ian Spray84687392014-01-02 16:57:12 +0000126 val = gicr_read_waker(base);
127 val |= WAKER_PS;
128 gicr_write_waker(base, val);
129 dsb();
130
131 /* We need to wait for ChildrenAsleep to set. */
132 val = gicr_read_waker(base);
Dan Handleyfb42b122014-06-20 09:43:15 +0100133 while ((val & WAKER_CA) == 0)
Ian Spray84687392014-01-02 16:57:12 +0000134 val = gicr_read_waker(base);
Ian Spray84687392014-01-02 16:57:12 +0000135}
136
137
138/*******************************************************************************
139 * Enable secure interrupts and use FIQs to route them. Disable legacy bypass
140 * and set the priority mask register to allow all interrupts to trickle in.
141 ******************************************************************************/
Dan Handleyfb42b122014-06-20 09:43:15 +0100142void arm_gic_cpuif_setup(void)
Ian Spray84687392014-01-02 16:57:12 +0000143{
144 unsigned int val;
145
Dan Handleyfb42b122014-06-20 09:43:15 +0100146 assert(g_gicc_base);
147 val = gicc_read_iidr(g_gicc_base);
Ian Spray84687392014-01-02 16:57:12 +0000148
149 /*
150 * If GICv3 we need to do a bit of additional setup. We want to
151 * allow default GICv2 behaviour but allow the next stage to
152 * enable full gicv3 features.
153 */
Dan Handleyfb42b122014-06-20 09:43:15 +0100154 if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3)
Ian Spray84687392014-01-02 16:57:12 +0000155 gicv3_cpuif_setup();
Ian Spray84687392014-01-02 16:57:12 +0000156
157 val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0;
158 val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
159
Dan Handleyfb42b122014-06-20 09:43:15 +0100160 gicc_write_pmr(g_gicc_base, GIC_PRI_MASK);
161 gicc_write_ctlr(g_gicc_base, val);
Ian Spray84687392014-01-02 16:57:12 +0000162}
163
164/*******************************************************************************
165 * Place the cpu interface in a state where it can never make a cpu exit wfi as
166 * as result of an asserted interrupt. This is critical for powering down a cpu
167 ******************************************************************************/
Dan Handleyfb42b122014-06-20 09:43:15 +0100168void arm_gic_cpuif_deactivate(void)
Ian Spray84687392014-01-02 16:57:12 +0000169{
170 unsigned int val;
171
172 /* Disable secure, non-secure interrupts and disable their bypass */
Dan Handleyfb42b122014-06-20 09:43:15 +0100173 assert(g_gicc_base);
174 val = gicc_read_ctlr(g_gicc_base);
Ian Spray84687392014-01-02 16:57:12 +0000175 val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
176 val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
177 val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
Dan Handleyfb42b122014-06-20 09:43:15 +0100178 gicc_write_ctlr(g_gicc_base, val);
Ian Spray84687392014-01-02 16:57:12 +0000179
Dan Handleyfb42b122014-06-20 09:43:15 +0100180 val = gicc_read_iidr(g_gicc_base);
Ian Spray84687392014-01-02 16:57:12 +0000181
182 /*
183 * If GICv3 we need to do a bit of additional setup. Make sure the
184 * RDIST is put to sleep.
185 */
Dan Handleyfb42b122014-06-20 09:43:15 +0100186 if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3)
Ian Spray84687392014-01-02 16:57:12 +0000187 gicv3_cpuif_deactivate();
Ian Spray84687392014-01-02 16:57:12 +0000188}
189
190/*******************************************************************************
191 * Per cpu gic distributor setup which will be done by all cpus after a cold
192 * boot/hotplug. This marks out the secure interrupts & enables them.
193 ******************************************************************************/
Dan Handleyfb42b122014-06-20 09:43:15 +0100194void arm_gic_pcpu_distif_setup(void)
Ian Spray84687392014-01-02 16:57:12 +0000195{
Achin Gupta897333d2015-03-09 21:54:40 +0000196 unsigned int index, irq_num, sec_ppi_sgi_mask;
Ian Spray84687392014-01-02 16:57:12 +0000197
Dan Handleyfb42b122014-06-20 09:43:15 +0100198 assert(g_gicd_base);
Juan Castillo82312952014-10-20 12:27:28 +0100199
Juan Castillo82312952014-10-20 12:27:28 +0100200 /* Setup PPI priorities doing four at a time */
201 for (index = 0; index < 32; index += 4) {
202 gicd_write_ipriorityr(g_gicd_base, index,
203 GICD_IPRIORITYR_DEF_VAL);
204 }
205
Dan Handleyfb42b122014-06-20 09:43:15 +0100206 assert(g_irq_sec_ptr);
Achin Gupta897333d2015-03-09 21:54:40 +0000207 sec_ppi_sgi_mask = 0;
Dan Handleyfb42b122014-06-20 09:43:15 +0100208 for (index = 0; index < g_num_irqs; index++) {
209 irq_num = g_irq_sec_ptr[index];
210 if (irq_num < MIN_SPI_ID) {
Achin Gupta897333d2015-03-09 21:54:40 +0000211 /* We have an SGI or a PPI. They are Group0 at reset */
212 sec_ppi_sgi_mask |= 1U << irq_num;
Dan Handleyfb42b122014-06-20 09:43:15 +0100213 gicd_set_ipriorityr(g_gicd_base, irq_num,
214 GIC_HIGHEST_SEC_PRIORITY);
215 gicd_set_isenabler(g_gicd_base, irq_num);
216 }
217 }
Achin Gupta897333d2015-03-09 21:54:40 +0000218
219 /*
220 * Invert the bitmask to create a mask for non-secure PPIs and
221 * SGIs. Program the GICD_IGROUPR0 with this bit mask. This write will
222 * update the GICR_IGROUPR0 as well in case we are running on a GICv3
223 * system. This is critical if GICD_CTLR.ARE_NS=1.
224 */
225 gicd_write_igroupr(g_gicd_base, 0, ~sec_ppi_sgi_mask);
Ian Spray84687392014-01-02 16:57:12 +0000226}
227
228/*******************************************************************************
Juan Castillo82312952014-10-20 12:27:28 +0100229 * Get the current CPU bit mask from GICD_ITARGETSR0
230 ******************************************************************************/
231static unsigned int arm_gic_get_cpuif_id(void)
232{
233 unsigned int val;
234
235 val = gicd_read_itargetsr(g_gicd_base, 0);
236 return val & GIC_TARGET_CPU_MASK;
237}
238
239/*******************************************************************************
Ian Spray84687392014-01-02 16:57:12 +0000240 * Global gic distributor setup which will be done by the primary cpu after a
241 * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
242 * then enables the secure GIC distributor interface.
243 ******************************************************************************/
Dan Handleyfb42b122014-06-20 09:43:15 +0100244static void arm_gic_distif_setup(void)
Ian Spray84687392014-01-02 16:57:12 +0000245{
Dan Handleyfb42b122014-06-20 09:43:15 +0100246 unsigned int num_ints, ctlr, index, irq_num;
Juan Castillo82312952014-10-20 12:27:28 +0100247 uint8_t target_cpu;
Ian Spray84687392014-01-02 16:57:12 +0000248
249 /* Disable the distributor before going further */
Dan Handleyfb42b122014-06-20 09:43:15 +0100250 assert(g_gicd_base);
251 ctlr = gicd_read_ctlr(g_gicd_base);
Ian Spray84687392014-01-02 16:57:12 +0000252 ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1);
Dan Handleyfb42b122014-06-20 09:43:15 +0100253 gicd_write_ctlr(g_gicd_base, ctlr);
Ian Spray84687392014-01-02 16:57:12 +0000254
255 /*
Juan Castillo82312952014-10-20 12:27:28 +0100256 * Mark out non-secure SPI interrupts. The number of interrupts is
257 * calculated as 32 * (IT_LINES + 1). We do 32 at a time.
Ian Spray84687392014-01-02 16:57:12 +0000258 */
Dan Handleyfb42b122014-06-20 09:43:15 +0100259 num_ints = gicd_read_typer(g_gicd_base) & IT_LINES_NO_MASK;
Juan Castillo82312952014-10-20 12:27:28 +0100260 num_ints = (num_ints + 1) << 5;
261 for (index = MIN_SPI_ID; index < num_ints; index += 32)
262 gicd_write_igroupr(g_gicd_base, index, ~0);
263
264 /* Setup SPI priorities doing four at a time */
265 for (index = MIN_SPI_ID; index < num_ints; index += 4) {
266 gicd_write_ipriorityr(g_gicd_base, index,
267 GICD_IPRIORITYR_DEF_VAL);
268 }
Ian Spray84687392014-01-02 16:57:12 +0000269
Juan Castillo82312952014-10-20 12:27:28 +0100270 /* Read the target CPU mask */
271 target_cpu = arm_gic_get_cpuif_id();
272
273 /* Configure SPI secure interrupts now */
Dan Handleyfb42b122014-06-20 09:43:15 +0100274 assert(g_irq_sec_ptr);
275 for (index = 0; index < g_num_irqs; index++) {
276 irq_num = g_irq_sec_ptr[index];
277 if (irq_num >= MIN_SPI_ID) {
278 /* We have an SPI */
279 gicd_clr_igroupr(g_gicd_base, irq_num);
280 gicd_set_ipriorityr(g_gicd_base, irq_num,
281 GIC_HIGHEST_SEC_PRIORITY);
Juan Castillo82312952014-10-20 12:27:28 +0100282 gicd_set_itargetsr(g_gicd_base, irq_num, target_cpu);
Dan Handleyfb42b122014-06-20 09:43:15 +0100283 gicd_set_isenabler(g_gicd_base, irq_num);
284 }
285 }
Juan Castillo82312952014-10-20 12:27:28 +0100286
287 /*
288 * Configure the SGI and PPI. This is done in a separated function
289 * because each CPU is responsible for initializing its own private
290 * interrupts.
291 */
Dan Handleyfb42b122014-06-20 09:43:15 +0100292 arm_gic_pcpu_distif_setup();
293
294 gicd_write_ctlr(g_gicd_base, ctlr | ENABLE_GRP0);
295}
Ian Spray84687392014-01-02 16:57:12 +0000296
Dan Handleyfb42b122014-06-20 09:43:15 +0100297/*******************************************************************************
298 * Initialize the ARM GIC driver with the provided platform inputs
299******************************************************************************/
Juan Castillo7f1f0622014-09-09 09:49:23 +0100300void arm_gic_init(uintptr_t gicc_base,
301 uintptr_t gicd_base,
302 uintptr_t gicr_base,
303 const unsigned int *irq_sec_ptr,
304 unsigned int num_irqs)
Dan Handleyfb42b122014-06-20 09:43:15 +0100305{
Juan Castillo82312952014-10-20 12:27:28 +0100306 unsigned int val;
307
Dan Handleyfb42b122014-06-20 09:43:15 +0100308 assert(gicc_base);
309 assert(gicd_base);
Dan Handleyfb42b122014-06-20 09:43:15 +0100310 assert(irq_sec_ptr);
Juan Castillo82312952014-10-20 12:27:28 +0100311
Dan Handleyfb42b122014-06-20 09:43:15 +0100312 g_gicc_base = gicc_base;
313 g_gicd_base = gicd_base;
Juan Castillo82312952014-10-20 12:27:28 +0100314
315 val = gicc_read_iidr(g_gicc_base);
316
317 if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) {
318 assert(gicr_base);
319 g_gicr_base = gicr_base;
320 }
321
Dan Handleyfb42b122014-06-20 09:43:15 +0100322 g_irq_sec_ptr = irq_sec_ptr;
323 g_num_irqs = num_irqs;
Ian Spray84687392014-01-02 16:57:12 +0000324}
325
Dan Handleyfb42b122014-06-20 09:43:15 +0100326/*******************************************************************************
327 * Setup the ARM GIC CPU and distributor interfaces.
328******************************************************************************/
329void arm_gic_setup(void)
Ian Spray84687392014-01-02 16:57:12 +0000330{
Dan Handleyfb42b122014-06-20 09:43:15 +0100331 arm_gic_cpuif_setup();
332 arm_gic_distif_setup();
Ian Spray84687392014-01-02 16:57:12 +0000333}
Achin Gupta191e86e2014-05-09 10:03:15 +0100334
335/*******************************************************************************
336 * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
337 * The interrupt controller knows which pin/line it uses to signal a type of
Dan Handleyfb42b122014-06-20 09:43:15 +0100338 * interrupt. This function provides a common implementation of
339 * plat_interrupt_type_to_line() in an ARM GIC environment for optional re-use
340 * across platforms. It lets the interrupt management framework determine
341 * for a type of interrupt and security state, which line should be used in the
342 * SCR_EL3 to control its routing to EL3. The interrupt line is represented as
343 * the bit position of the IRQ or FIQ bit in the SCR_EL3.
Achin Gupta191e86e2014-05-09 10:03:15 +0100344 ******************************************************************************/
Dan Handleyfb42b122014-06-20 09:43:15 +0100345uint32_t arm_gic_interrupt_type_to_line(uint32_t type,
346 uint32_t security_state)
Achin Gupta191e86e2014-05-09 10:03:15 +0100347{
Achin Gupta191e86e2014-05-09 10:03:15 +0100348 assert(type == INTR_TYPE_S_EL1 ||
349 type == INTR_TYPE_EL3 ||
350 type == INTR_TYPE_NS);
351
Juan Castillof558cac2014-06-05 09:45:36 +0100352 assert(sec_state_is_valid(security_state));
Achin Gupta191e86e2014-05-09 10:03:15 +0100353
354 /*
355 * We ignore the security state parameter under the assumption that
356 * both normal and secure worlds are using ARM GICv2. This parameter
357 * will be used when the secure world starts using GICv3.
358 */
Dan Handleyfb42b122014-06-20 09:43:15 +0100359#if ARM_GIC_ARCH == 2
360 return gicv2_interrupt_type_to_line(g_gicc_base, type);
Achin Gupta191e86e2014-05-09 10:03:15 +0100361#else
Dan Handleyfb42b122014-06-20 09:43:15 +0100362#error "Invalid ARM GIC architecture version specified for platform port"
363#endif /* ARM_GIC_ARCH */
Achin Gupta191e86e2014-05-09 10:03:15 +0100364}
365
Dan Handleyfb42b122014-06-20 09:43:15 +0100366#if ARM_GIC_ARCH == 2
Achin Gupta02d36282014-05-04 19:02:52 +0100367/*******************************************************************************
368 * This function returns the type of the highest priority pending interrupt at
369 * the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
370 * interrupt pending.
371 ******************************************************************************/
Dan Handleyfb42b122014-06-20 09:43:15 +0100372uint32_t arm_gic_get_pending_interrupt_type(void)
Achin Gupta02d36282014-05-04 19:02:52 +0100373{
Dan Handley1c54d972014-06-20 12:02:01 +0100374 uint32_t id;
Achin Gupta02d36282014-05-04 19:02:52 +0100375
Dan Handleyfb42b122014-06-20 09:43:15 +0100376 assert(g_gicc_base);
Achin Gupta966b9522015-05-18 10:56:47 +0100377 id = gicc_read_hppir(g_gicc_base) & INT_ID_MASK;
Achin Gupta02d36282014-05-04 19:02:52 +0100378
379 /* Assume that all secure interrupts are S-EL1 interrupts */
380 if (id < 1022)
381 return INTR_TYPE_S_EL1;
382
383 if (id == GIC_SPURIOUS_INTERRUPT)
384 return INTR_TYPE_INVAL;
385
386 return INTR_TYPE_NS;
387}
388
389/*******************************************************************************
390 * This function returns the id of the highest priority pending interrupt at
391 * the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no
392 * interrupt pending.
393 ******************************************************************************/
Dan Handleyfb42b122014-06-20 09:43:15 +0100394uint32_t arm_gic_get_pending_interrupt_id(void)
Achin Gupta02d36282014-05-04 19:02:52 +0100395{
Dan Handleyfb42b122014-06-20 09:43:15 +0100396 uint32_t id;
Achin Gupta02d36282014-05-04 19:02:52 +0100397
Dan Handleyfb42b122014-06-20 09:43:15 +0100398 assert(g_gicc_base);
Achin Gupta966b9522015-05-18 10:56:47 +0100399 id = gicc_read_hppir(g_gicc_base) & INT_ID_MASK;
Achin Gupta02d36282014-05-04 19:02:52 +0100400
401 if (id < 1022)
402 return id;
403
404 if (id == 1023)
405 return INTR_ID_UNAVAILABLE;
406
407 /*
408 * Find out which non-secure interrupt it is under the assumption that
409 * the GICC_CTLR.AckCtl bit is 0.
410 */
Achin Gupta966b9522015-05-18 10:56:47 +0100411 return gicc_read_ahppir(g_gicc_base) & INT_ID_MASK;
Achin Gupta02d36282014-05-04 19:02:52 +0100412}
413
414/*******************************************************************************
415 * This functions reads the GIC cpu interface Interrupt Acknowledge register
416 * to start handling the pending interrupt. It returns the contents of the IAR.
417 ******************************************************************************/
Dan Handleyfb42b122014-06-20 09:43:15 +0100418uint32_t arm_gic_acknowledge_interrupt(void)
Achin Gupta02d36282014-05-04 19:02:52 +0100419{
Dan Handleyfb42b122014-06-20 09:43:15 +0100420 assert(g_gicc_base);
421 return gicc_read_IAR(g_gicc_base);
Achin Gupta02d36282014-05-04 19:02:52 +0100422}
423
424/*******************************************************************************
425 * This functions writes the GIC cpu interface End Of Interrupt register with
426 * the passed value to finish handling the active interrupt
427 ******************************************************************************/
Dan Handleyfb42b122014-06-20 09:43:15 +0100428void arm_gic_end_of_interrupt(uint32_t id)
Achin Gupta02d36282014-05-04 19:02:52 +0100429{
Dan Handleyfb42b122014-06-20 09:43:15 +0100430 assert(g_gicc_base);
431 gicc_write_EOIR(g_gicc_base, id);
Achin Gupta02d36282014-05-04 19:02:52 +0100432}
433
434/*******************************************************************************
435 * This function returns the type of the interrupt id depending upon the group
436 * this interrupt has been configured under by the interrupt controller i.e.
437 * group0 or group1.
438 ******************************************************************************/
Dan Handleyfb42b122014-06-20 09:43:15 +0100439uint32_t arm_gic_get_interrupt_type(uint32_t id)
Achin Gupta02d36282014-05-04 19:02:52 +0100440{
441 uint32_t group;
442
Dan Handleyfb42b122014-06-20 09:43:15 +0100443 assert(g_gicd_base);
444 group = gicd_get_igroupr(g_gicd_base, id);
Achin Gupta02d36282014-05-04 19:02:52 +0100445
446 /* Assume that all secure interrupts are S-EL1 interrupts */
447 if (group == GRP0)
448 return INTR_TYPE_S_EL1;
449 else
450 return INTR_TYPE_NS;
451}
452
453#else
Dan Handleyfb42b122014-06-20 09:43:15 +0100454#error "Invalid ARM GIC architecture version specified for platform port"
455#endif /* ARM_GIC_ARCH */