Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch_helpers.h> |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame^] | 32 | #include <assert.h> |
| 33 | #include <bl_common.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 34 | #include <debug.h> |
Dan Handley | 930ee2e | 2014-04-17 17:48:52 +0100 | [diff] [blame] | 35 | #include <gic_v2.h> |
| 36 | #include <gic_v3.h> |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame^] | 37 | #include <interrupt_mgmt.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 38 | #include <platform.h> |
| 39 | #include <stdint.h> |
Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 40 | |
| 41 | |
| 42 | /******************************************************************************* |
| 43 | * TODO: Revisit if priorities are being set such that no non-secure interrupt |
| 44 | * can have a higher priority than a secure one as recommended in the GICv2 spec |
| 45 | ******************************************************************************/ |
| 46 | |
| 47 | /******************************************************************************* |
| 48 | * This function does some minimal GICv3 configuration. The Firmware itself does |
| 49 | * not fully support GICv3 at this time and relies on GICv2 emulation as |
| 50 | * provided by GICv3. This function allows software (like Linux) in later stages |
| 51 | * to use full GICv3 features. |
| 52 | ******************************************************************************/ |
| 53 | void gicv3_cpuif_setup(void) |
| 54 | { |
Harry Liebel | eaec590 | 2013-12-12 13:00:29 +0000 | [diff] [blame] | 55 | unsigned int scr_val, val; |
| 56 | uintptr_t base; |
Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 57 | |
| 58 | /* |
| 59 | * When CPUs come out of reset they have their GICR_WAKER.ProcessorSleep |
| 60 | * bit set. In order to allow interrupts to get routed to the CPU we |
| 61 | * need to clear this bit if set and wait for GICR_WAKER.ChildrenAsleep |
| 62 | * to clear (GICv3 Architecture specification 5.4.23). |
| 63 | * GICR_WAKER is NOT banked per CPU, compute the correct base address |
| 64 | * per CPU. |
Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 65 | */ |
Harry Liebel | eaec590 | 2013-12-12 13:00:29 +0000 | [diff] [blame] | 66 | base = gicv3_get_rdist(BASE_GICR_BASE, read_mpidr()); |
| 67 | if (base == (uintptr_t)NULL) { |
| 68 | /* No re-distributor base address. This interface cannot be |
| 69 | * configured. |
| 70 | */ |
| 71 | panic(); |
| 72 | } |
| 73 | |
Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 74 | val = gicr_read_waker(base); |
| 75 | |
| 76 | val &= ~WAKER_PS; |
| 77 | gicr_write_waker(base, val); |
| 78 | dsb(); |
| 79 | |
| 80 | /* We need to wait for ChildrenAsleep to clear. */ |
| 81 | val = gicr_read_waker(base); |
| 82 | while (val & WAKER_CA) { |
| 83 | val = gicr_read_waker(base); |
| 84 | } |
| 85 | |
| 86 | /* |
| 87 | * We need to set SCR_EL3.NS in order to see GICv3 non-secure state. |
| 88 | * Restore SCR_EL3.NS again before exit. |
| 89 | */ |
| 90 | scr_val = read_scr(); |
| 91 | write_scr(scr_val | SCR_NS_BIT); |
Andrew Thoelke | 42e75a7 | 2014-04-28 12:28:39 +0100 | [diff] [blame] | 92 | isb(); /* ensure NS=1 takes effect before accessing ICC_SRE_EL2 */ |
Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 93 | |
| 94 | /* |
| 95 | * By default EL2 and NS-EL1 software should be able to enable GICv3 |
| 96 | * System register access without any configuration at EL3. But it turns |
| 97 | * out that GICC PMR as set in GICv2 mode does not affect GICv3 mode. So |
| 98 | * we need to set it here again. In order to do that we need to enable |
| 99 | * register access. We leave it enabled as it should be fine and might |
| 100 | * prevent problems with later software trying to access GIC System |
| 101 | * Registers. |
| 102 | */ |
| 103 | val = read_icc_sre_el3(); |
| 104 | write_icc_sre_el3(val | ICC_SRE_EN | ICC_SRE_SRE); |
| 105 | |
| 106 | val = read_icc_sre_el2(); |
| 107 | write_icc_sre_el2(val | ICC_SRE_EN | ICC_SRE_SRE); |
| 108 | |
Jon Medhurst | d0212c2 | 2014-02-11 14:48:56 +0000 | [diff] [blame] | 109 | write_icc_pmr_el1(GIC_PRI_MASK); |
Andrew Thoelke | 42e75a7 | 2014-04-28 12:28:39 +0100 | [diff] [blame] | 110 | isb(); /* commite ICC_* changes before setting NS=0 */ |
Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 111 | |
| 112 | /* Restore SCR_EL3 */ |
| 113 | write_scr(scr_val); |
Andrew Thoelke | 42e75a7 | 2014-04-28 12:28:39 +0100 | [diff] [blame] | 114 | isb(); /* ensure NS=0 takes effect immediately */ |
Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 115 | } |
| 116 | |
| 117 | /******************************************************************************* |
| 118 | * This function does some minimal GICv3 configuration when cores go |
| 119 | * down. |
| 120 | ******************************************************************************/ |
| 121 | void gicv3_cpuif_deactivate(void) |
| 122 | { |
Harry Liebel | eaec590 | 2013-12-12 13:00:29 +0000 | [diff] [blame] | 123 | unsigned int val; |
| 124 | uintptr_t base; |
Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 125 | |
| 126 | /* |
| 127 | * When taking CPUs down we need to set GICR_WAKER.ProcessorSleep and |
| 128 | * wait for GICR_WAKER.ChildrenAsleep to get set. |
| 129 | * (GICv3 Architecture specification 5.4.23). |
| 130 | * GICR_WAKER is NOT banked per CPU, compute the correct base address |
| 131 | * per CPU. |
Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 132 | */ |
Harry Liebel | eaec590 | 2013-12-12 13:00:29 +0000 | [diff] [blame] | 133 | base = gicv3_get_rdist(BASE_GICR_BASE, read_mpidr()); |
| 134 | if (base == (uintptr_t)NULL) { |
| 135 | /* No re-distributor base address. This interface cannot be |
| 136 | * configured. |
| 137 | */ |
| 138 | panic(); |
| 139 | } |
| 140 | |
Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 141 | val = gicr_read_waker(base); |
| 142 | val |= WAKER_PS; |
| 143 | gicr_write_waker(base, val); |
| 144 | dsb(); |
| 145 | |
| 146 | /* We need to wait for ChildrenAsleep to set. */ |
| 147 | val = gicr_read_waker(base); |
| 148 | while ((val & WAKER_CA) == 0) { |
| 149 | val = gicr_read_waker(base); |
| 150 | } |
| 151 | } |
| 152 | |
| 153 | |
| 154 | /******************************************************************************* |
| 155 | * Enable secure interrupts and use FIQs to route them. Disable legacy bypass |
| 156 | * and set the priority mask register to allow all interrupts to trickle in. |
| 157 | ******************************************************************************/ |
| 158 | void gic_cpuif_setup(unsigned int gicc_base) |
| 159 | { |
| 160 | unsigned int val; |
| 161 | |
| 162 | val = gicc_read_iidr(gicc_base); |
| 163 | |
| 164 | /* |
| 165 | * If GICv3 we need to do a bit of additional setup. We want to |
| 166 | * allow default GICv2 behaviour but allow the next stage to |
| 167 | * enable full gicv3 features. |
| 168 | */ |
| 169 | if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) { |
| 170 | gicv3_cpuif_setup(); |
| 171 | } |
| 172 | |
| 173 | val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0; |
| 174 | val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; |
| 175 | |
Jon Medhurst | d0212c2 | 2014-02-11 14:48:56 +0000 | [diff] [blame] | 176 | gicc_write_pmr(gicc_base, GIC_PRI_MASK); |
Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 177 | gicc_write_ctlr(gicc_base, val); |
| 178 | } |
| 179 | |
| 180 | /******************************************************************************* |
| 181 | * Place the cpu interface in a state where it can never make a cpu exit wfi as |
| 182 | * as result of an asserted interrupt. This is critical for powering down a cpu |
| 183 | ******************************************************************************/ |
| 184 | void gic_cpuif_deactivate(unsigned int gicc_base) |
| 185 | { |
| 186 | unsigned int val; |
| 187 | |
| 188 | /* Disable secure, non-secure interrupts and disable their bypass */ |
| 189 | val = gicc_read_ctlr(gicc_base); |
| 190 | val &= ~(ENABLE_GRP0 | ENABLE_GRP1); |
| 191 | val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; |
| 192 | val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; |
| 193 | gicc_write_ctlr(gicc_base, val); |
| 194 | |
| 195 | val = gicc_read_iidr(gicc_base); |
| 196 | |
| 197 | /* |
| 198 | * If GICv3 we need to do a bit of additional setup. Make sure the |
| 199 | * RDIST is put to sleep. |
| 200 | */ |
| 201 | if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) { |
| 202 | gicv3_cpuif_deactivate(); |
| 203 | } |
| 204 | } |
| 205 | |
| 206 | /******************************************************************************* |
| 207 | * Per cpu gic distributor setup which will be done by all cpus after a cold |
| 208 | * boot/hotplug. This marks out the secure interrupts & enables them. |
| 209 | ******************************************************************************/ |
| 210 | void gic_pcpu_distif_setup(unsigned int gicd_base) |
| 211 | { |
| 212 | gicd_write_igroupr(gicd_base, 0, ~0); |
| 213 | |
| 214 | gicd_clr_igroupr(gicd_base, IRQ_SEC_PHY_TIMER); |
| 215 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_0); |
| 216 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_1); |
| 217 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_2); |
| 218 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_3); |
| 219 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_4); |
| 220 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_5); |
| 221 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_6); |
| 222 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_7); |
| 223 | |
Jon Medhurst | d0212c2 | 2014-02-11 14:48:56 +0000 | [diff] [blame] | 224 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY); |
| 225 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY); |
| 226 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY); |
| 227 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY); |
| 228 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY); |
| 229 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY); |
| 230 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY); |
| 231 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY); |
| 232 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY); |
Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 233 | |
| 234 | gicd_set_isenabler(gicd_base, IRQ_SEC_PHY_TIMER); |
| 235 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_0); |
| 236 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_1); |
| 237 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_2); |
| 238 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_3); |
| 239 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_4); |
| 240 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_5); |
| 241 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_6); |
| 242 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_7); |
| 243 | } |
| 244 | |
| 245 | /******************************************************************************* |
| 246 | * Global gic distributor setup which will be done by the primary cpu after a |
| 247 | * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It |
| 248 | * then enables the secure GIC distributor interface. |
| 249 | ******************************************************************************/ |
| 250 | void gic_distif_setup(unsigned int gicd_base) |
| 251 | { |
| 252 | unsigned int ctr, num_ints, ctlr; |
| 253 | |
| 254 | /* Disable the distributor before going further */ |
| 255 | ctlr = gicd_read_ctlr(gicd_base); |
| 256 | ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1); |
| 257 | gicd_write_ctlr(gicd_base, ctlr); |
| 258 | |
| 259 | /* |
| 260 | * Mark out non-secure interrupts. Calculate number of |
| 261 | * IGROUPR registers to consider. Will be equal to the |
| 262 | * number of IT_LINES |
| 263 | */ |
| 264 | num_ints = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK; |
| 265 | num_ints++; |
| 266 | for (ctr = 0; ctr < num_ints; ctr++) |
| 267 | gicd_write_igroupr(gicd_base, ctr << IGROUPR_SHIFT, ~0); |
| 268 | |
| 269 | /* Configure secure interrupts now */ |
| 270 | gicd_clr_igroupr(gicd_base, IRQ_TZ_WDOG); |
Jon Medhurst | d0212c2 | 2014-02-11 14:48:56 +0000 | [diff] [blame] | 271 | gicd_set_ipriorityr(gicd_base, IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY); |
Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 272 | gicd_set_itargetsr(gicd_base, IRQ_TZ_WDOG, |
| 273 | platform_get_core_pos(read_mpidr())); |
| 274 | gicd_set_isenabler(gicd_base, IRQ_TZ_WDOG); |
| 275 | gic_pcpu_distif_setup(gicd_base); |
| 276 | |
| 277 | gicd_write_ctlr(gicd_base, ctlr | ENABLE_GRP0); |
| 278 | } |
| 279 | |
| 280 | void gic_setup(void) |
| 281 | { |
| 282 | unsigned int gicd_base, gicc_base; |
| 283 | |
| 284 | gicd_base = platform_get_cfgvar(CONFIG_GICD_ADDR); |
| 285 | gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR); |
| 286 | |
| 287 | gic_cpuif_setup(gicc_base); |
| 288 | gic_distif_setup(gicd_base); |
| 289 | } |
Achin Gupta | 191e86e | 2014-05-09 10:03:15 +0100 | [diff] [blame^] | 290 | |
| 291 | /******************************************************************************* |
| 292 | * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. |
| 293 | * The interrupt controller knows which pin/line it uses to signal a type of |
| 294 | * interrupt. The platform knows which interrupt controller type is being used |
| 295 | * in a particular security state e.g. with an ARM GIC, normal world could use |
| 296 | * the GICv2 features while the secure world could use GICv3 features and vice |
| 297 | * versa. |
| 298 | * This function is exported by the platform to let the interrupt management |
| 299 | * framework determine for a type of interrupt and security state, which line |
| 300 | * should be used in the SCR_EL3 to control its routing to EL3. The interrupt |
| 301 | * line is represented as the bit position of the IRQ or FIQ bit in the SCR_EL3. |
| 302 | ******************************************************************************/ |
| 303 | uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state) |
| 304 | { |
| 305 | uint32_t gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR); |
| 306 | |
| 307 | assert(type == INTR_TYPE_S_EL1 || |
| 308 | type == INTR_TYPE_EL3 || |
| 309 | type == INTR_TYPE_NS); |
| 310 | |
| 311 | assert(security_state == NON_SECURE || security_state == SECURE); |
| 312 | |
| 313 | /* |
| 314 | * We ignore the security state parameter under the assumption that |
| 315 | * both normal and secure worlds are using ARM GICv2. This parameter |
| 316 | * will be used when the secure world starts using GICv3. |
| 317 | */ |
| 318 | #if FVP_GIC_ARCH == 2 |
| 319 | return gicv2_interrupt_type_to_line(gicc_base, type); |
| 320 | #else |
| 321 | #error "Invalid GIC architecture version specified for FVP port" |
| 322 | #endif |
| 323 | } |
| 324 | |