Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame^] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch_helpers.h> |
| 32 | #include <platform.h> |
| 33 | #include <gic.h> |
| 34 | |
| 35 | |
| 36 | /******************************************************************************* |
| 37 | * TODO: Revisit if priorities are being set such that no non-secure interrupt |
| 38 | * can have a higher priority than a secure one as recommended in the GICv2 spec |
| 39 | ******************************************************************************/ |
| 40 | |
| 41 | /******************************************************************************* |
| 42 | * This function does some minimal GICv3 configuration. The Firmware itself does |
| 43 | * not fully support GICv3 at this time and relies on GICv2 emulation as |
| 44 | * provided by GICv3. This function allows software (like Linux) in later stages |
| 45 | * to use full GICv3 features. |
| 46 | ******************************************************************************/ |
| 47 | void gicv3_cpuif_setup(void) |
| 48 | { |
| 49 | unsigned int scr_val, val, base; |
| 50 | |
| 51 | /* |
| 52 | * When CPUs come out of reset they have their GICR_WAKER.ProcessorSleep |
| 53 | * bit set. In order to allow interrupts to get routed to the CPU we |
| 54 | * need to clear this bit if set and wait for GICR_WAKER.ChildrenAsleep |
| 55 | * to clear (GICv3 Architecture specification 5.4.23). |
| 56 | * GICR_WAKER is NOT banked per CPU, compute the correct base address |
| 57 | * per CPU. |
| 58 | * |
| 59 | * TODO: |
| 60 | * For GICv4 we also need to adjust the Base address based on |
| 61 | * GICR_TYPER.VLPIS |
| 62 | */ |
| 63 | base = BASE_GICR_BASE + |
| 64 | (platform_get_core_pos(read_mpidr()) << GICR_PCPUBASE_SHIFT); |
| 65 | val = gicr_read_waker(base); |
| 66 | |
| 67 | val &= ~WAKER_PS; |
| 68 | gicr_write_waker(base, val); |
| 69 | dsb(); |
| 70 | |
| 71 | /* We need to wait for ChildrenAsleep to clear. */ |
| 72 | val = gicr_read_waker(base); |
| 73 | while (val & WAKER_CA) { |
| 74 | val = gicr_read_waker(base); |
| 75 | } |
| 76 | |
| 77 | /* |
| 78 | * We need to set SCR_EL3.NS in order to see GICv3 non-secure state. |
| 79 | * Restore SCR_EL3.NS again before exit. |
| 80 | */ |
| 81 | scr_val = read_scr(); |
| 82 | write_scr(scr_val | SCR_NS_BIT); |
| 83 | |
| 84 | /* |
| 85 | * By default EL2 and NS-EL1 software should be able to enable GICv3 |
| 86 | * System register access without any configuration at EL3. But it turns |
| 87 | * out that GICC PMR as set in GICv2 mode does not affect GICv3 mode. So |
| 88 | * we need to set it here again. In order to do that we need to enable |
| 89 | * register access. We leave it enabled as it should be fine and might |
| 90 | * prevent problems with later software trying to access GIC System |
| 91 | * Registers. |
| 92 | */ |
| 93 | val = read_icc_sre_el3(); |
| 94 | write_icc_sre_el3(val | ICC_SRE_EN | ICC_SRE_SRE); |
| 95 | |
| 96 | val = read_icc_sre_el2(); |
| 97 | write_icc_sre_el2(val | ICC_SRE_EN | ICC_SRE_SRE); |
| 98 | |
| 99 | write_icc_pmr_el1(MAX_PRI_VAL); |
| 100 | |
| 101 | /* Restore SCR_EL3 */ |
| 102 | write_scr(scr_val); |
| 103 | } |
| 104 | |
| 105 | /******************************************************************************* |
| 106 | * This function does some minimal GICv3 configuration when cores go |
| 107 | * down. |
| 108 | ******************************************************************************/ |
| 109 | void gicv3_cpuif_deactivate(void) |
| 110 | { |
| 111 | unsigned int val, base; |
| 112 | |
| 113 | /* |
| 114 | * When taking CPUs down we need to set GICR_WAKER.ProcessorSleep and |
| 115 | * wait for GICR_WAKER.ChildrenAsleep to get set. |
| 116 | * (GICv3 Architecture specification 5.4.23). |
| 117 | * GICR_WAKER is NOT banked per CPU, compute the correct base address |
| 118 | * per CPU. |
| 119 | * |
| 120 | * TODO: |
| 121 | * For GICv4 we also need to adjust the Base address based on |
| 122 | * GICR_TYPER.VLPIS |
| 123 | */ |
| 124 | base = BASE_GICR_BASE + |
| 125 | (platform_get_core_pos(read_mpidr()) << GICR_PCPUBASE_SHIFT); |
| 126 | val = gicr_read_waker(base); |
| 127 | val |= WAKER_PS; |
| 128 | gicr_write_waker(base, val); |
| 129 | dsb(); |
| 130 | |
| 131 | /* We need to wait for ChildrenAsleep to set. */ |
| 132 | val = gicr_read_waker(base); |
| 133 | while ((val & WAKER_CA) == 0) { |
| 134 | val = gicr_read_waker(base); |
| 135 | } |
| 136 | } |
| 137 | |
| 138 | |
| 139 | /******************************************************************************* |
| 140 | * Enable secure interrupts and use FIQs to route them. Disable legacy bypass |
| 141 | * and set the priority mask register to allow all interrupts to trickle in. |
| 142 | ******************************************************************************/ |
| 143 | void gic_cpuif_setup(unsigned int gicc_base) |
| 144 | { |
| 145 | unsigned int val; |
| 146 | |
| 147 | val = gicc_read_iidr(gicc_base); |
| 148 | |
| 149 | /* |
| 150 | * If GICv3 we need to do a bit of additional setup. We want to |
| 151 | * allow default GICv2 behaviour but allow the next stage to |
| 152 | * enable full gicv3 features. |
| 153 | */ |
| 154 | if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) { |
| 155 | gicv3_cpuif_setup(); |
| 156 | } |
| 157 | |
| 158 | val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0; |
| 159 | val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1; |
| 160 | |
| 161 | gicc_write_pmr(gicc_base, MAX_PRI_VAL); |
| 162 | gicc_write_ctlr(gicc_base, val); |
| 163 | } |
| 164 | |
| 165 | /******************************************************************************* |
| 166 | * Place the cpu interface in a state where it can never make a cpu exit wfi as |
| 167 | * as result of an asserted interrupt. This is critical for powering down a cpu |
| 168 | ******************************************************************************/ |
| 169 | void gic_cpuif_deactivate(unsigned int gicc_base) |
| 170 | { |
| 171 | unsigned int val; |
| 172 | |
| 173 | /* Disable secure, non-secure interrupts and disable their bypass */ |
| 174 | val = gicc_read_ctlr(gicc_base); |
| 175 | val &= ~(ENABLE_GRP0 | ENABLE_GRP1); |
| 176 | val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0; |
| 177 | val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1; |
| 178 | gicc_write_ctlr(gicc_base, val); |
| 179 | |
| 180 | val = gicc_read_iidr(gicc_base); |
| 181 | |
| 182 | /* |
| 183 | * If GICv3 we need to do a bit of additional setup. Make sure the |
| 184 | * RDIST is put to sleep. |
| 185 | */ |
| 186 | if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3) { |
| 187 | gicv3_cpuif_deactivate(); |
| 188 | } |
| 189 | } |
| 190 | |
| 191 | /******************************************************************************* |
| 192 | * Per cpu gic distributor setup which will be done by all cpus after a cold |
| 193 | * boot/hotplug. This marks out the secure interrupts & enables them. |
| 194 | ******************************************************************************/ |
| 195 | void gic_pcpu_distif_setup(unsigned int gicd_base) |
| 196 | { |
| 197 | gicd_write_igroupr(gicd_base, 0, ~0); |
| 198 | |
| 199 | gicd_clr_igroupr(gicd_base, IRQ_SEC_PHY_TIMER); |
| 200 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_0); |
| 201 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_1); |
| 202 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_2); |
| 203 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_3); |
| 204 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_4); |
| 205 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_5); |
| 206 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_6); |
| 207 | gicd_clr_igroupr(gicd_base, IRQ_SEC_SGI_7); |
| 208 | |
| 209 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_PHY_TIMER, MAX_PRI_VAL); |
| 210 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_0, MAX_PRI_VAL); |
| 211 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_1, MAX_PRI_VAL); |
| 212 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_2, MAX_PRI_VAL); |
| 213 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_3, MAX_PRI_VAL); |
| 214 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_4, MAX_PRI_VAL); |
| 215 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_5, MAX_PRI_VAL); |
| 216 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_6, MAX_PRI_VAL); |
| 217 | gicd_set_ipriorityr(gicd_base, IRQ_SEC_SGI_7, MAX_PRI_VAL); |
| 218 | |
| 219 | gicd_set_isenabler(gicd_base, IRQ_SEC_PHY_TIMER); |
| 220 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_0); |
| 221 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_1); |
| 222 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_2); |
| 223 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_3); |
| 224 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_4); |
| 225 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_5); |
| 226 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_6); |
| 227 | gicd_set_isenabler(gicd_base, IRQ_SEC_SGI_7); |
| 228 | } |
| 229 | |
| 230 | /******************************************************************************* |
| 231 | * Global gic distributor setup which will be done by the primary cpu after a |
| 232 | * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It |
| 233 | * then enables the secure GIC distributor interface. |
| 234 | ******************************************************************************/ |
| 235 | void gic_distif_setup(unsigned int gicd_base) |
| 236 | { |
| 237 | unsigned int ctr, num_ints, ctlr; |
| 238 | |
| 239 | /* Disable the distributor before going further */ |
| 240 | ctlr = gicd_read_ctlr(gicd_base); |
| 241 | ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1); |
| 242 | gicd_write_ctlr(gicd_base, ctlr); |
| 243 | |
| 244 | /* |
| 245 | * Mark out non-secure interrupts. Calculate number of |
| 246 | * IGROUPR registers to consider. Will be equal to the |
| 247 | * number of IT_LINES |
| 248 | */ |
| 249 | num_ints = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK; |
| 250 | num_ints++; |
| 251 | for (ctr = 0; ctr < num_ints; ctr++) |
| 252 | gicd_write_igroupr(gicd_base, ctr << IGROUPR_SHIFT, ~0); |
| 253 | |
| 254 | /* Configure secure interrupts now */ |
| 255 | gicd_clr_igroupr(gicd_base, IRQ_TZ_WDOG); |
| 256 | gicd_set_ipriorityr(gicd_base, IRQ_TZ_WDOG, MAX_PRI_VAL); |
| 257 | gicd_set_itargetsr(gicd_base, IRQ_TZ_WDOG, |
| 258 | platform_get_core_pos(read_mpidr())); |
| 259 | gicd_set_isenabler(gicd_base, IRQ_TZ_WDOG); |
| 260 | gic_pcpu_distif_setup(gicd_base); |
| 261 | |
| 262 | gicd_write_ctlr(gicd_base, ctlr | ENABLE_GRP0); |
| 263 | } |
| 264 | |
| 265 | void gic_setup(void) |
| 266 | { |
| 267 | unsigned int gicd_base, gicc_base; |
| 268 | |
| 269 | gicd_base = platform_get_cfgvar(CONFIG_GICD_ADDR); |
| 270 | gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR); |
| 271 | |
| 272 | gic_cpuif_setup(gicc_base); |
| 273 | gic_distif_setup(gicd_base); |
| 274 | } |