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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Soby Mathew0b4c5a32016-10-21 17:51:22 +01002 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch_helpers.h>
Soby Mathew0d9e8522015-07-15 13:36:24 +010032#include <arm_def.h>
Soby Mathew61e8d0b2015-10-12 17:32:29 +010033#include <arm_gic.h>
Dan Handley9df48042015-03-19 18:58:55 +000034#include <assert.h>
Soby Mathew61e8d0b2015-10-12 17:32:29 +010035#include <console.h>
Dan Handley9df48042015-03-19 18:58:55 +000036#include <errno.h>
Soby Mathew7799cf72015-04-16 14:49:09 +010037#include <plat_arm.h>
Soby Mathewfeac8fc2015-09-29 15:47:16 +010038#include <platform_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000039#include <psci.h>
40
Soby Mathew0b4c5a32016-10-21 17:51:22 +010041/* Allow ARM Standard platforms to override this function */
42#pragma weak plat_arm_psci_override_pm_ops
43
Soby Mathewfeac8fc2015-09-29 15:47:16 +010044/* Standard ARM platforms are expected to export plat_arm_psci_pm_ops */
Soby Mathew0b4c5a32016-10-21 17:51:22 +010045extern plat_psci_ops_t plat_arm_psci_pm_ops;
Soby Mathewfeac8fc2015-09-29 15:47:16 +010046
Soby Mathew7799cf72015-04-16 14:49:09 +010047#if ARM_RECOM_STATE_ID_ENC
48extern unsigned int arm_pm_idle_states[];
49#endif /* __ARM_RECOM_STATE_ID_ENC__ */
50
Soby Mathew7799cf72015-04-16 14:49:09 +010051#if !ARM_RECOM_STATE_ID_ENC
Dan Handley9df48042015-03-19 18:58:55 +000052/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +010053 * ARM standard platform handler called to check the validity of the power state
54 * parameter.
Dan Handley9df48042015-03-19 18:58:55 +000055 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +010056int arm_validate_power_state(unsigned int power_state,
57 psci_power_state_t *req_state)
Dan Handley9df48042015-03-19 18:58:55 +000058{
Soby Mathewfec4eb72015-07-01 16:16:20 +010059 int pstate = psci_get_pstate_type(power_state);
60 int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
61 int i;
Dan Handley9df48042015-03-19 18:58:55 +000062
Soby Mathewfec4eb72015-07-01 16:16:20 +010063 assert(req_state);
Dan Handley9df48042015-03-19 18:58:55 +000064
Soby Mathewfec4eb72015-07-01 16:16:20 +010065 if (pwr_lvl > PLAT_MAX_PWR_LVL)
66 return PSCI_E_INVALID_PARAMS;
Dan Handley9df48042015-03-19 18:58:55 +000067
Dan Handley9df48042015-03-19 18:58:55 +000068 /* Sanity check the requested state */
Soby Mathewfec4eb72015-07-01 16:16:20 +010069 if (pstate == PSTATE_TYPE_STANDBY) {
Dan Handley9df48042015-03-19 18:58:55 +000070 /*
Soby Mathewfec4eb72015-07-01 16:16:20 +010071 * It's possible to enter standby only on power level 0
72 * Ignore any other power level.
Dan Handley9df48042015-03-19 18:58:55 +000073 */
Soby Mathewfec4eb72015-07-01 16:16:20 +010074 if (pwr_lvl != ARM_PWR_LVL0)
Dan Handley9df48042015-03-19 18:58:55 +000075 return PSCI_E_INVALID_PARAMS;
Soby Mathewfec4eb72015-07-01 16:16:20 +010076
77 req_state->pwr_domain_state[ARM_PWR_LVL0] =
78 ARM_LOCAL_STATE_RET;
79 } else {
80 for (i = ARM_PWR_LVL0; i <= pwr_lvl; i++)
81 req_state->pwr_domain_state[i] =
82 ARM_LOCAL_STATE_OFF;
Dan Handley9df48042015-03-19 18:58:55 +000083 }
84
85 /*
86 * We expect the 'state id' to be zero.
87 */
88 if (psci_get_pstate_id(power_state))
89 return PSCI_E_INVALID_PARAMS;
90
Soby Mathew7799cf72015-04-16 14:49:09 +010091 return PSCI_E_SUCCESS;
92}
93
94#else
95/*******************************************************************************
96 * ARM standard platform handler called to check the validity of the power
97 * state parameter. The power state parameter has to be a composite power
98 * state.
99 ******************************************************************************/
100int arm_validate_power_state(unsigned int power_state,
101 psci_power_state_t *req_state)
102{
103 unsigned int state_id;
104 int i;
105
106 assert(req_state);
107
108 /*
109 * Currently we are using a linear search for finding the matching
110 * entry in the idle power state array. This can be made a binary
111 * search if the number of entries justify the additional complexity.
112 */
113 for (i = 0; !!arm_pm_idle_states[i]; i++) {
114 if (power_state == arm_pm_idle_states[i])
115 break;
116 }
117
118 /* Return error if entry not found in the idle state array */
119 if (!arm_pm_idle_states[i])
120 return PSCI_E_INVALID_PARAMS;
121
122 i = 0;
123 state_id = psci_get_pstate_id(power_state);
124
125 /* Parse the State ID and populate the state info parameter */
126 while (state_id) {
127 req_state->pwr_domain_state[i++] = state_id &
128 ARM_LOCAL_PSTATE_MASK;
129 state_id >>= ARM_LOCAL_PSTATE_WIDTH;
130 }
131
Dan Handley9df48042015-03-19 18:58:55 +0000132 return PSCI_E_SUCCESS;
133}
Soby Mathew7799cf72015-04-16 14:49:09 +0100134#endif /* __ARM_RECOM_STATE_ID_ENC__ */
Soby Mathew0d9e8522015-07-15 13:36:24 +0100135
136/*******************************************************************************
137 * ARM standard platform handler called to check the validity of the non secure
138 * entrypoint.
139 ******************************************************************************/
140int arm_validate_ns_entrypoint(uintptr_t entrypoint)
141{
142 /*
143 * Check if the non secure entrypoint lies within the non
144 * secure DRAM.
145 */
146 if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint <
147 (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE)))
148 return PSCI_E_SUCCESS;
149 if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint <
150 (ARM_DRAM2_BASE + ARM_DRAM2_SIZE)))
151 return PSCI_E_SUCCESS;
152
153 return PSCI_E_INVALID_ADDRESS;
154}
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100155
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100156/******************************************************************************
Soby Mathew0b4c5a32016-10-21 17:51:22 +0100157 * Default definition on ARM standard platforms to override the plat_psci_ops.
158 *****************************************************************************/
159const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
160{
161 return ops;
162}
163
164/******************************************************************************
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100165 * Helper function to resume the platform from system suspend. Reinitialize
166 * the system components which are not in the Always ON power domain.
167 * TODO: Unify the platform setup when waking up from cold boot and system
168 * resume in arm_bl31_platform_setup().
169 *****************************************************************************/
170void arm_system_pwr_domain_resume(void)
171{
Soby Mathew2fd66be2015-12-09 11:38:43 +0000172 console_init(PLAT_ARM_BL31_RUN_UART_BASE, PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ,
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100173 ARM_CONSOLE_BAUDRATE);
174
175 /* Assert system power domain is available on the platform */
176 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2);
177
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000178 /*
179 * TODO: On GICv3 systems, figure out whether the core that wakes up
180 * first from system suspend need to initialize the re-distributor
181 * interface of all the other suspended cores.
182 */
183 plat_arm_gic_init();
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100184 plat_arm_security_setup();
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100185 arm_configure_sys_timer();
186}
187
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100188/*******************************************************************************
189 * Private function to program the mailbox for a cpu before it is released
190 * from reset. This function assumes that the Trusted mail box base is within
191 * the ARM_SHARED_RAM region
192 ******************************************************************************/
Sandrine Bailleux03897bb2015-11-26 16:31:34 +0000193void arm_program_trusted_mailbox(uintptr_t address)
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100194{
195 uintptr_t *mailbox = (void *) PLAT_ARM_TRUSTED_MAILBOX_BASE;
196
197 *mailbox = address;
198
199 /*
200 * Ensure that the PLAT_ARM_TRUSTED_MAILBOX_BASE is within
201 * ARM_SHARED_RAM region.
202 */
203 assert((PLAT_ARM_TRUSTED_MAILBOX_BASE >= ARM_SHARED_RAM_BASE) &&
204 ((PLAT_ARM_TRUSTED_MAILBOX_BASE + sizeof(*mailbox)) <= \
205 (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE)));
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100206}
207
208/*******************************************************************************
209 * The ARM Standard platform definition of platform porting API
210 * `plat_setup_psci_ops`.
211 ******************************************************************************/
212int plat_setup_psci_ops(uintptr_t sec_entrypoint,
213 const plat_psci_ops_t **psci_ops)
214{
Soby Mathew0b4c5a32016-10-21 17:51:22 +0100215 *psci_ops = plat_arm_psci_override_pm_ops(&plat_arm_psci_pm_ops);
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100216
217 /* Setup mailbox with entry point. */
218 arm_program_trusted_mailbox(sec_entrypoint);
219 return 0;
220}