blob: 4f7110562962e77404f257e54be3a6f434893117 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Antonio Nino Diaze40306b2017-01-13 15:03:07 +00002 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __ARCH_HELPERS_H__
32#define __ARCH_HELPERS_H__
33
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010034#include <arch.h> /* for additional register definitions */
35#include <cdefs.h> /* For __dead2 */
36#include <stdint.h>
Antonio Nino Diaze40306b2017-01-13 15:03:07 +000037#include <sys/types.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010038
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010039/**********************************************************************
40 * Macros which create inline functions to read or write CPU system
41 * registers
42 *********************************************************************/
43
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000044#define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
45static inline uint64_t read_ ## _name(void) \
46{ \
47 uint64_t v; \
48 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \
49 return v; \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010050}
51
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000052#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
53static inline void write_ ## _name(uint64_t v) \
54{ \
55 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010056}
57
58#define _DEFINE_SYSREG_WRITE_CONST_FUNC(_name, _reg_name) \
Sandrine Bailleux30c231b2015-01-07 16:36:11 +000059static inline void write_ ## _name(const uint64_t v) \
60{ \
61 __asm__ volatile ("msr " #_reg_name ", %0" : : "i" (v)); \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010062}
63
64/* Define read function for system register */
65#define DEFINE_SYSREG_READ_FUNC(_name) \
66 _DEFINE_SYSREG_READ_FUNC(_name, _name)
67
68/* Define read & write function for system register */
69#define DEFINE_SYSREG_RW_FUNCS(_name) \
70 _DEFINE_SYSREG_READ_FUNC(_name, _name) \
71 _DEFINE_SYSREG_WRITE_FUNC(_name, _name)
72
73/* Define read & write function for renamed system register */
74#define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \
75 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
76 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
77
Achin Gupta92712a52015-09-03 14:18:02 +010078/* Define read function for renamed system register */
79#define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \
80 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name)
81
82/* Define write function for renamed system register */
83#define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \
84 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name)
85
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010086/* Define write function for special system registers */
87#define DEFINE_SYSREG_WRITE_CONST_FUNC(_name) \
88 _DEFINE_SYSREG_WRITE_CONST_FUNC(_name, _name)
89
90
91/**********************************************************************
92 * Macros to create inline functions for system instructions
93 *********************************************************************/
94
95/* Define function for simple system instruction */
96#define DEFINE_SYSOP_FUNC(_op) \
Juan Castillo2d552402014-06-13 17:05:10 +010097static inline void _op(void) \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010098{ \
99 __asm__ (#_op); \
100}
101
102/* Define function for system instruction with type specifier */
103#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
Juan Castillo2d552402014-06-13 17:05:10 +0100104static inline void _op ## _type(void) \
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100105{ \
106 __asm__ (#_op " " #_type); \
107}
108
109/* Define function for system instruction with register parameter */
110#define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \
111static inline void _op ## _type(uint64_t v) \
112{ \
113 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \
114}
Achin Gupta4f6ad662013-10-25 09:08:21 +0100115
116/*******************************************************************************
117 * TLB maintenance accessor prototypes
118 ******************************************************************************/
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000119
120#if ERRATA_A57_813419
121/*
122 * Define function for TLBI instruction with type specifier that implements
123 * the workaround for errata 813419 of Cortex-A57.
124 */
125#define DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(_type)\
126static inline void tlbi ## _type(void) \
127{ \
128 __asm__("tlbi " #_type "\n" \
129 "dsb ish\n" \
130 "tlbi " #_type); \
131}
132
133/*
134 * Define function for TLBI instruction with register parameter that implements
135 * the workaround for errata 813419 of Cortex-A57.
136 */
137#define DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(_type) \
138static inline void tlbi ## _type(uint64_t v) \
139{ \
140 __asm__("tlbi " #_type ", %0\n" \
141 "dsb ish\n" \
142 "tlbi " #_type ", %0" : : "r" (v)); \
143}
144#endif /* ERRATA_A57_813419 */
145
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100146DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1)
147DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is)
148DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2)
149DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is)
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000150#if ERRATA_A57_813419
151DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3)
152DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3is)
153#else
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100154DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3)
155DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is)
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000156#endif
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100157DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100158
Antonio Nino Diazac998032017-02-27 17:23:54 +0000159DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is)
160DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is)
161DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is)
162DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is)
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000163#if ERRATA_A57_813419
164DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vae3is)
165DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vale3is)
166#else
Antonio Nino Diazac998032017-02-27 17:23:54 +0000167DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is)
168DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is)
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000169#endif
Antonio Nino Diazac998032017-02-27 17:23:54 +0000170
Achin Gupta4f6ad662013-10-25 09:08:21 +0100171/*******************************************************************************
172 * Cache maintenance accessor prototypes
173 ******************************************************************************/
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100174DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw)
175DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw)
176DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw)
177DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac)
178DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac)
179DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac)
180DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau)
181DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva)
182
Varun Wadekar97625e32015-03-13 14:59:03 +0530183/*******************************************************************************
184 * Address translation accessor prototypes
185 ******************************************************************************/
186DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r)
187DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w)
188DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r)
189DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w)
190
Antonio Nino Diaze40306b2017-01-13 15:03:07 +0000191void flush_dcache_range(uintptr_t addr, size_t size);
192void clean_dcache_range(uintptr_t addr, size_t size);
193void inv_dcache_range(uintptr_t addr, size_t size);
194
195void dcsw_op_louis(u_register_t op_type);
196void dcsw_op_all(u_register_t op_type);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100197
Dan Handleya17fefa2014-05-14 12:38:32 +0100198void disable_mmu_el3(void);
199void disable_mmu_icache_el3(void);
Andrew Thoelke438c63a2014-04-28 12:06:18 +0100200
Achin Gupta4f6ad662013-10-25 09:08:21 +0100201/*******************************************************************************
202 * Misc. accessor prototypes
203 ******************************************************************************/
Achin Gupta4f6ad662013-10-25 09:08:21 +0100204
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100205DEFINE_SYSREG_WRITE_CONST_FUNC(daifset)
206DEFINE_SYSREG_WRITE_CONST_FUNC(daifclr)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100207
Varun Wadekar97625e32015-03-13 14:59:03 +0530208DEFINE_SYSREG_READ_FUNC(par_el1)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100209DEFINE_SYSREG_READ_FUNC(id_pfr1_el1)
210DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1)
211DEFINE_SYSREG_READ_FUNC(CurrentEl)
212DEFINE_SYSREG_RW_FUNCS(daif)
213DEFINE_SYSREG_RW_FUNCS(spsr_el1)
214DEFINE_SYSREG_RW_FUNCS(spsr_el2)
215DEFINE_SYSREG_RW_FUNCS(spsr_el3)
216DEFINE_SYSREG_RW_FUNCS(elr_el1)
217DEFINE_SYSREG_RW_FUNCS(elr_el2)
218DEFINE_SYSREG_RW_FUNCS(elr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100219
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100220DEFINE_SYSOP_FUNC(wfi)
221DEFINE_SYSOP_FUNC(wfe)
222DEFINE_SYSOP_FUNC(sev)
223DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
Soby Mathewed995662014-12-30 16:11:42 +0000224DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
Juan Castillo2e86cb12016-01-13 15:01:09 +0000225DEFINE_SYSOP_TYPE_FUNC(dmb, st)
226DEFINE_SYSOP_TYPE_FUNC(dmb, ld)
Soby Mathewed995662014-12-30 16:11:42 +0000227DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000228DEFINE_SYSOP_TYPE_FUNC(dsb, ishst)
Soby Mathewed995662014-12-30 16:11:42 +0000229DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100230DEFINE_SYSOP_FUNC(isb)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100231
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100232uint32_t get_afflvl_shift(uint32_t);
233uint32_t mpidr_mask_lower_afflvls(uint64_t, uint32_t);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100234
Achin Gupta4f6ad662013-10-25 09:08:21 +0100235
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100236void __dead2 eret(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
237 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
238void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3,
239 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100240
241/*******************************************************************************
242 * System register accessor prototypes
243 ******************************************************************************/
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100244DEFINE_SYSREG_READ_FUNC(midr_el1)
245DEFINE_SYSREG_READ_FUNC(mpidr_el1)
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000246DEFINE_SYSREG_READ_FUNC(id_aa64mmfr0_el1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100247
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100248DEFINE_SYSREG_RW_FUNCS(scr_el3)
249DEFINE_SYSREG_RW_FUNCS(hcr_el2)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100250
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100251DEFINE_SYSREG_RW_FUNCS(vbar_el1)
252DEFINE_SYSREG_RW_FUNCS(vbar_el2)
253DEFINE_SYSREG_RW_FUNCS(vbar_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100254
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100255DEFINE_SYSREG_RW_FUNCS(sctlr_el1)
256DEFINE_SYSREG_RW_FUNCS(sctlr_el2)
257DEFINE_SYSREG_RW_FUNCS(sctlr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100258
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100259DEFINE_SYSREG_RW_FUNCS(actlr_el1)
260DEFINE_SYSREG_RW_FUNCS(actlr_el2)
261DEFINE_SYSREG_RW_FUNCS(actlr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100262
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100263DEFINE_SYSREG_RW_FUNCS(esr_el1)
264DEFINE_SYSREG_RW_FUNCS(esr_el2)
265DEFINE_SYSREG_RW_FUNCS(esr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100266
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100267DEFINE_SYSREG_RW_FUNCS(afsr0_el1)
268DEFINE_SYSREG_RW_FUNCS(afsr0_el2)
269DEFINE_SYSREG_RW_FUNCS(afsr0_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100270
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100271DEFINE_SYSREG_RW_FUNCS(afsr1_el1)
272DEFINE_SYSREG_RW_FUNCS(afsr1_el2)
273DEFINE_SYSREG_RW_FUNCS(afsr1_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100274
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100275DEFINE_SYSREG_RW_FUNCS(far_el1)
276DEFINE_SYSREG_RW_FUNCS(far_el2)
277DEFINE_SYSREG_RW_FUNCS(far_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100278
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100279DEFINE_SYSREG_RW_FUNCS(mair_el1)
280DEFINE_SYSREG_RW_FUNCS(mair_el2)
281DEFINE_SYSREG_RW_FUNCS(mair_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100282
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100283DEFINE_SYSREG_RW_FUNCS(amair_el1)
284DEFINE_SYSREG_RW_FUNCS(amair_el2)
285DEFINE_SYSREG_RW_FUNCS(amair_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100286
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100287DEFINE_SYSREG_READ_FUNC(rvbar_el1)
288DEFINE_SYSREG_READ_FUNC(rvbar_el2)
289DEFINE_SYSREG_READ_FUNC(rvbar_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100290
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100291DEFINE_SYSREG_RW_FUNCS(rmr_el1)
292DEFINE_SYSREG_RW_FUNCS(rmr_el2)
293DEFINE_SYSREG_RW_FUNCS(rmr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100294
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100295DEFINE_SYSREG_RW_FUNCS(tcr_el1)
296DEFINE_SYSREG_RW_FUNCS(tcr_el2)
297DEFINE_SYSREG_RW_FUNCS(tcr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100298
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100299DEFINE_SYSREG_RW_FUNCS(ttbr0_el1)
300DEFINE_SYSREG_RW_FUNCS(ttbr0_el2)
301DEFINE_SYSREG_RW_FUNCS(ttbr0_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100302
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100303DEFINE_SYSREG_RW_FUNCS(ttbr1_el1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100304
Sandrine Bailleux8b0eafe2015-11-25 17:00:44 +0000305DEFINE_SYSREG_RW_FUNCS(vttbr_el2)
306
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100307DEFINE_SYSREG_RW_FUNCS(cptr_el2)
308DEFINE_SYSREG_RW_FUNCS(cptr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100309
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100310DEFINE_SYSREG_RW_FUNCS(cpacr_el1)
311DEFINE_SYSREG_RW_FUNCS(cntfrq_el0)
312DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1)
313DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1)
314DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1)
315DEFINE_SYSREG_READ_FUNC(cntpct_el0)
316DEFINE_SYSREG_RW_FUNCS(cnthctl_el2)
Soby Mathew5e5c2072014-04-07 15:28:55 +0100317
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100318DEFINE_SYSREG_RW_FUNCS(tpidr_el3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100319
Soby Mathewfeddfcf2014-08-29 14:41:58 +0100320DEFINE_SYSREG_RW_FUNCS(cntvoff_el2)
321
Andrew Thoelke4e126072014-06-04 21:10:52 +0100322DEFINE_SYSREG_RW_FUNCS(vpidr_el2)
323DEFINE_SYSREG_RW_FUNCS(vmpidr_el2)
developer550bf5e2016-07-11 16:05:23 +0800324DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0)
Andrew Thoelke4e126072014-06-04 21:10:52 +0100325
Soby Mathew26fb90e2015-01-06 21:36:55 +0000326DEFINE_SYSREG_READ_FUNC(isr_el1)
327
Dan Handley0cdebbd2015-03-30 17:15:16 +0100328DEFINE_SYSREG_READ_FUNC(ctr_el0)
329
David Cunado5f55e282016-10-31 17:37:34 +0000330DEFINE_SYSREG_RW_FUNCS(mdcr_el2)
David Cunadoc14b08e2016-11-25 00:21:59 +0000331DEFINE_SYSREG_RW_FUNCS(hstr_el2)
332DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2)
David Cunado5f55e282016-10-31 17:37:34 +0000333DEFINE_SYSREG_READ_FUNC(pmcr_el0)
334
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100335DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
336DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2)
337DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3)
338DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1)
Achin Gupta92712a52015-09-03 14:18:02 +0100339DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3)
340DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1)
341DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1)
342DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1)
343DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1)
344DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1)
345DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1)
346DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100347
Achin Gupta4f6ad662013-10-25 09:08:21 +0100348
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100349#define IS_IN_EL(x) \
350 (GET_EL(read_CurrentEl()) == MODE_EL##x)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100351
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100352#define IS_IN_EL1() IS_IN_EL(1)
353#define IS_IN_EL3() IS_IN_EL(3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100354
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100355/* Previously defined accesor functions with incomplete register names */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100356
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100357#define read_current_el() read_CurrentEl()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100358
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100359#define dsb() dsbsy()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100360
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100361#define read_midr() read_midr_el1()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100362
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100363#define read_mpidr() read_mpidr_el1()
Achin Gupta4f6ad662013-10-25 09:08:21 +0100364
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100365#define read_scr() read_scr_el3()
366#define write_scr(_v) write_scr_el3(_v)
Soby Mathew5e5c2072014-04-07 15:28:55 +0100367
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100368#define read_hcr() read_hcr_el2()
369#define write_hcr(_v) write_hcr_el2(_v)
Sandrine Bailleux25232af2014-05-09 11:23:11 +0100370
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100371#define read_cpacr() read_cpacr_el1()
372#define write_cpacr(_v) write_cpacr_el1(_v)
Soby Mathew5e5c2072014-04-07 15:28:55 +0100373
Achin Gupta4f6ad662013-10-25 09:08:21 +0100374#endif /* __ARCH_HELPERS_H__ */