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Paul Beesleyfc9ee362019-03-07 15:47:15 +00001Firmware Design
2===============
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
Dan Handley610e7e12018-03-01 18:44:00 +00004Trusted Firmware-A (TF-A) implements a subset of the Trusted Board Boot
Paul Beesleyf8640672019-04-12 14:19:42 +01005Requirements (TBBR) Platform Design Document (PDD) for Arm reference
6platforms.
7
8The TBB sequence starts when the platform is powered on and runs up
Douglas Raillardd7c21b72017-06-28 15:23:03 +01009to the stage where it hands-off control to firmware running in the normal
10world in DRAM. This is the cold boot path.
11
Paul Beesleyf8640672019-04-12 14:19:42 +010012TF-A also implements the `Power State Coordination Interface PDD`_ as a
Dan Handley610e7e12018-03-01 18:44:00 +000013runtime service. PSCI is the interface from normal world software to firmware
14implementing power management use-cases (for example, secondary CPU boot,
15hotplug and idle). Normal world software can access TF-A runtime services via
16the Arm SMC (Secure Monitor Call) instruction. The SMC instruction must be
Paul Beesleyf8640672019-04-12 14:19:42 +010017used as mandated by the SMC Calling Convention (`SMCCC`_).
Douglas Raillardd7c21b72017-06-28 15:23:03 +010018
Dan Handley610e7e12018-03-01 18:44:00 +000019TF-A implements a framework for configuring and managing interrupts generated
20in either security state. The details of the interrupt management framework
Paul Beesleyf8640672019-04-12 14:19:42 +010021and its design can be found in :ref:`Interrupt Management Framework`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010022
Dan Handley610e7e12018-03-01 18:44:00 +000023TF-A also implements a library for setting up and managing the translation
Paul Beesleyf8640672019-04-12 14:19:42 +010024tables. The details of this library can be found in
25:ref:`Translation (XLAT) Tables Library`.
Antonio Nino Diazb5d68092017-05-23 11:49:22 +010026
Dan Handley610e7e12018-03-01 18:44:00 +000027TF-A can be built to support either AArch64 or AArch32 execution state.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010028
29Cold boot
30---------
31
32The cold boot path starts when the platform is physically turned on. If
33``COLD_BOOT_SINGLE_CPU=0``, one of the CPUs released from reset is chosen as the
34primary CPU, and the remaining CPUs are considered secondary CPUs. The primary
35CPU is chosen through platform-specific means. The cold boot path is mainly
36executed by the primary CPU, other than essential CPU initialization executed by
37all CPUs. The secondary CPUs are kept in a safe platform-specific state until
38the primary CPU has performed enough initialization to boot them.
39
Paul Beesleyf8640672019-04-12 14:19:42 +010040Refer to the :ref:`CPU Reset` for more information on the effect of the
Douglas Raillardd7c21b72017-06-28 15:23:03 +010041``COLD_BOOT_SINGLE_CPU`` platform build option.
42
Dan Handley610e7e12018-03-01 18:44:00 +000043The cold boot path in this implementation of TF-A depends on the execution
44state. For AArch64, it is divided into five steps (in order of execution):
Douglas Raillardd7c21b72017-06-28 15:23:03 +010045
46- Boot Loader stage 1 (BL1) *AP Trusted ROM*
47- Boot Loader stage 2 (BL2) *Trusted Boot Firmware*
48- Boot Loader stage 3-1 (BL31) *EL3 Runtime Software*
49- Boot Loader stage 3-2 (BL32) *Secure-EL1 Payload* (optional)
50- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware*
51
52For AArch32, it is divided into four steps (in order of execution):
53
54- Boot Loader stage 1 (BL1) *AP Trusted ROM*
55- Boot Loader stage 2 (BL2) *Trusted Boot Firmware*
56- Boot Loader stage 3-2 (BL32) *EL3 Runtime Software*
57- Boot Loader stage 3-3 (BL33) *Non-trusted Firmware*
58
Dan Handley610e7e12018-03-01 18:44:00 +000059Arm development platforms (Fixed Virtual Platforms (FVPs) and Juno) implement a
Douglas Raillardd7c21b72017-06-28 15:23:03 +010060combination of the following types of memory regions. Each bootloader stage uses
61one or more of these memory regions.
62
63- Regions accessible from both non-secure and secure states. For example,
64 non-trusted SRAM, ROM and DRAM.
65- Regions accessible from only the secure state. For example, trusted SRAM and
66 ROM. The FVPs also implement the trusted DRAM which is statically
67 configured. Additionally, the Base FVPs and Juno development platform
68 configure the TrustZone Controller (TZC) to create a region in the DRAM
69 which is accessible only from the secure state.
70
71The sections below provide the following details:
72
Soby Mathewb1bf0442018-02-16 14:52:52 +000073- dynamic configuration of Boot Loader stages
Douglas Raillardd7c21b72017-06-28 15:23:03 +010074- initialization and execution of the first three stages during cold boot
75- specification of the EL3 Runtime Software (BL31 for AArch64 and BL32 for
76 AArch32) entrypoint requirements for use by alternative Trusted Boot
77 Firmware in place of the provided BL1 and BL2
78
Soby Mathewb1bf0442018-02-16 14:52:52 +000079Dynamic Configuration during cold boot
80~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
81
82Each of the Boot Loader stages may be dynamically configured if required by the
83platform. The Boot Loader stage may optionally specify a firmware
84configuration file and/or hardware configuration file as listed below:
85
Manish V Badarkheece96fd2020-06-13 09:42:28 +010086- FW_CONFIG - The firmware configuration file. Holds properties shared across
87 all BLx images.
88 An example is the "dtb-registry" node, which contains the information about
89 the other device tree configurations (load-address, size, image_id).
Soby Mathewb1bf0442018-02-16 14:52:52 +000090- HW_CONFIG - The hardware configuration file. Can be shared by all Boot Loader
91 stages and also by the Normal World Rich OS.
92- TB_FW_CONFIG - Trusted Boot Firmware configuration file. Shared between BL1
93 and BL2.
94- SOC_FW_CONFIG - SoC Firmware configuration file. Used by BL31.
95- TOS_FW_CONFIG - Trusted OS Firmware configuration file. Used by Trusted OS
96 (BL32).
97- NT_FW_CONFIG - Non Trusted Firmware configuration file. Used by Non-trusted
98 firmware (BL33).
99
100The Arm development platforms use the Flattened Device Tree format for the
101dynamic configuration files.
102
103Each Boot Loader stage can pass up to 4 arguments via registers to the next
104stage. BL2 passes the list of the next images to execute to the *EL3 Runtime
105Software* (BL31 for AArch64 and BL32 for AArch32) via `arg0`. All the other
106arguments are platform defined. The Arm development platforms use the following
107convention:
108
109- BL1 passes the address of a meminfo_t structure to BL2 via ``arg1``. This
110 structure contains the memory layout available to BL2.
111- When dynamic configuration files are present, the firmware configuration for
112 the next Boot Loader stage is populated in the first available argument and
113 the generic hardware configuration is passed the next available argument.
114 For example,
115
Manish V Badarkheece96fd2020-06-13 09:42:28 +0100116 - FW_CONFIG is loaded by BL1, then its address is passed in ``arg0`` to BL2.
117 - TB_FW_CONFIG address is retrieved by BL2 from FW_CONFIG device tree.
Soby Mathewb1bf0442018-02-16 14:52:52 +0000118 - If HW_CONFIG is loaded by BL1, then its address is passed in ``arg2`` to
119 BL2. Note, ``arg1`` is already used for meminfo_t.
120 - If SOC_FW_CONFIG is loaded by BL2, then its address is passed in ``arg1``
121 to BL31. Note, ``arg0`` is used to pass the list of executable images.
122 - Similarly, if HW_CONFIG is loaded by BL1 or BL2, then its address is
123 passed in ``arg2`` to BL31.
124 - For other BL3x images, if the firmware configuration file is loaded by
125 BL2, then its address is passed in ``arg0`` and if HW_CONFIG is loaded
126 then its address is passed in ``arg1``.
127
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100128BL1
129~~~
130
131This stage begins execution from the platform's reset vector at EL3. The reset
132address is platform dependent but it is usually located in a Trusted ROM area.
133The BL1 data section is copied to trusted SRAM at runtime.
134
Dan Handley610e7e12018-03-01 18:44:00 +0000135On the Arm development platforms, BL1 code starts execution from the reset
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100136vector defined by the constant ``BL1_RO_BASE``. The BL1 data section is copied
137to the top of trusted SRAM as defined by the constant ``BL1_RW_BASE``.
138
139The functionality implemented by this stage is as follows.
140
141Determination of boot path
142^^^^^^^^^^^^^^^^^^^^^^^^^^
143
144Whenever a CPU is released from reset, BL1 needs to distinguish between a warm
145boot and a cold boot. This is done using platform-specific mechanisms (see the
Paul Beesleyf8640672019-04-12 14:19:42 +0100146``plat_get_my_entrypoint()`` function in the :ref:`Porting Guide`). In the case
147of a warm boot, a CPU is expected to continue execution from a separate
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100148entrypoint. In the case of a cold boot, the secondary CPUs are placed in a safe
149platform-specific state (see the ``plat_secondary_cold_boot_setup()`` function in
Paul Beesleyf8640672019-04-12 14:19:42 +0100150the :ref:`Porting Guide`) while the primary CPU executes the remaining cold boot
151path as described in the following sections.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100152
153This step only applies when ``PROGRAMMABLE_RESET_ADDRESS=0``. Refer to the
Paul Beesleyf8640672019-04-12 14:19:42 +0100154:ref:`CPU Reset` for more information on the effect of the
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100155``PROGRAMMABLE_RESET_ADDRESS`` platform build option.
156
157Architectural initialization
158^^^^^^^^^^^^^^^^^^^^^^^^^^^^
159
160BL1 performs minimal architectural initialization as follows.
161
162- Exception vectors
163
164 BL1 sets up simple exception vectors for both synchronous and asynchronous
165 exceptions. The default behavior upon receiving an exception is to populate
166 a status code in the general purpose register ``X0/R0`` and call the
Paul Beesleyf8640672019-04-12 14:19:42 +0100167 ``plat_report_exception()`` function (see the :ref:`Porting Guide`). The
168 status code is one of:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100169
170 For AArch64:
171
172 ::
173
174 0x0 : Synchronous exception from Current EL with SP_EL0
175 0x1 : IRQ exception from Current EL with SP_EL0
176 0x2 : FIQ exception from Current EL with SP_EL0
177 0x3 : System Error exception from Current EL with SP_EL0
178 0x4 : Synchronous exception from Current EL with SP_ELx
179 0x5 : IRQ exception from Current EL with SP_ELx
180 0x6 : FIQ exception from Current EL with SP_ELx
181 0x7 : System Error exception from Current EL with SP_ELx
182 0x8 : Synchronous exception from Lower EL using aarch64
183 0x9 : IRQ exception from Lower EL using aarch64
184 0xa : FIQ exception from Lower EL using aarch64
185 0xb : System Error exception from Lower EL using aarch64
186 0xc : Synchronous exception from Lower EL using aarch32
187 0xd : IRQ exception from Lower EL using aarch32
188 0xe : FIQ exception from Lower EL using aarch32
189 0xf : System Error exception from Lower EL using aarch32
190
191 For AArch32:
192
193 ::
194
195 0x10 : User mode
196 0x11 : FIQ mode
197 0x12 : IRQ mode
198 0x13 : SVC mode
199 0x16 : Monitor mode
200 0x17 : Abort mode
201 0x1a : Hypervisor mode
202 0x1b : Undefined mode
203 0x1f : System mode
204
Dan Handley610e7e12018-03-01 18:44:00 +0000205 The ``plat_report_exception()`` implementation on the Arm FVP port programs
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100206 the Versatile Express System LED register in the following format to
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000207 indicate the occurrence of an unexpected exception:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100208
209 ::
210
211 SYS_LED[0] - Security state (Secure=0/Non-Secure=1)
212 SYS_LED[2:1] - Exception Level (EL3=0x3, EL2=0x2, EL1=0x1, EL0=0x0)
213 For AArch32 it is always 0x0
214 SYS_LED[7:3] - Exception Class (Sync/Async & origin). This is the value
215 of the status code
216
217 A write to the LED register reflects in the System LEDs (S6LED0..7) in the
218 CLCD window of the FVP.
219
220 BL1 does not expect to receive any exceptions other than the SMC exception.
221 For the latter, BL1 installs a simple stub. The stub expects to receive a
222 limited set of SMC types (determined by their function IDs in the general
223 purpose register ``X0/R0``):
224
225 - ``BL1_SMC_RUN_IMAGE``: This SMC is raised by BL2 to make BL1 pass control
226 to EL3 Runtime Software.
Paul Beesleyf8640672019-04-12 14:19:42 +0100227 - All SMCs listed in section "BL1 SMC Interface" in the :ref:`Firmware Update (FWU)`
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100228 Design Guide are supported for AArch64 only. These SMCs are currently
229 not supported when BL1 is built for AArch32.
230
231 Any other SMC leads to an assertion failure.
232
233- CPU initialization
234
235 BL1 calls the ``reset_handler()`` function which in turn calls the CPU
236 specific reset handler function (see the section: "CPU specific operations
237 framework").
238
239- Control register setup (for AArch64)
240
241 - ``SCTLR_EL3``. Instruction cache is enabled by setting the ``SCTLR_EL3.I``
242 bit. Alignment and stack alignment checking is enabled by setting the
243 ``SCTLR_EL3.A`` and ``SCTLR_EL3.SA`` bits. Exception endianness is set to
244 little-endian by clearing the ``SCTLR_EL3.EE`` bit.
245
246 - ``SCR_EL3``. The register width of the next lower exception level is set
247 to AArch64 by setting the ``SCR.RW`` bit. The ``SCR.EA`` bit is set to trap
248 both External Aborts and SError Interrupts in EL3. The ``SCR.SIF`` bit is
249 also set to disable instruction fetches from Non-secure memory when in
250 secure state.
251
252 - ``CPTR_EL3``. Accesses to the ``CPACR_EL1`` register from EL1 or EL2, or the
253 ``CPTR_EL2`` register from EL2 are configured to not trap to EL3 by
254 clearing the ``CPTR_EL3.TCPAC`` bit. Access to the trace functionality is
255 configured not to trap to EL3 by clearing the ``CPTR_EL3.TTA`` bit.
256 Instructions that access the registers associated with Floating Point
257 and Advanced SIMD execution are configured to not trap to EL3 by
258 clearing the ``CPTR_EL3.TFP`` bit.
259
260 - ``DAIF``. The SError interrupt is enabled by clearing the SError interrupt
261 mask bit.
262
263 - ``MDCR_EL3``. The trap controls, ``MDCR_EL3.TDOSA``, ``MDCR_EL3.TDA`` and
264 ``MDCR_EL3.TPM``, are set so that accesses to the registers they control
265 do not trap to EL3. AArch64 Secure self-hosted debug is disabled by
266 setting the ``MDCR_EL3.SDD`` bit. Also ``MDCR_EL3.SPD32`` is set to
267 disable AArch32 Secure self-hosted privileged debug from S-EL1.
268
269- Control register setup (for AArch32)
270
271 - ``SCTLR``. Instruction cache is enabled by setting the ``SCTLR.I`` bit.
272 Alignment checking is enabled by setting the ``SCTLR.A`` bit.
273 Exception endianness is set to little-endian by clearing the
274 ``SCTLR.EE`` bit.
275
276 - ``SCR``. The ``SCR.SIF`` bit is set to disable instruction fetches from
277 Non-secure memory when in secure state.
278
279 - ``CPACR``. Allow execution of Advanced SIMD instructions at PL0 and PL1,
280 by clearing the ``CPACR.ASEDIS`` bit. Access to the trace functionality
281 is configured not to trap to undefined mode by clearing the
282 ``CPACR.TRCDIS`` bit.
283
284 - ``NSACR``. Enable non-secure access to Advanced SIMD functionality and
285 system register access to implemented trace registers.
286
287 - ``FPEXC``. Enable access to the Advanced SIMD and floating-point
288 functionality from all Exception levels.
289
290 - ``CPSR.A``. The Asynchronous data abort interrupt is enabled by clearing
291 the Asynchronous data abort interrupt mask bit.
292
293 - ``SDCR``. The ``SDCR.SPD`` field is set to disable AArch32 Secure
294 self-hosted privileged debug.
295
296Platform initialization
297^^^^^^^^^^^^^^^^^^^^^^^
298
Dan Handley610e7e12018-03-01 18:44:00 +0000299On Arm platforms, BL1 performs the following platform initializations:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100300
301- Enable the Trusted Watchdog.
302- Initialize the console.
303- Configure the Interconnect to enable hardware coherency.
304- Enable the MMU and map the memory it needs to access.
305- Configure any required platform storage to load the next bootloader image
306 (BL2).
Soby Mathewb1bf0442018-02-16 14:52:52 +0000307- If the BL1 dynamic configuration file, ``TB_FW_CONFIG``, is available, then
308 load it to the platform defined address and make it available to BL2 via
309 ``arg0``.
Soby Mathewd969a7e2018-06-11 16:40:36 +0100310- Configure the system timer and program the `CNTFRQ_EL0` for use by NS-BL1U
311 and NS-BL2U firmware update images.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100312
313Firmware Update detection and execution
314^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
315
316After performing platform setup, BL1 common code calls
Paul Beesleyf8640672019-04-12 14:19:42 +0100317``bl1_plat_get_next_image_id()`` to determine if :ref:`Firmware Update (FWU)` is
318required or to proceed with the normal boot process. If the platform code
319returns ``BL2_IMAGE_ID`` then the normal boot sequence is executed as described
320in the next section, else BL1 assumes that :ref:`Firmware Update (FWU)` is
321required and execution passes to the first image in the
322:ref:`Firmware Update (FWU)` process. In either case, BL1 retrieves a descriptor
323of the next image by calling ``bl1_plat_get_image_desc()``. The image descriptor
324contains an ``entry_point_info_t`` structure, which BL1 uses to initialize the
325execution state of the next image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100326
327BL2 image load and execution
328^^^^^^^^^^^^^^^^^^^^^^^^^^^^
329
330In the normal boot flow, BL1 execution continues as follows:
331
332#. BL1 prints the following string from the primary CPU to indicate successful
333 execution of the BL1 stage:
334
335 ::
336
337 "Booting Trusted Firmware"
338
Soby Mathewb1bf0442018-02-16 14:52:52 +0000339#. BL1 loads a BL2 raw binary image from platform storage, at a
340 platform-specific base address. Prior to the load, BL1 invokes
341 ``bl1_plat_handle_pre_image_load()`` which allows the platform to update or
342 use the image information. If the BL2 image file is not present or if
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100343 there is not enough free trusted SRAM the following error message is
344 printed:
345
346 ::
347
348 "Failed to load BL2 firmware."
349
Soby Mathewb1bf0442018-02-16 14:52:52 +0000350#. BL1 invokes ``bl1_plat_handle_post_image_load()`` which again is intended
351 for platforms to take further action after image load. This function must
352 populate the necessary arguments for BL2, which may also include the memory
353 layout. Further description of the memory layout can be found later
354 in this document.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100355
356#. BL1 passes control to the BL2 image at Secure EL1 (for AArch64) or at
357 Secure SVC mode (for AArch32), starting from its load address.
358
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100359BL2
360~~~
361
362BL1 loads and passes control to BL2 at Secure-EL1 (for AArch64) or at Secure
363SVC mode (for AArch32) . BL2 is linked against and loaded at a platform-specific
364base address (more information can be found later in this document).
365The functionality implemented by BL2 is as follows.
366
367Architectural initialization
368^^^^^^^^^^^^^^^^^^^^^^^^^^^^
369
370For AArch64, BL2 performs the minimal architectural initialization required
Dan Handley610e7e12018-03-01 18:44:00 +0000371for subsequent stages of TF-A and normal world software. EL1 and EL0 are given
372access to Floating Point and Advanced SIMD registers by clearing the
373``CPACR.FPEN`` bits.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100374
375For AArch32, the minimal architectural initialization required for subsequent
Dan Handley610e7e12018-03-01 18:44:00 +0000376stages of TF-A and normal world software is taken care of in BL1 as both BL1
377and BL2 execute at PL1.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100378
379Platform initialization
380^^^^^^^^^^^^^^^^^^^^^^^
381
Dan Handley610e7e12018-03-01 18:44:00 +0000382On Arm platforms, BL2 performs the following platform initializations:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100383
384- Initialize the console.
385- Configure any required platform storage to allow loading further bootloader
386 images.
387- Enable the MMU and map the memory it needs to access.
388- Perform platform security setup to allow access to controlled components.
389- Reserve some memory for passing information to the next bootloader image
390 EL3 Runtime Software and populate it.
391- Define the extents of memory available for loading each subsequent
392 bootloader image.
Soby Mathewb1bf0442018-02-16 14:52:52 +0000393- If BL1 has passed TB_FW_CONFIG dynamic configuration file in ``arg0``,
394 then parse it.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100395
396Image loading in BL2
397^^^^^^^^^^^^^^^^^^^^
398
Roberto Vargas025946a2018-09-24 17:20:48 +0100399BL2 generic code loads the images based on the list of loadable images
400provided by the platform. BL2 passes the list of executable images
401provided by the platform to the next handover BL image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100402
Soby Mathewb1bf0442018-02-16 14:52:52 +0000403The list of loadable images provided by the platform may also contain
404dynamic configuration files. The files are loaded and can be parsed as
405needed in the ``bl2_plat_handle_post_image_load()`` function. These
406configuration files can be passed to next Boot Loader stages as arguments
407by updating the corresponding entrypoint information in this function.
408
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100409SCP_BL2 (System Control Processor Firmware) image load
410^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100411
412Some systems have a separate System Control Processor (SCP) for power, clock,
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100413reset and system control. BL2 loads the optional SCP_BL2 image from platform
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100414storage into a platform-specific region of secure memory. The subsequent
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100415handling of SCP_BL2 is platform specific. For example, on the Juno Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100416development platform port the image is transferred into SCP's internal memory
417using the Boot Over MHU (BOM) protocol after being loaded in the trusted SRAM
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100418memory. The SCP executes SCP_BL2 and signals to the Application Processor (AP)
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100419for BL2 execution to continue.
420
421EL3 Runtime Software image load
422^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
423
424BL2 loads the EL3 Runtime Software image from platform storage into a platform-
425specific address in trusted SRAM. If there is not enough memory to load the
Roberto Vargas025946a2018-09-24 17:20:48 +0100426image or image is missing it leads to an assertion failure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100427
428AArch64 BL32 (Secure-EL1 Payload) image load
429^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
430
431BL2 loads the optional BL32 image from platform storage into a platform-
432specific region of secure memory. The image executes in the secure world. BL2
433relies on BL31 to pass control to the BL32 image, if present. Hence, BL2
434populates a platform-specific area of memory with the entrypoint/load-address
435of the BL32 image. The value of the Saved Processor Status Register (``SPSR``)
436for entry into BL32 is not determined by BL2, it is initialized by the
437Secure-EL1 Payload Dispatcher (see later) within BL31, which is responsible for
438managing interaction with BL32. This information is passed to BL31.
439
440BL33 (Non-trusted Firmware) image load
441^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
442
443BL2 loads the BL33 image (e.g. UEFI or other test or boot software) from
444platform storage into non-secure memory as defined by the platform.
445
446BL2 relies on EL3 Runtime Software to pass control to BL33 once secure state
447initialization is complete. Hence, BL2 populates a platform-specific area of
448memory with the entrypoint and Saved Program Status Register (``SPSR``) of the
449normal world software image. The entrypoint is the load address of the BL33
450image. The ``SPSR`` is determined as specified in Section 5.13 of the
Paul Beesleyf8640672019-04-12 14:19:42 +0100451`Power State Coordination Interface PDD`_. This information is passed to the
452EL3 Runtime Software.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100453
454AArch64 BL31 (EL3 Runtime Software) execution
455^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
456
457BL2 execution continues as follows:
458
459#. BL2 passes control back to BL1 by raising an SMC, providing BL1 with the
460 BL31 entrypoint. The exception is handled by the SMC exception handler
461 installed by BL1.
462
463#. BL1 turns off the MMU and flushes the caches. It clears the
464 ``SCTLR_EL3.M/I/C`` bits, flushes the data cache to the point of coherency
465 and invalidates the TLBs.
466
467#. BL1 passes control to BL31 at the specified entrypoint at EL3.
468
Roberto Vargasb1584272017-11-20 13:36:10 +0000469Running BL2 at EL3 execution level
470~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
471
Dan Handley610e7e12018-03-01 18:44:00 +0000472Some platforms have a non-TF-A Boot ROM that expects the next boot stage
473to execute at EL3. On these platforms, TF-A BL1 is a waste of memory
474as its only purpose is to ensure TF-A BL2 is entered at S-EL1. To avoid
Roberto Vargasb1584272017-11-20 13:36:10 +0000475this waste, a special mode enables BL2 to execute at EL3, which allows
Dan Handley610e7e12018-03-01 18:44:00 +0000476a non-TF-A Boot ROM to load and jump directly to BL2. This mode is selected
Roberto Vargasb1584272017-11-20 13:36:10 +0000477when the build flag BL2_AT_EL3 is enabled. The main differences in this
478mode are:
479
480#. BL2 includes the reset code and the mailbox mechanism to differentiate
481 cold boot and warm boot. It runs at EL3 doing the arch
482 initialization required for EL3.
483
484#. BL2 does not receive the meminfo information from BL1 anymore. This
485 information can be passed by the Boot ROM or be internal to the
486 BL2 image.
487
488#. Since BL2 executes at EL3, BL2 jumps directly to the next image,
489 instead of invoking the RUN_IMAGE SMC call.
490
491
492We assume 3 different types of BootROM support on the platform:
493
494#. The Boot ROM always jumps to the same address, for both cold
495 and warm boot. In this case, we will need to keep a resident part
496 of BL2 whose memory cannot be reclaimed by any other image. The
497 linker script defines the symbols __TEXT_RESIDENT_START__ and
498 __TEXT_RESIDENT_END__ that allows the platform to configure
499 correctly the memory map.
500#. The platform has some mechanism to indicate the jump address to the
501 Boot ROM. Platform code can then program the jump address with
502 psci_warmboot_entrypoint during cold boot.
503#. The platform has some mechanism to program the reset address using
504 the PROGRAMMABLE_RESET_ADDRESS feature. Platform code can then
505 program the reset address with psci_warmboot_entrypoint during
506 cold boot, bypassing the boot ROM for warm boot.
507
508In the last 2 cases, no part of BL2 needs to remain resident at
509runtime. In the first 2 cases, we expect the Boot ROM to be able to
510differentiate between warm and cold boot, to avoid loading BL2 again
511during warm boot.
512
513This functionality can be tested with FVP loading the image directly
514in memory and changing the address where the system jumps at reset.
515For example:
516
Dimitris Papastamos25836492018-06-11 11:07:58 +0100517 -C cluster0.cpu0.RVBAR=0x4022000
518 --data cluster0.cpu0=bl2.bin@0x4022000
Roberto Vargasb1584272017-11-20 13:36:10 +0000519
520With this configuration, FVP is like a platform of the first case,
521where the Boot ROM jumps always to the same address. For simplification,
522BL32 is loaded in DRAM in this case, to avoid other images reclaiming
523BL2 memory.
524
525
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100526AArch64 BL31
527~~~~~~~~~~~~
528
529The image for this stage is loaded by BL2 and BL1 passes control to BL31 at
530EL3. BL31 executes solely in trusted SRAM. BL31 is linked against and
531loaded at a platform-specific base address (more information can be found later
532in this document). The functionality implemented by BL31 is as follows.
533
534Architectural initialization
535^^^^^^^^^^^^^^^^^^^^^^^^^^^^
536
537Currently, BL31 performs a similar architectural initialization to BL1 as
538far as system register settings are concerned. Since BL1 code resides in ROM,
539architectural initialization in BL31 allows override of any previous
540initialization done by BL1.
541
542BL31 initializes the per-CPU data framework, which provides a cache of
543frequently accessed per-CPU data optimised for fast, concurrent manipulation
544on different CPUs. This buffer includes pointers to per-CPU contexts, crash
545buffer, CPU reset and power down operations, PSCI data, platform data and so on.
546
547It then replaces the exception vectors populated by BL1 with its own. BL31
548exception vectors implement more elaborate support for handling SMCs since this
549is the only mechanism to access the runtime services implemented by BL31 (PSCI
550for example). BL31 checks each SMC for validity as specified by the
Sandrine Bailleuxd9202df2020-04-17 14:06:52 +0200551`SMC Calling Convention`_ before passing control to the required SMC
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100552handler routine.
553
554BL31 programs the ``CNTFRQ_EL0`` register with the clock frequency of the system
555counter, which is provided by the platform.
556
557Platform initialization
558^^^^^^^^^^^^^^^^^^^^^^^
559
560BL31 performs detailed platform initialization, which enables normal world
561software to function correctly.
562
Dan Handley610e7e12018-03-01 18:44:00 +0000563On Arm platforms, this consists of the following:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100564
565- Initialize the console.
566- Configure the Interconnect to enable hardware coherency.
567- Enable the MMU and map the memory it needs to access.
568- Initialize the generic interrupt controller.
569- Initialize the power controller device.
570- Detect the system topology.
571
572Runtime services initialization
573^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
574
575BL31 is responsible for initializing the runtime services. One of them is PSCI.
576
577As part of the PSCI initializations, BL31 detects the system topology. It also
578initializes the data structures that implement the state machine used to track
579the state of power domain nodes. The state can be one of ``OFF``, ``RUN`` or
580``RETENTION``. All secondary CPUs are initially in the ``OFF`` state. The cluster
581that the primary CPU belongs to is ``ON``; any other cluster is ``OFF``. It also
582initializes the locks that protect them. BL31 accesses the state of a CPU or
583cluster immediately after reset and before the data cache is enabled in the
584warm boot path. It is not currently possible to use 'exclusive' based spinlocks,
585therefore BL31 uses locks based on Lamport's Bakery algorithm instead.
586
587The runtime service framework and its initialization is described in more
588detail in the "EL3 runtime services framework" section below.
589
590Details about the status of the PSCI implementation are provided in the
591"Power State Coordination Interface" section below.
592
593AArch64 BL32 (Secure-EL1 Payload) image initialization
594^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
595
596If a BL32 image is present then there must be a matching Secure-EL1 Payload
597Dispatcher (SPD) service (see later for details). During initialization
598that service must register a function to carry out initialization of BL32
599once the runtime services are fully initialized. BL31 invokes such a
600registered function to initialize BL32 before running BL33. This initialization
601is not necessary for AArch32 SPs.
602
603Details on BL32 initialization and the SPD's role are described in the
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100604:ref:`firmware_design_sel1_spd` section below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100605
606BL33 (Non-trusted Firmware) execution
607^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
608
609EL3 Runtime Software initializes the EL2 or EL1 processor context for normal-
610world cold boot, ensuring that no secure state information finds its way into
611the non-secure execution state. EL3 Runtime Software uses the entrypoint
612information provided by BL2 to jump to the Non-trusted firmware image (BL33)
613at the highest available Exception Level (EL2 if available, otherwise EL1).
614
615Using alternative Trusted Boot Firmware in place of BL1 & BL2 (AArch64 only)
616~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
617
618Some platforms have existing implementations of Trusted Boot Firmware that
Dan Handley610e7e12018-03-01 18:44:00 +0000619would like to use TF-A BL31 for the EL3 Runtime Software. To enable this
620firmware architecture it is important to provide a fully documented and stable
621interface between the Trusted Boot Firmware and BL31.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100622
623Future changes to the BL31 interface will be done in a backwards compatible
624way, and this enables these firmware components to be independently enhanced/
625updated to develop and exploit new functionality.
626
627Required CPU state when calling ``bl31_entrypoint()`` during cold boot
628^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
629
630This function must only be called by the primary CPU.
631
632On entry to this function the calling primary CPU must be executing in AArch64
633EL3, little-endian data access, and all interrupt sources masked:
634
635::
636
637 PSTATE.EL = 3
638 PSTATE.RW = 1
639 PSTATE.DAIF = 0xf
640 SCTLR_EL3.EE = 0
641
642X0 and X1 can be used to pass information from the Trusted Boot Firmware to the
643platform code in BL31:
644
645::
646
Dan Handley610e7e12018-03-01 18:44:00 +0000647 X0 : Reserved for common TF-A information
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100648 X1 : Platform specific information
649
650BL31 zero-init sections (e.g. ``.bss``) should not contain valid data on entry,
651these will be zero filled prior to invoking platform setup code.
652
653Use of the X0 and X1 parameters
654'''''''''''''''''''''''''''''''
655
656The parameters are platform specific and passed from ``bl31_entrypoint()`` to
657``bl31_early_platform_setup()``. The value of these parameters is never directly
658used by the common BL31 code.
659
660The convention is that ``X0`` conveys information regarding the BL31, BL32 and
661BL33 images from the Trusted Boot firmware and ``X1`` can be used for other
Dan Handley610e7e12018-03-01 18:44:00 +0000662platform specific purpose. This convention allows platforms which use TF-A's
663BL1 and BL2 images to transfer additional platform specific information from
664Secure Boot without conflicting with future evolution of TF-A using ``X0`` to
665pass a ``bl31_params`` structure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100666
667BL31 common and SPD initialization code depends on image and entrypoint
668information about BL33 and BL32, which is provided via BL31 platform APIs.
669This information is required until the start of execution of BL33. This
670information can be provided in a platform defined manner, e.g. compiled into
671the platform code in BL31, or provided in a platform defined memory location
672by the Trusted Boot firmware, or passed from the Trusted Boot Firmware via the
673Cold boot Initialization parameters. This data may need to be cleaned out of
674the CPU caches if it is provided by an earlier boot stage and then accessed by
675BL31 platform code before the caches are enabled.
676
Dan Handley610e7e12018-03-01 18:44:00 +0000677TF-A's BL2 implementation passes a ``bl31_params`` structure in
678``X0`` and the Arm development platforms interpret this in the BL31 platform
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100679code.
680
681MMU, Data caches & Coherency
682''''''''''''''''''''''''''''
683
684BL31 does not depend on the enabled state of the MMU, data caches or
685interconnect coherency on entry to ``bl31_entrypoint()``. If these are disabled
686on entry, these should be enabled during ``bl31_plat_arch_setup()``.
687
688Data structures used in the BL31 cold boot interface
689''''''''''''''''''''''''''''''''''''''''''''''''''''
690
691These structures are designed to support compatibility and independent
692evolution of the structures and the firmware images. For example, a version of
693BL31 that can interpret the BL3x image information from different versions of
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100694BL2, a platform that uses an extended entry_point_info structure to convey
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100695additional register information to BL31, or a ELF image loader that can convey
696more details about the firmware images.
697
698To support these scenarios the structures are versioned and sized, which enables
699BL31 to detect which information is present and respond appropriately. The
700``param_header`` is defined to capture this information:
701
702.. code:: c
703
704 typedef struct param_header {
705 uint8_t type; /* type of the structure */
706 uint8_t version; /* version of this structure */
707 uint16_t size; /* size of this structure in bytes */
708 uint32_t attr; /* attributes: unused bits SBZ */
709 } param_header_t;
710
711The structures using this format are ``entry_point_info``, ``image_info`` and
712``bl31_params``. The code that allocates and populates these structures must set
713the header fields appropriately, and the ``SET_PARAM_HEAD()`` a macro is defined
714to simplify this action.
715
716Required CPU state for BL31 Warm boot initialization
717^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
718
Dan Handley610e7e12018-03-01 18:44:00 +0000719When requesting a CPU power-on, or suspending a running CPU, TF-A provides
720the platform power management code with a Warm boot initialization
721entry-point, to be invoked by the CPU immediately after the reset handler.
722On entry to the Warm boot initialization function the calling CPU must be in
723AArch64 EL3, little-endian data access and all interrupt sources masked:
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100724
725::
726
727 PSTATE.EL = 3
728 PSTATE.RW = 1
729 PSTATE.DAIF = 0xf
730 SCTLR_EL3.EE = 0
731
732The PSCI implementation will initialize the processor state and ensure that the
733platform power management code is then invoked as required to initialize all
734necessary system, cluster and CPU resources.
735
736AArch32 EL3 Runtime Software entrypoint interface
737~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
738
739To enable this firmware architecture it is important to provide a fully
740documented and stable interface between the Trusted Boot Firmware and the
741AArch32 EL3 Runtime Software.
742
743Future changes to the entrypoint interface will be done in a backwards
744compatible way, and this enables these firmware components to be independently
745enhanced/updated to develop and exploit new functionality.
746
747Required CPU state when entering during cold boot
748^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
749
750This function must only be called by the primary CPU.
751
752On entry to this function the calling primary CPU must be executing in AArch32
753EL3, little-endian data access, and all interrupt sources masked:
754
755::
756
757 PSTATE.AIF = 0x7
758 SCTLR.EE = 0
759
760R0 and R1 are used to pass information from the Trusted Boot Firmware to the
761platform code in AArch32 EL3 Runtime Software:
762
763::
764
Dan Handley610e7e12018-03-01 18:44:00 +0000765 R0 : Reserved for common TF-A information
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100766 R1 : Platform specific information
767
768Use of the R0 and R1 parameters
769'''''''''''''''''''''''''''''''
770
771The parameters are platform specific and the convention is that ``R0`` conveys
772information regarding the BL3x images from the Trusted Boot firmware and ``R1``
773can be used for other platform specific purpose. This convention allows
Dan Handley610e7e12018-03-01 18:44:00 +0000774platforms which use TF-A's BL1 and BL2 images to transfer additional platform
775specific information from Secure Boot without conflicting with future
776evolution of TF-A using ``R0`` to pass a ``bl_params`` structure.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100777
778The AArch32 EL3 Runtime Software is responsible for entry into BL33. This
779information can be obtained in a platform defined manner, e.g. compiled into
780the AArch32 EL3 Runtime Software, or provided in a platform defined memory
781location by the Trusted Boot firmware, or passed from the Trusted Boot Firmware
782via the Cold boot Initialization parameters. This data may need to be cleaned
783out of the CPU caches if it is provided by an earlier boot stage and then
784accessed by AArch32 EL3 Runtime Software before the caches are enabled.
785
Dan Handley610e7e12018-03-01 18:44:00 +0000786When using AArch32 EL3 Runtime Software, the Arm development platforms pass a
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100787``bl_params`` structure in ``R0`` from BL2 to be interpreted by AArch32 EL3 Runtime
788Software platform code.
789
790MMU, Data caches & Coherency
791''''''''''''''''''''''''''''
792
793AArch32 EL3 Runtime Software must not depend on the enabled state of the MMU,
794data caches or interconnect coherency in its entrypoint. They must be explicitly
795enabled if required.
796
797Data structures used in cold boot interface
798'''''''''''''''''''''''''''''''''''''''''''
799
800The AArch32 EL3 Runtime Software cold boot interface uses ``bl_params`` instead
801of ``bl31_params``. The ``bl_params`` structure is based on the convention
802described in AArch64 BL31 cold boot interface section.
803
804Required CPU state for warm boot initialization
805^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
806
807When requesting a CPU power-on, or suspending a running CPU, AArch32 EL3
808Runtime Software must ensure execution of a warm boot initialization entrypoint.
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100809If TF-A BL1 is used and the PROGRAMMABLE_RESET_ADDRESS build flag is false,
Dan Handley610e7e12018-03-01 18:44:00 +0000810then AArch32 EL3 Runtime Software must ensure that BL1 branches to the warm
811boot entrypoint by arranging for the BL1 platform function,
Sandrine Bailleux15530dd2019-02-08 15:26:36 +0100812plat_get_my_entrypoint(), to return a non-zero value.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100813
814In this case, the warm boot entrypoint must be in AArch32 EL3, little-endian
815data access and all interrupt sources masked:
816
817::
818
819 PSTATE.AIF = 0x7
820 SCTLR.EE = 0
821
Dan Handley610e7e12018-03-01 18:44:00 +0000822The warm boot entrypoint may be implemented by using TF-A
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100823``psci_warmboot_entrypoint()`` function. In that case, the platform must fulfil
Paul Beesleyf8640672019-04-12 14:19:42 +0100824the pre-requisites mentioned in the
825:ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100826
827EL3 runtime services framework
828------------------------------
829
830Software executing in the non-secure state and in the secure state at exception
831levels lower than EL3 will request runtime services using the Secure Monitor
832Call (SMC) instruction. These requests will follow the convention described in
833the SMC Calling Convention PDD (`SMCCC`_). The `SMCCC`_ assigns function
834identifiers to each SMC request and describes how arguments are passed and
835returned.
836
837The EL3 runtime services framework enables the development of services by
838different providers that can be easily integrated into final product firmware.
839The following sections describe the framework which facilitates the
840registration, initialization and use of runtime services in EL3 Runtime
841Software (BL31).
842
843The design of the runtime services depends heavily on the concepts and
844definitions described in the `SMCCC`_, in particular SMC Function IDs, Owning
845Entity Numbers (OEN), Fast and Yielding calls, and the SMC32 and SMC64 calling
846conventions. Please refer to that document for more detailed explanation of
847these terms.
848
849The following runtime services are expected to be implemented first. They have
850not all been instantiated in the current implementation.
851
852#. Standard service calls
853
854 This service is for management of the entire system. The Power State
855 Coordination Interface (`PSCI`_) is the first set of standard service calls
Dan Handley610e7e12018-03-01 18:44:00 +0000856 defined by Arm (see PSCI section later).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100857
858#. Secure-EL1 Payload Dispatcher service
859
860 If a system runs a Trusted OS or other Secure-EL1 Payload (SP) then
861 it also requires a *Secure Monitor* at EL3 to switch the EL1 processor
862 context between the normal world (EL1/EL2) and trusted world (Secure-EL1).
863 The Secure Monitor will make these world switches in response to SMCs. The
864 `SMCCC`_ provides for such SMCs with the Trusted OS Call and Trusted
865 Application Call OEN ranges.
866
867 The interface between the EL3 Runtime Software and the Secure-EL1 Payload is
868 not defined by the `SMCCC`_ or any other standard. As a result, each
869 Secure-EL1 Payload requires a specific Secure Monitor that runs as a runtime
Dan Handley610e7e12018-03-01 18:44:00 +0000870 service - within TF-A this service is referred to as the Secure-EL1 Payload
871 Dispatcher (SPD).
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100872
Dan Handley610e7e12018-03-01 18:44:00 +0000873 TF-A provides a Test Secure-EL1 Payload (TSP) and its associated Dispatcher
874 (TSPD). Details of SPD design and TSP/TSPD operation are described in the
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +0100875 :ref:`firmware_design_sel1_spd` section below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100876
877#. CPU implementation service
878
879 This service will provide an interface to CPU implementation specific
880 services for a given platform e.g. access to processor errata workarounds.
881 This service is currently unimplemented.
882
Dan Handley610e7e12018-03-01 18:44:00 +0000883Additional services for Arm Architecture, SiP and OEM calls can be implemented.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100884Each implemented service handles a range of SMC function identifiers as
885described in the `SMCCC`_.
886
887Registration
888~~~~~~~~~~~~
889
890A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying
891the name of the service, the range of OENs covered, the type of service and
892initialization and call handler functions. This macro instantiates a ``const struct rt_svc_desc`` for the service with these details (see ``runtime_svc.h``).
893This structure is allocated in a special ELF section ``rt_svc_descs``, enabling
894the framework to find all service descriptors included into BL31.
895
896The specific service for a SMC Function is selected based on the OEN and call
897type of the Function ID, and the framework uses that information in the service
898descriptor to identify the handler for the SMC Call.
899
900The service descriptors do not include information to identify the precise set
901of SMC function identifiers supported by this service implementation, the
902security state from which such calls are valid nor the capability to support
90364-bit and/or 32-bit callers (using SMC32 or SMC64). Responding appropriately
904to these aspects of a SMC call is the responsibility of the service
905implementation, the framework is focused on integration of services from
906different providers and minimizing the time taken by the framework before the
907service handler is invoked.
908
909Details of the parameters, requirements and behavior of the initialization and
910call handling functions are provided in the following sections.
911
912Initialization
913~~~~~~~~~~~~~~
914
915``runtime_svc_init()`` in ``runtime_svc.c`` initializes the runtime services
916framework running on the primary CPU during cold boot as part of the BL31
917initialization. This happens prior to initializing a Trusted OS and running
918Normal world boot firmware that might in turn use these services.
919Initialization involves validating each of the declared runtime service
920descriptors, calling the service initialization function and populating the
921index used for runtime lookup of the service.
922
923The BL31 linker script collects all of the declared service descriptors into a
924single array and defines symbols that allow the framework to locate and traverse
925the array, and determine its size.
926
927The framework does basic validation of each descriptor to halt firmware
928initialization if service declaration errors are detected. The framework does
929not check descriptors for the following error conditions, and may behave in an
930unpredictable manner under such scenarios:
931
932#. Overlapping OEN ranges
933#. Multiple descriptors for the same range of OENs and ``call_type``
934#. Incorrect range of owning entity numbers for a given ``call_type``
935
936Once validated, the service ``init()`` callback is invoked. This function carries
937out any essential EL3 initialization before servicing requests. The ``init()``
938function is only invoked on the primary CPU during cold boot. If the service
939uses per-CPU data this must either be initialized for all CPUs during this call,
940or be done lazily when a CPU first issues an SMC call to that service. If
941``init()`` returns anything other than ``0``, this is treated as an initialization
942error and the service is ignored: this does not cause the firmware to halt.
943
944The OEN and call type fields present in the SMC Function ID cover a total of
945128 distinct services, but in practice a single descriptor can cover a range of
946OENs, e.g. SMCs to call a Trusted OS function. To optimize the lookup of a
947service handler, the framework uses an array of 128 indices that map every
948distinct OEN/call-type combination either to one of the declared services or to
949indicate the service is not handled. This ``rt_svc_descs_indices[]`` array is
950populated for all of the OENs covered by a service after the service ``init()``
951function has reported success. So a service that fails to initialize will never
952have it's ``handle()`` function invoked.
953
954The following figure shows how the ``rt_svc_descs_indices[]`` index maps the SMC
955Function ID call type and OEN onto a specific service handler in the
956``rt_svc_descs[]`` array.
957
958|Image 1|
959
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -0500960.. _handling-an-smc:
961
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100962Handling an SMC
963~~~~~~~~~~~~~~~
964
965When the EL3 runtime services framework receives a Secure Monitor Call, the SMC
966Function ID is passed in W0 from the lower exception level (as per the
967`SMCCC`_). If the calling register width is AArch32, it is invalid to invoke an
968SMC Function which indicates the SMC64 calling convention: such calls are
969ignored and return the Unknown SMC Function Identifier result code ``0xFFFFFFFF``
970in R0/X0.
971
972Bit[31] (fast/yielding call) and bits[29:24] (owning entity number) of the SMC
973Function ID are combined to index into the ``rt_svc_descs_indices[]`` array. The
974resulting value might indicate a service that has no handler, in this case the
975framework will also report an Unknown SMC Function ID. Otherwise, the value is
976used as a further index into the ``rt_svc_descs[]`` array to locate the required
977service and handler.
978
979The service's ``handle()`` callback is provided with five of the SMC parameters
980directly, the others are saved into memory for retrieval (if needed) by the
981handler. The handler is also provided with an opaque ``handle`` for use with the
982supporting library for parameter retrieval, setting return values and context
983manipulation; and with ``flags`` indicating the security state of the caller. The
984framework finally sets up the execution stack for the handler, and invokes the
985services ``handle()`` function.
986
Madhukar Pappireddy20be0772019-11-09 23:28:08 -0600987On return from the handler the result registers are populated in X0-X7 as needed
988before restoring the stack and CPU state and returning from the original SMC.
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100989
Jeenu Viswambharancbb40d52017-10-18 14:30:53 +0100990Exception Handling Framework
991----------------------------
992
johpow017402f072020-07-28 13:07:25 -0500993Please refer to the :ref:`Exception Handling Framework` document.
Jeenu Viswambharancbb40d52017-10-18 14:30:53 +0100994
Douglas Raillardd7c21b72017-06-28 15:23:03 +0100995Power State Coordination Interface
996----------------------------------
997
998TODO: Provide design walkthrough of PSCI implementation.
999
Roberto Vargasd963e3e2017-09-12 10:28:35 +01001000The PSCI v1.1 specification categorizes APIs as optional and mandatory. All the
1001mandatory APIs in PSCI v1.1, PSCI v1.0 and in PSCI v0.2 draft specification
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001002`Power State Coordination Interface PDD`_ are implemented. The table lists
Roberto Vargasd963e3e2017-09-12 10:28:35 +01001003the PSCI v1.1 APIs and their support in generic code.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001004
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001005An API implementation might have a dependency on platform code e.g. CPU_SUSPEND
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001006requires the platform to export a part of the implementation. Hence the level
1007of support of the mandatory APIs depends upon the support exported by the
1008platform port as well. The Juno and FVP (all variants) platforms export all the
1009required support.
1010
1011+-----------------------------+-------------+-------------------------------+
Roberto Vargasd963e3e2017-09-12 10:28:35 +01001012| PSCI v1.1 API | Supported | Comments |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001013+=============================+=============+===============================+
Roberto Vargasd963e3e2017-09-12 10:28:35 +01001014| ``PSCI_VERSION`` | Yes | The version returned is 1.1 |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001015+-----------------------------+-------------+-------------------------------+
1016| ``CPU_SUSPEND`` | Yes\* | |
1017+-----------------------------+-------------+-------------------------------+
1018| ``CPU_OFF`` | Yes\* | |
1019+-----------------------------+-------------+-------------------------------+
1020| ``CPU_ON`` | Yes\* | |
1021+-----------------------------+-------------+-------------------------------+
1022| ``AFFINITY_INFO`` | Yes | |
1023+-----------------------------+-------------+-------------------------------+
1024| ``MIGRATE`` | Yes\*\* | |
1025+-----------------------------+-------------+-------------------------------+
1026| ``MIGRATE_INFO_TYPE`` | Yes\*\* | |
1027+-----------------------------+-------------+-------------------------------+
1028| ``MIGRATE_INFO_CPU`` | Yes\*\* | |
1029+-----------------------------+-------------+-------------------------------+
1030| ``SYSTEM_OFF`` | Yes\* | |
1031+-----------------------------+-------------+-------------------------------+
1032| ``SYSTEM_RESET`` | Yes\* | |
1033+-----------------------------+-------------+-------------------------------+
1034| ``PSCI_FEATURES`` | Yes | |
1035+-----------------------------+-------------+-------------------------------+
1036| ``CPU_FREEZE`` | No | |
1037+-----------------------------+-------------+-------------------------------+
1038| ``CPU_DEFAULT_SUSPEND`` | No | |
1039+-----------------------------+-------------+-------------------------------+
1040| ``NODE_HW_STATE`` | Yes\* | |
1041+-----------------------------+-------------+-------------------------------+
1042| ``SYSTEM_SUSPEND`` | Yes\* | |
1043+-----------------------------+-------------+-------------------------------+
1044| ``PSCI_SET_SUSPEND_MODE`` | No | |
1045+-----------------------------+-------------+-------------------------------+
1046| ``PSCI_STAT_RESIDENCY`` | Yes\* | |
1047+-----------------------------+-------------+-------------------------------+
1048| ``PSCI_STAT_COUNT`` | Yes\* | |
1049+-----------------------------+-------------+-------------------------------+
Roberto Vargasd963e3e2017-09-12 10:28:35 +01001050| ``SYSTEM_RESET2`` | Yes\* | |
1051+-----------------------------+-------------+-------------------------------+
1052| ``MEM_PROTECT`` | Yes\* | |
1053+-----------------------------+-------------+-------------------------------+
1054| ``MEM_PROTECT_CHECK_RANGE`` | Yes\* | |
1055+-----------------------------+-------------+-------------------------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001056
1057\*Note : These PSCI APIs require platform power management hooks to be
1058registered with the generic PSCI code to be supported.
1059
1060\*\*Note : These PSCI APIs require appropriate Secure Payload Dispatcher
1061hooks to be registered with the generic PSCI code to be supported.
1062
Dan Handley610e7e12018-03-01 18:44:00 +00001063The PSCI implementation in TF-A is a library which can be integrated with
1064AArch64 or AArch32 EL3 Runtime Software for Armv8-A systems. A guide to
1065integrating PSCI library with AArch32 EL3 Runtime Software can be found
Paul Beesleyf8640672019-04-12 14:19:42 +01001066at :ref:`PSCI Library Integration guide for Armv8-A AArch32 systems`.
1067
1068.. _firmware_design_sel1_spd:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001069
1070Secure-EL1 Payloads and Dispatchers
1071-----------------------------------
1072
1073On a production system that includes a Trusted OS running in Secure-EL1/EL0,
1074the Trusted OS is coupled with a companion runtime service in the BL31
1075firmware. This service is responsible for the initialisation of the Trusted
1076OS and all communications with it. The Trusted OS is the BL32 stage of the
Dan Handley610e7e12018-03-01 18:44:00 +00001077boot flow in TF-A. The firmware will attempt to locate, load and execute a
1078BL32 image.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001079
Dan Handley610e7e12018-03-01 18:44:00 +00001080TF-A uses a more general term for the BL32 software that runs at Secure-EL1 -
1081the *Secure-EL1 Payload* - as it is not always a Trusted OS.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001082
Dan Handley610e7e12018-03-01 18:44:00 +00001083TF-A provides a Test Secure-EL1 Payload (TSP) and a Test Secure-EL1 Payload
1084Dispatcher (TSPD) service as an example of how a Trusted OS is supported on a
1085production system using the Runtime Services Framework. On such a system, the
1086Test BL32 image and service are replaced by the Trusted OS and its dispatcher
1087service. The TF-A build system expects that the dispatcher will define the
1088build flag ``NEED_BL32`` to enable it to include the BL32 in the build either
1089as a binary or to compile from source depending on whether the ``BL32`` build
1090option is specified or not.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001091
1092The TSP runs in Secure-EL1. It is designed to demonstrate synchronous
1093communication with the normal-world software running in EL1/EL2. Communication
1094is initiated by the normal-world software
1095
1096- either directly through a Fast SMC (as defined in the `SMCCC`_)
1097
1098- or indirectly through a `PSCI`_ SMC. The `PSCI`_ implementation in turn
1099 informs the TSPD about the requested power management operation. This allows
1100 the TSP to prepare for or respond to the power state change
1101
1102The TSPD service is responsible for.
1103
1104- Initializing the TSP
1105
1106- Routing requests and responses between the secure and the non-secure
1107 states during the two types of communications just described
1108
1109Initializing a BL32 Image
1110~~~~~~~~~~~~~~~~~~~~~~~~~
1111
1112The Secure-EL1 Payload Dispatcher (SPD) service is responsible for initializing
1113the BL32 image. It needs access to the information passed by BL2 to BL31 to do
1114so. This is provided by:
1115
1116.. code:: c
1117
1118 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t);
1119
1120which returns a reference to the ``entry_point_info`` structure corresponding to
1121the image which will be run in the specified security state. The SPD uses this
1122API to get entry point information for the SECURE image, BL32.
1123
1124In the absence of a BL32 image, BL31 passes control to the normal world
1125bootloader image (BL33). When the BL32 image is present, it is typical
1126that the SPD wants control to be passed to BL32 first and then later to BL33.
1127
1128To do this the SPD has to register a BL32 initialization function during
1129initialization of the SPD service. The BL32 initialization function has this
1130prototype:
1131
1132.. code:: c
1133
1134 int32_t init(void);
1135
1136and is registered using the ``bl31_register_bl32_init()`` function.
1137
Dan Handley610e7e12018-03-01 18:44:00 +00001138TF-A supports two approaches for the SPD to pass control to BL32 before
1139returning through EL3 and running the non-trusted firmware (BL33):
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001140
1141#. In the BL32 setup function, use ``bl31_set_next_image_type()`` to
1142 request that the exit from ``bl31_main()`` is to the BL32 entrypoint in
1143 Secure-EL1. BL31 will exit to BL32 using the asynchronous method by
1144 calling ``bl31_prepare_next_image_entry()`` and ``el3_exit()``.
1145
1146 When the BL32 has completed initialization at Secure-EL1, it returns to
1147 BL31 by issuing an SMC, using a Function ID allocated to the SPD. On
1148 receipt of this SMC, the SPD service handler should switch the CPU context
1149 from trusted to normal world and use the ``bl31_set_next_image_type()`` and
1150 ``bl31_prepare_next_image_entry()`` functions to set up the initial return to
1151 the normal world firmware BL33. On return from the handler the framework
1152 will exit to EL2 and run BL33.
1153
1154#. The BL32 setup function registers an initialization function using
1155 ``bl31_register_bl32_init()`` which provides a SPD-defined mechanism to
1156 invoke a 'world-switch synchronous call' to Secure-EL1 to run the BL32
1157 entrypoint.
Paul Beesleyba3ed402019-03-13 16:20:44 +00001158
1159 .. note::
1160 The Test SPD service included with TF-A provides one implementation
1161 of such a mechanism.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001162
1163 On completion BL32 returns control to BL31 via a SMC, and on receipt the
1164 SPD service handler invokes the synchronous call return mechanism to return
1165 to the BL32 initialization function. On return from this function,
1166 ``bl31_main()`` will set up the return to the normal world firmware BL33 and
1167 continue the boot process in the normal world.
1168
Jeenu Viswambharanb60420a2017-08-24 15:43:44 +01001169Crash Reporting in BL31
1170-----------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001171
1172BL31 implements a scheme for reporting the processor state when an unhandled
1173exception is encountered. The reporting mechanism attempts to preserve all the
1174register contents and report it via a dedicated UART (PL011 console). BL31
1175reports the general purpose, EL3, Secure EL1 and some EL2 state registers.
1176
1177A dedicated per-CPU crash stack is maintained by BL31 and this is retrieved via
1178the per-CPU pointer cache. The implementation attempts to minimise the memory
1179required for this feature. The file ``crash_reporting.S`` contains the
1180implementation for crash reporting.
1181
1182The sample crash output is shown below.
1183
1184::
1185
Alexei Fedorov813c9f92020-03-03 13:31:58 +00001186 x0 = 0x000000002a4a0000
1187 x1 = 0x0000000000000001
1188 x2 = 0x0000000000000002
1189 x3 = 0x0000000000000003
1190 x4 = 0x0000000000000004
1191 x5 = 0x0000000000000005
1192 x6 = 0x0000000000000006
1193 x7 = 0x0000000000000007
1194 x8 = 0x0000000000000008
1195 x9 = 0x0000000000000009
1196 x10 = 0x0000000000000010
1197 x11 = 0x0000000000000011
1198 x12 = 0x0000000000000012
1199 x13 = 0x0000000000000013
1200 x14 = 0x0000000000000014
1201 x15 = 0x0000000000000015
1202 x16 = 0x0000000000000016
1203 x17 = 0x0000000000000017
1204 x18 = 0x0000000000000018
1205 x19 = 0x0000000000000019
1206 x20 = 0x0000000000000020
1207 x21 = 0x0000000000000021
1208 x22 = 0x0000000000000022
1209 x23 = 0x0000000000000023
1210 x24 = 0x0000000000000024
1211 x25 = 0x0000000000000025
1212 x26 = 0x0000000000000026
1213 x27 = 0x0000000000000027
1214 x28 = 0x0000000000000028
1215 x29 = 0x0000000000000029
1216 x30 = 0x0000000088000b78
1217 scr_el3 = 0x000000000003073d
1218 sctlr_el3 = 0x00000000b0cd183f
1219 cptr_el3 = 0x0000000000000000
1220 tcr_el3 = 0x000000008080351c
1221 daif = 0x00000000000002c0
1222 mair_el3 = 0x00000000004404ff
1223 spsr_el3 = 0x0000000060000349
1224 elr_el3 = 0x0000000088000114
1225 ttbr0_el3 = 0x0000000004018201
1226 esr_el3 = 0x00000000be000000
1227 far_el3 = 0x0000000000000000
1228 spsr_el1 = 0x0000000000000000
1229 elr_el1 = 0x0000000000000000
1230 spsr_abt = 0x0000000000000000
1231 spsr_und = 0x0000000000000000
1232 spsr_irq = 0x0000000000000000
1233 spsr_fiq = 0x0000000000000000
1234 sctlr_el1 = 0x0000000030d00800
1235 actlr_el1 = 0x0000000000000000
1236 cpacr_el1 = 0x0000000000000000
1237 csselr_el1 = 0x0000000000000000
1238 sp_el1 = 0x0000000000000000
1239 esr_el1 = 0x0000000000000000
1240 ttbr0_el1 = 0x0000000000000000
1241 ttbr1_el1 = 0x0000000000000000
1242 mair_el1 = 0x0000000000000000
1243 amair_el1 = 0x0000000000000000
1244 tcr_el1 = 0x0000000000000000
1245 tpidr_el1 = 0x0000000000000000
1246 tpidr_el0 = 0x0000000000000000
1247 tpidrro_el0 = 0x0000000000000000
1248 par_el1 = 0x0000000000000000
1249 mpidr_el1 = 0x0000000080000000
1250 afsr0_el1 = 0x0000000000000000
1251 afsr1_el1 = 0x0000000000000000
1252 contextidr_el1 = 0x0000000000000000
1253 vbar_el1 = 0x0000000000000000
1254 cntp_ctl_el0 = 0x0000000000000000
1255 cntp_cval_el0 = 0x0000000000000000
1256 cntv_ctl_el0 = 0x0000000000000000
1257 cntv_cval_el0 = 0x0000000000000000
1258 cntkctl_el1 = 0x0000000000000000
1259 sp_el0 = 0x0000000004014940
1260 isr_el1 = 0x0000000000000000
1261 dacr32_el2 = 0x0000000000000000
1262 ifsr32_el2 = 0x0000000000000000
1263 icc_hppir0_el1 = 0x00000000000003ff
1264 icc_hppir1_el1 = 0x00000000000003ff
1265 icc_ctlr_el3 = 0x0000000000080400
1266 gicd_ispendr regs (Offsets 0x200-0x278)
1267 Offset Value
1268 0x200: 0x0000000000000000
1269 0x208: 0x0000000000000000
1270 0x210: 0x0000000000000000
1271 0x218: 0x0000000000000000
1272 0x220: 0x0000000000000000
1273 0x228: 0x0000000000000000
1274 0x230: 0x0000000000000000
1275 0x238: 0x0000000000000000
1276 0x240: 0x0000000000000000
1277 0x248: 0x0000000000000000
1278 0x250: 0x0000000000000000
1279 0x258: 0x0000000000000000
1280 0x260: 0x0000000000000000
1281 0x268: 0x0000000000000000
1282 0x270: 0x0000000000000000
1283 0x278: 0x0000000000000000
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001284
1285Guidelines for Reset Handlers
1286-----------------------------
1287
Dan Handley610e7e12018-03-01 18:44:00 +00001288TF-A implements a framework that allows CPU and platform ports to perform
1289actions very early after a CPU is released from reset in both the cold and warm
1290boot paths. This is done by calling the ``reset_handler()`` function in both
1291the BL1 and BL31 images. It in turn calls the platform and CPU specific reset
1292handling functions.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001293
1294Details for implementing a CPU specific reset handler can be found in
1295Section 8. Details for implementing a platform specific reset handler can be
Paul Beesleyf8640672019-04-12 14:19:42 +01001296found in the :ref:`Porting Guide` (see the ``plat_reset_handler()`` function).
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001297
1298When adding functionality to a reset handler, keep in mind that if a different
1299reset handling behavior is required between the first and the subsequent
1300invocations of the reset handling code, this should be detected at runtime.
1301In other words, the reset handler should be able to detect whether an action has
1302already been performed and act as appropriate. Possible courses of actions are,
1303e.g. skip the action the second time, or undo/redo it.
1304
Madhukar Pappireddy86350ae2020-07-29 09:37:25 -05001305.. _configuring-secure-interrupts:
1306
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001307Configuring secure interrupts
1308-----------------------------
1309
1310The GIC driver is responsible for performing initial configuration of secure
1311interrupts on the platform. To this end, the platform is expected to provide the
1312GIC driver (either GICv2 or GICv3, as selected by the platform) with the
1313interrupt configuration during the driver initialisation.
1314
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001315Secure interrupt configuration are specified in an array of secure interrupt
1316properties. In this scheme, in both GICv2 and GICv3 driver data structures, the
1317``interrupt_props`` member points to an array of interrupt properties. Each
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +00001318element of the array specifies the interrupt number and its attributes
1319(priority, group, configuration). Each element of the array shall be populated
1320by the macro ``INTR_PROP_DESC()``. The macro takes the following arguments:
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001321
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001322- 10-bit interrupt number,
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001323
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001324- 8-bit interrupt priority,
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001325
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001326- Interrupt type (one of ``INTR_TYPE_EL3``, ``INTR_TYPE_S_EL1``,
1327 ``INTR_TYPE_NS``),
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001328
Antonio Nino Diaz29b9f5b2018-09-24 17:23:24 +01001329- Interrupt configuration (either ``GIC_INTR_CFG_LEVEL`` or
1330 ``GIC_INTR_CFG_EDGE``).
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +01001331
Paul Beesleyf8640672019-04-12 14:19:42 +01001332.. _firmware_design_cpu_ops_fwk:
1333
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001334CPU specific operations framework
1335---------------------------------
1336
Dan Handley610e7e12018-03-01 18:44:00 +00001337Certain aspects of the Armv8-A architecture are implementation defined,
1338that is, certain behaviours are not architecturally defined, but must be
1339defined and documented by individual processor implementations. TF-A
1340implements a framework which categorises the common implementation defined
1341behaviours and allows a processor to export its implementation of that
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001342behaviour. The categories are:
1343
1344#. Processor specific reset sequence.
1345
1346#. Processor specific power down sequences.
1347
1348#. Processor specific register dumping as a part of crash reporting.
1349
1350#. Errata status reporting.
1351
1352Each of the above categories fulfils a different requirement.
1353
1354#. allows any processor specific initialization before the caches and MMU
1355 are turned on, like implementation of errata workarounds, entry into
1356 the intra-cluster coherency domain etc.
1357
1358#. allows each processor to implement the power down sequence mandated in
1359 its Technical Reference Manual (TRM).
1360
1361#. allows a processor to provide additional information to the developer
1362 in the event of a crash, for example Cortex-A53 has registers which
1363 can expose the data cache contents.
1364
1365#. allows a processor to define a function that inspects and reports the status
1366 of all errata workarounds on that processor.
1367
1368Please note that only 2. is mandated by the TRM.
1369
1370The CPU specific operations framework scales to accommodate a large number of
1371different CPUs during power down and reset handling. The platform can specify
1372any CPU optimization it wants to enable for each CPU. It can also specify
1373the CPU errata workarounds to be applied for each CPU type during reset
1374handling by defining CPU errata compile time macros. Details on these macros
Paul Beesleyf8640672019-04-12 14:19:42 +01001375can be found in the :ref:`Arm CPU Specific Build Macros` document.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001376
1377The CPU specific operations framework depends on the ``cpu_ops`` structure which
1378needs to be exported for each type of CPU in the platform. It is defined in
1379``include/lib/cpus/aarch64/cpu_macros.S`` and has the following fields : ``midr``,
1380``reset_func()``, ``cpu_pwr_down_ops`` (array of power down functions) and
1381``cpu_reg_dump()``.
1382
1383The CPU specific files in ``lib/cpus`` export a ``cpu_ops`` data structure with
1384suitable handlers for that CPU. For example, ``lib/cpus/aarch64/cortex_a53.S``
1385exports the ``cpu_ops`` for Cortex-A53 CPU. According to the platform
1386configuration, these CPU specific files must be included in the build by
1387the platform makefile. The generic CPU specific operations framework code exists
1388in ``lib/cpus/aarch64/cpu_helpers.S``.
1389
1390CPU specific Reset Handling
1391~~~~~~~~~~~~~~~~~~~~~~~~~~~
1392
1393After a reset, the state of the CPU when it calls generic reset handler is:
1394MMU turned off, both instruction and data caches turned off and not part
1395of any coherency domain.
1396
1397The BL entrypoint code first invokes the ``plat_reset_handler()`` to allow
1398the platform to perform any system initialization required and any system
1399errata workarounds that needs to be applied. The ``get_cpu_ops_ptr()`` reads
1400the current CPU midr, finds the matching ``cpu_ops`` entry in the ``cpu_ops``
1401array and returns it. Note that only the part number and implementer fields
1402in midr are used to find the matching ``cpu_ops`` entry. The ``reset_func()`` in
1403the returned ``cpu_ops`` is then invoked which executes the required reset
1404handling for that CPU and also any errata workarounds enabled by the platform.
1405This function must preserve the values of general purpose registers x20 to x29.
1406
1407Refer to Section "Guidelines for Reset Handlers" for general guidelines
1408regarding placement of code in a reset handler.
1409
1410CPU specific power down sequence
1411~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1412
1413During the BL31 initialization sequence, the pointer to the matching ``cpu_ops``
1414entry is stored in per-CPU data by ``init_cpu_ops()`` so that it can be quickly
1415retrieved during power down sequences.
1416
1417Various CPU drivers register handlers to perform power down at certain power
1418levels for that specific CPU. The PSCI service, upon receiving a power down
1419request, determines the highest power level at which to execute power down
1420sequence for a particular CPU. It uses the ``prepare_cpu_pwr_dwn()`` function to
1421pick the right power down handler for the requested level. The function
1422retrieves ``cpu_ops`` pointer member of per-CPU data, and from that, further
1423retrieves ``cpu_pwr_down_ops`` array, and indexes into the required level. If the
1424requested power level is higher than what a CPU driver supports, the handler
1425registered for highest level is invoked.
1426
1427At runtime the platform hooks for power down are invoked by the PSCI service to
1428perform platform specific operations during a power down sequence, for example
1429turning off CCI coherency during a cluster power down.
1430
1431CPU specific register reporting during crash
1432~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1433
1434If the crash reporting is enabled in BL31, when a crash occurs, the crash
1435reporting framework calls ``do_cpu_reg_dump`` which retrieves the matching
1436``cpu_ops`` using ``get_cpu_ops_ptr()`` function. The ``cpu_reg_dump()`` in
1437``cpu_ops`` is invoked, which then returns the CPU specific register values to
1438be reported and a pointer to the ASCII list of register names in a format
1439expected by the crash reporting framework.
1440
Paul Beesleyf8640672019-04-12 14:19:42 +01001441.. _firmware_design_cpu_errata_reporting:
1442
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001443CPU errata status reporting
1444~~~~~~~~~~~~~~~~~~~~~~~~~~~
1445
Dan Handley610e7e12018-03-01 18:44:00 +00001446Errata workarounds for CPUs supported in TF-A are applied during both cold and
1447warm boots, shortly after reset. Individual Errata workarounds are enabled as
1448build options. Some errata workarounds have potential run-time implications;
1449therefore some are enabled by default, others not. Platform ports shall
1450override build options to enable or disable errata as appropriate. The CPU
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001451drivers take care of applying errata workarounds that are enabled and applicable
Paul Beesleyf8640672019-04-12 14:19:42 +01001452to a given CPU. Refer to :ref:`arm_cpu_macros_errata_workarounds` for more
1453information.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001454
1455Functions in CPU drivers that apply errata workaround must follow the
1456conventions listed below.
1457
1458The errata workaround must be authored as two separate functions:
1459
1460- One that checks for errata. This function must determine whether that errata
1461 applies to the current CPU. Typically this involves matching the current
1462 CPUs revision and variant against a value that's known to be affected by the
1463 errata. If the function determines that the errata applies to this CPU, it
1464 must return ``ERRATA_APPLIES``; otherwise, it must return
1465 ``ERRATA_NOT_APPLIES``. The utility functions ``cpu_get_rev_var`` and
1466 ``cpu_rev_var_ls`` functions may come in handy for this purpose.
1467
1468For an errata identified as ``E``, the check function must be named
1469``check_errata_E``.
1470
1471This function will be invoked at different times, both from assembly and from
1472C run time. Therefore it must follow AAPCS, and must not use stack.
1473
1474- Another one that applies the errata workaround. This function would call the
1475 check function described above, and applies errata workaround if required.
1476
1477CPU drivers that apply errata workaround can optionally implement an assembly
1478function that report the status of errata workarounds pertaining to that CPU.
Antonio Nino Diaz56b68ad2019-02-28 13:35:21 +00001479For a driver that registers the CPU, for example, ``cpux`` via ``declare_cpu_ops``
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001480macro, the errata reporting function, if it exists, must be named
1481``cpux_errata_report``. This function will always be called with MMU enabled; it
1482must follow AAPCS and may use stack.
1483
Dan Handley610e7e12018-03-01 18:44:00 +00001484In a debug build of TF-A, on a CPU that comes out of reset, both BL1 and the
1485runtime firmware (BL31 in AArch64, and BL32 in AArch32) will invoke errata
1486status reporting function, if one exists, for that type of CPU.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001487
1488To report the status of each errata workaround, the function shall use the
1489assembler macro ``report_errata``, passing it:
1490
1491- The build option that enables the errata;
1492
1493- The name of the CPU: this must be the same identifier that CPU driver
1494 registered itself with, using ``declare_cpu_ops``;
1495
1496- And the errata identifier: the identifier must match what's used in the
1497 errata's check function described above.
1498
1499The errata status reporting function will be called once per CPU type/errata
1500combination during the software's active life time.
1501
Dan Handley610e7e12018-03-01 18:44:00 +00001502It's expected that whenever an errata workaround is submitted to TF-A, the
1503errata reporting function is appropriately extended to report its status as
1504well.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001505
1506Reporting the status of errata workaround is for informational purpose only; it
1507has no functional significance.
1508
1509Memory layout of BL images
1510--------------------------
1511
1512Each bootloader image can be divided in 2 parts:
1513
1514- the static contents of the image. These are data actually stored in the
1515 binary on the disk. In the ELF terminology, they are called ``PROGBITS``
1516 sections;
1517
1518- the run-time contents of the image. These are data that don't occupy any
1519 space in the binary on the disk. The ELF binary just contains some
1520 metadata indicating where these data will be stored at run-time and the
1521 corresponding sections need to be allocated and initialized at run-time.
1522 In the ELF terminology, they are called ``NOBITS`` sections.
1523
1524All PROGBITS sections are grouped together at the beginning of the image,
Dan Handley610e7e12018-03-01 18:44:00 +00001525followed by all NOBITS sections. This is true for all TF-A images and it is
1526governed by the linker scripts. This ensures that the raw binary images are
1527as small as possible. If a NOBITS section was inserted in between PROGBITS
1528sections then the resulting binary file would contain zero bytes in place of
1529this NOBITS section, making the image unnecessarily bigger. Smaller images
1530allow faster loading from the FIP to the main memory.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001531
Samuel Holland31a14e12018-10-17 21:40:18 -05001532For BL31, a platform can specify an alternate location for NOBITS sections
1533(other than immediately following PROGBITS sections) by setting
1534``SEPARATE_NOBITS_REGION`` to 1 and defining ``BL31_NOBITS_BASE`` and
1535``BL31_NOBITS_LIMIT``.
1536
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001537Linker scripts and symbols
1538~~~~~~~~~~~~~~~~~~~~~~~~~~
1539
1540Each bootloader stage image layout is described by its own linker script. The
1541linker scripts export some symbols into the program symbol table. Their values
Dan Handley610e7e12018-03-01 18:44:00 +00001542correspond to particular addresses. TF-A code can refer to these symbols to
1543figure out the image memory layout.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001544
Dan Handley610e7e12018-03-01 18:44:00 +00001545Linker symbols follow the following naming convention in TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001546
1547- ``__<SECTION>_START__``
1548
1549 Start address of a given section named ``<SECTION>``.
1550
1551- ``__<SECTION>_END__``
1552
1553 End address of a given section named ``<SECTION>``. If there is an alignment
1554 constraint on the section's end address then ``__<SECTION>_END__`` corresponds
1555 to the end address of the section's actual contents, rounded up to the right
1556 boundary. Refer to the value of ``__<SECTION>_UNALIGNED_END__`` to know the
1557 actual end address of the section's contents.
1558
1559- ``__<SECTION>_UNALIGNED_END__``
1560
1561 End address of a given section named ``<SECTION>`` without any padding or
1562 rounding up due to some alignment constraint.
1563
1564- ``__<SECTION>_SIZE__``
1565
1566 Size (in bytes) of a given section named ``<SECTION>``. If there is an
1567 alignment constraint on the section's end address then ``__<SECTION>_SIZE__``
1568 corresponds to the size of the section's actual contents, rounded up to the
1569 right boundary. In other words, ``__<SECTION>_SIZE__ = __<SECTION>_END__ - _<SECTION>_START__``. Refer to the value of ``__<SECTION>_UNALIGNED_SIZE__``
1570 to know the actual size of the section's contents.
1571
1572- ``__<SECTION>_UNALIGNED_SIZE__``
1573
1574 Size (in bytes) of a given section named ``<SECTION>`` without any padding or
1575 rounding up due to some alignment constraint. In other words,
1576 ``__<SECTION>_UNALIGNED_SIZE__ = __<SECTION>_UNALIGNED_END__ - __<SECTION>_START__``.
1577
Dan Handley610e7e12018-03-01 18:44:00 +00001578Some of the linker symbols are mandatory as TF-A code relies on them to be
1579defined. They are listed in the following subsections. Some of them must be
1580provided for each bootloader stage and some are specific to a given bootloader
1581stage.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001582
1583The linker scripts define some extra, optional symbols. They are not actually
1584used by any code but they help in understanding the bootloader images' memory
1585layout as they are easy to spot in the link map files.
1586
1587Common linker symbols
1588^^^^^^^^^^^^^^^^^^^^^
1589
1590All BL images share the following requirements:
1591
1592- The BSS section must be zero-initialised before executing any C code.
1593- The coherent memory section (if enabled) must be zero-initialised as well.
1594- The MMU setup code needs to know the extents of the coherent and read-only
1595 memory regions to set the right memory attributes. When
1596 ``SEPARATE_CODE_AND_RODATA=1``, it needs to know more specifically how the
1597 read-only memory region is divided between code and data.
1598
1599The following linker symbols are defined for this purpose:
1600
1601- ``__BSS_START__``
1602- ``__BSS_SIZE__``
1603- ``__COHERENT_RAM_START__`` Must be aligned on a page-size boundary.
1604- ``__COHERENT_RAM_END__`` Must be aligned on a page-size boundary.
1605- ``__COHERENT_RAM_UNALIGNED_SIZE__``
1606- ``__RO_START__``
1607- ``__RO_END__``
1608- ``__TEXT_START__``
1609- ``__TEXT_END__``
1610- ``__RODATA_START__``
1611- ``__RODATA_END__``
1612
1613BL1's linker symbols
1614^^^^^^^^^^^^^^^^^^^^
1615
1616BL1 being the ROM image, it has additional requirements. BL1 resides in ROM and
1617it is entirely executed in place but it needs some read-write memory for its
1618mutable data. Its ``.data`` section (i.e. its allocated read-write data) must be
1619relocated from ROM to RAM before executing any C code.
1620
1621The following additional linker symbols are defined for BL1:
1622
1623- ``__BL1_ROM_END__`` End address of BL1's ROM contents, covering its code
1624 and ``.data`` section in ROM.
1625- ``__DATA_ROM_START__`` Start address of the ``.data`` section in ROM. Must be
1626 aligned on a 16-byte boundary.
1627- ``__DATA_RAM_START__`` Address in RAM where the ``.data`` section should be
1628 copied over. Must be aligned on a 16-byte boundary.
1629- ``__DATA_SIZE__`` Size of the ``.data`` section (in ROM or RAM).
1630- ``__BL1_RAM_START__`` Start address of BL1 read-write data.
1631- ``__BL1_RAM_END__`` End address of BL1 read-write data.
1632
1633How to choose the right base addresses for each bootloader stage image
1634~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1635
Dan Handley610e7e12018-03-01 18:44:00 +00001636There is currently no support for dynamic image loading in TF-A. This means
1637that all bootloader images need to be linked against their ultimate runtime
1638locations and the base addresses of each image must be chosen carefully such
1639that images don't overlap each other in an undesired way. As the code grows,
1640the base addresses might need adjustments to cope with the new memory layout.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001641
1642The memory layout is completely specific to the platform and so there is no
1643general recipe for choosing the right base addresses for each bootloader image.
1644However, there are tools to aid in understanding the memory layout. These are
1645the link map files: ``build/<platform>/<build-type>/bl<x>/bl<x>.map``, with ``<x>``
1646being the stage bootloader. They provide a detailed view of the memory usage of
1647each image. Among other useful information, they provide the end address of
1648each image.
1649
1650- ``bl1.map`` link map file provides ``__BL1_RAM_END__`` address.
1651- ``bl2.map`` link map file provides ``__BL2_END__`` address.
1652- ``bl31.map`` link map file provides ``__BL31_END__`` address.
1653- ``bl32.map`` link map file provides ``__BL32_END__`` address.
1654
1655For each bootloader image, the platform code must provide its start address
1656as well as a limit address that it must not overstep. The latter is used in the
1657linker scripts to check that the image doesn't grow past that address. If that
1658happens, the linker will issue a message similar to the following:
1659
1660::
1661
1662 aarch64-none-elf-ld: BLx has exceeded its limit.
1663
1664Additionally, if the platform memory layout implies some image overlaying like
1665on FVP, BL31 and TSP need to know the limit address that their PROGBITS
1666sections must not overstep. The platform code must provide those.
1667
Soby Mathew97b1bff2018-09-27 16:46:41 +01001668TF-A does not provide any mechanism to verify at boot time that the memory
1669to load a new image is free to prevent overwriting a previously loaded image.
1670The platform must specify the memory available in the system for all the
1671relevant BL images to be loaded.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001672
1673For example, in the case of BL1 loading BL2, ``bl1_plat_sec_mem_layout()`` will
1674return the region defined by the platform where BL1 intends to load BL2. The
1675``load_image()`` function performs bounds check for the image size based on the
1676base and maximum image size provided by the platforms. Platforms must take
1677this behaviour into account when defining the base/size for each of the images.
1678
Dan Handley610e7e12018-03-01 18:44:00 +00001679Memory layout on Arm development platforms
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001680^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1681
Dan Handley610e7e12018-03-01 18:44:00 +00001682The following list describes the memory layout on the Arm development platforms:
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001683
1684- A 4KB page of shared memory is used for communication between Trusted
1685 Firmware and the platform's power controller. This is located at the base of
1686 Trusted SRAM. The amount of Trusted SRAM available to load the bootloader
1687 images is reduced by the size of the shared memory.
1688
1689 The shared memory is used to store the CPUs' entrypoint mailbox. On Juno,
1690 this is also used for the MHU payload when passing messages to and from the
1691 SCP.
1692
Soby Mathew492e2452018-06-06 16:03:10 +01001693- Another 4 KB page is reserved for passing memory layout between BL1 and BL2
1694 and also the dynamic firmware configurations.
1695
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001696- On FVP, BL1 is originally sitting in the Trusted ROM at address ``0x0``. On
1697 Juno, BL1 resides in flash memory at address ``0x0BEC0000``. BL1 read-write
1698 data are relocated to the top of Trusted SRAM at runtime.
1699
Soby Mathew492e2452018-06-06 16:03:10 +01001700- BL2 is loaded below BL1 RW
1701
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001702- EL3 Runtime Software, BL31 for AArch64 and BL32 for AArch32 (e.g. SP_MIN),
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001703 is loaded at the top of the Trusted SRAM, such that its NOBITS sections will
Soby Mathew492e2452018-06-06 16:03:10 +01001704 overwrite BL1 R/W data and BL2. This implies that BL1 global variables
1705 remain valid only until execution reaches the EL3 Runtime Software entry
1706 point during a cold boot.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001707
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01001708- On Juno, SCP_BL2 is loaded temporarily into the EL3 Runtime Software memory
Paul Beesleyf2ec7142019-10-04 16:17:46 +00001709 region and transferred to the SCP before being overwritten by EL3 Runtime
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001710 Software.
1711
1712- BL32 (for AArch64) can be loaded in one of the following locations:
1713
1714 - Trusted SRAM
1715 - Trusted DRAM (FVP only)
1716 - Secure region of DRAM (top 16MB of DRAM configured by the TrustZone
1717 controller)
1718
Soby Mathew492e2452018-06-06 16:03:10 +01001719 When BL32 (for AArch64) is loaded into Trusted SRAM, it is loaded below
1720 BL31.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001721
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001722The location of the BL32 image will result in different memory maps. This is
1723illustrated for both FVP and Juno in the following diagrams, using the TSP as
1724an example.
1725
Paul Beesleyba3ed402019-03-13 16:20:44 +00001726.. note::
1727 Loading the BL32 image in TZC secured DRAM doesn't change the memory
1728 layout of the other images in Trusted SRAM.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001729
Sathees Balya90950092018-11-15 14:22:30 +00001730CONFIG section in memory layouts shown below contains:
1731
1732::
1733
1734 +--------------------+
1735 |bl2_mem_params_descs|
1736 |--------------------|
1737 | fw_configs |
1738 +--------------------+
1739
1740``bl2_mem_params_descs`` contains parameters passed from BL2 to next the
1741BL image during boot.
1742
Manish V Badarkheece96fd2020-06-13 09:42:28 +01001743``fw_configs`` includes soc_fw_config, tos_fw_config, tb_fw_config and fw_config.
Sathees Balya90950092018-11-15 14:22:30 +00001744
Soby Mathew492e2452018-06-06 16:03:10 +01001745**FVP with TSP in Trusted SRAM with firmware configs :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001746(These diagrams only cover the AArch64 case)
1747
1748::
1749
Soby Mathew492e2452018-06-06 16:03:10 +01001750 DRAM
1751 0xffffffff +----------+
1752 : :
1753 |----------|
1754 |HW_CONFIG |
1755 0x83000000 |----------| (non-secure)
1756 | |
1757 0x80000000 +----------+
1758
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001759 Trusted SRAM
Soby Mathew492e2452018-06-06 16:03:10 +01001760 0x04040000 +----------+ loaded by BL2 +----------------+
1761 | BL1 (rw) | <<<<<<<<<<<<< | |
1762 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1763 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001764 |----------| <<<<<<<<<<<<< |----------------|
1765 | | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew492e2452018-06-06 16:03:10 +01001766 | | <<<<<<<<<<<<< |----------------|
1767 | | <<<<<<<<<<<<< | BL32 |
Manish V Badarkheece96fd2020-06-13 09:42:28 +01001768 0x04003000 +----------+ +----------------+
Sathees Balya90950092018-11-15 14:22:30 +00001769 | CONFIG |
Soby Mathew492e2452018-06-06 16:03:10 +01001770 0x04001000 +----------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001771 | Shared |
1772 0x04000000 +----------+
1773
1774 Trusted ROM
1775 0x04000000 +----------+
1776 | BL1 (ro) |
1777 0x00000000 +----------+
1778
Soby Mathew492e2452018-06-06 16:03:10 +01001779**FVP with TSP in Trusted DRAM with firmware configs (default option):**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001780
1781::
1782
Soby Mathewb1bf0442018-02-16 14:52:52 +00001783 DRAM
1784 0xffffffff +--------------+
1785 : :
1786 |--------------|
1787 | HW_CONFIG |
1788 0x83000000 |--------------| (non-secure)
1789 | |
1790 0x80000000 +--------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001791
Soby Mathewb1bf0442018-02-16 14:52:52 +00001792 Trusted DRAM
1793 0x08000000 +--------------+
1794 | BL32 |
1795 0x06000000 +--------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001796
Soby Mathewb1bf0442018-02-16 14:52:52 +00001797 Trusted SRAM
Soby Mathew492e2452018-06-06 16:03:10 +01001798 0x04040000 +--------------+ loaded by BL2 +----------------+
1799 | BL1 (rw) | <<<<<<<<<<<<< | |
1800 |--------------| <<<<<<<<<<<<< | BL31 NOBITS |
1801 | BL2 | <<<<<<<<<<<<< | |
Soby Mathewb1bf0442018-02-16 14:52:52 +00001802 |--------------| <<<<<<<<<<<<< |----------------|
1803 | | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew492e2452018-06-06 16:03:10 +01001804 | | +----------------+
Manish V Badarkheece96fd2020-06-13 09:42:28 +01001805 0x04003000 +--------------+
Sathees Balya90950092018-11-15 14:22:30 +00001806 | CONFIG |
Soby Mathewb1bf0442018-02-16 14:52:52 +00001807 0x04001000 +--------------+
1808 | Shared |
1809 0x04000000 +--------------+
1810
1811 Trusted ROM
1812 0x04000000 +--------------+
1813 | BL1 (ro) |
1814 0x00000000 +--------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001815
Soby Mathew492e2452018-06-06 16:03:10 +01001816**FVP with TSP in TZC-Secured DRAM with firmware configs :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001817
1818::
1819
1820 DRAM
1821 0xffffffff +----------+
Soby Mathewb1bf0442018-02-16 14:52:52 +00001822 | BL32 | (secure)
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001823 0xff000000 +----------+
1824 | |
Soby Mathew492e2452018-06-06 16:03:10 +01001825 |----------|
1826 |HW_CONFIG |
1827 0x83000000 |----------| (non-secure)
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001828 | |
1829 0x80000000 +----------+
1830
1831 Trusted SRAM
Soby Mathew492e2452018-06-06 16:03:10 +01001832 0x04040000 +----------+ loaded by BL2 +----------------+
1833 | BL1 (rw) | <<<<<<<<<<<<< | |
1834 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1835 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001836 |----------| <<<<<<<<<<<<< |----------------|
1837 | | <<<<<<<<<<<<< | BL31 PROGBITS |
Soby Mathew492e2452018-06-06 16:03:10 +01001838 | | +----------------+
Manish V Badarkheece96fd2020-06-13 09:42:28 +01001839 0x04003000 +----------+
Sathees Balya90950092018-11-15 14:22:30 +00001840 | CONFIG |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001841 0x04001000 +----------+
1842 | Shared |
1843 0x04000000 +----------+
1844
1845 Trusted ROM
1846 0x04000000 +----------+
1847 | BL1 (ro) |
1848 0x00000000 +----------+
1849
Soby Mathew492e2452018-06-06 16:03:10 +01001850**Juno with BL32 in Trusted SRAM :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001851
1852::
1853
1854 Flash0
1855 0x0C000000 +----------+
1856 : :
1857 0x0BED0000 |----------|
1858 | BL1 (ro) |
1859 0x0BEC0000 |----------|
1860 : :
1861 0x08000000 +----------+ BL31 is loaded
1862 after SCP_BL2 has
1863 Trusted SRAM been sent to SCP
Soby Mathew492e2452018-06-06 16:03:10 +01001864 0x04040000 +----------+ loaded by BL2 +----------------+
1865 | BL1 (rw) | <<<<<<<<<<<<< | |
1866 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1867 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001868 |----------| <<<<<<<<<<<<< |----------------|
1869 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS |
Chris Kayf8fa4652020-03-12 13:50:26 +00001870 | | <<<<<<<<<<<<< |----------------|
Soby Mathew492e2452018-06-06 16:03:10 +01001871 | | <<<<<<<<<<<<< | BL32 |
1872 | | +----------------+
1873 | |
1874 0x04001000 +----------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001875 | MHU |
1876 0x04000000 +----------+
1877
Soby Mathew492e2452018-06-06 16:03:10 +01001878**Juno with BL32 in TZC-secured DRAM :**
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001879
1880::
1881
1882 DRAM
1883 0xFFE00000 +----------+
Soby Mathewb1bf0442018-02-16 14:52:52 +00001884 | BL32 | (secure)
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001885 0xFF000000 |----------|
1886 | |
1887 : : (non-secure)
1888 | |
1889 0x80000000 +----------+
1890
1891 Flash0
1892 0x0C000000 +----------+
1893 : :
1894 0x0BED0000 |----------|
1895 | BL1 (ro) |
1896 0x0BEC0000 |----------|
1897 : :
1898 0x08000000 +----------+ BL31 is loaded
1899 after SCP_BL2 has
1900 Trusted SRAM been sent to SCP
Soby Mathew492e2452018-06-06 16:03:10 +01001901 0x04040000 +----------+ loaded by BL2 +----------------+
1902 | BL1 (rw) | <<<<<<<<<<<<< | |
1903 |----------| <<<<<<<<<<<<< | BL31 NOBITS |
1904 | BL2 | <<<<<<<<<<<<< | |
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001905 |----------| <<<<<<<<<<<<< |----------------|
1906 | SCP_BL2 | <<<<<<<<<<<<< | BL31 PROGBITS |
Chris Kayf8fa4652020-03-12 13:50:26 +00001907 | | +----------------+
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001908 0x04001000 +----------+
1909 | MHU |
1910 0x04000000 +----------+
1911
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01001912.. _firmware_design_fip:
Sathees Balya17d8eed2019-01-30 15:56:44 +00001913
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001914Firmware Image Package (FIP)
1915----------------------------
1916
1917Using a Firmware Image Package (FIP) allows for packing bootloader images (and
Dan Handley610e7e12018-03-01 18:44:00 +00001918potentially other payloads) into a single archive that can be loaded by TF-A
1919from non-volatile platform storage. A driver to load images from a FIP has
1920been added to the storage layer and allows a package to be read from supported
1921platform storage. A tool to create Firmware Image Packages is also provided
1922and described below.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001923
1924Firmware Image Package layout
1925~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1926
1927The FIP layout consists of a table of contents (ToC) followed by payload data.
1928The ToC itself has a header followed by one or more table entries. The ToC is
Jett Zhou75566102017-11-24 16:03:58 +08001929terminated by an end marker entry, and since the size of the ToC is 0 bytes,
1930the offset equals the total size of the FIP file. All ToC entries describe some
1931payload data that has been appended to the end of the binary package. With the
1932information provided in the ToC entry the corresponding payload data can be
1933retrieved.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001934
1935::
1936
1937 ------------------
1938 | ToC Header |
1939 |----------------|
1940 | ToC Entry 0 |
1941 |----------------|
1942 | ToC Entry 1 |
1943 |----------------|
1944 | ToC End Marker |
1945 |----------------|
1946 | |
1947 | Data 0 |
1948 | |
1949 |----------------|
1950 | |
1951 | Data 1 |
1952 | |
1953 ------------------
1954
1955The ToC header and entry formats are described in the header file
1956``include/tools_share/firmware_image_package.h``. This file is used by both the
Dan Handley610e7e12018-03-01 18:44:00 +00001957tool and TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001958
1959The ToC header has the following fields:
1960
1961::
1962
1963 `name`: The name of the ToC. This is currently used to validate the header.
1964 `serial_number`: A non-zero number provided by the creation tool
1965 `flags`: Flags associated with this data.
1966 Bits 0-31: Reserved
1967 Bits 32-47: Platform defined
1968 Bits 48-63: Reserved
1969
1970A ToC entry has the following fields:
1971
1972::
1973
1974 `uuid`: All files are referred to by a pre-defined Universally Unique
1975 IDentifier [UUID] . The UUIDs are defined in
1976 `include/tools_share/firmware_image_package.h`. The platform translates
1977 the requested image name into the corresponding UUID when accessing the
1978 package.
1979 `offset_address`: The offset address at which the corresponding payload data
1980 can be found. The offset is calculated from the ToC base address.
1981 `size`: The size of the corresponding payload data in bytes.
Etienne Carriere7421bf12017-08-23 15:43:33 +02001982 `flags`: Flags associated with this entry. None are yet defined.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001983
1984Firmware Image Package creation tool
1985~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1986
Dan Handley610e7e12018-03-01 18:44:00 +00001987The FIP creation tool can be used to pack specified images into a binary
1988package that can be loaded by TF-A from platform storage. The tool currently
1989only supports packing bootloader images. Additional image definitions can be
1990added to the tool as required.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001991
1992The tool can be found in ``tools/fiptool``.
1993
1994Loading from a Firmware Image Package (FIP)
1995~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1996
1997The Firmware Image Package (FIP) driver can load images from a binary package on
Dan Handley610e7e12018-03-01 18:44:00 +00001998non-volatile platform storage. For the Arm development platforms, this is
Douglas Raillardd7c21b72017-06-28 15:23:03 +01001999currently NOR FLASH.
2000
2001Bootloader images are loaded according to the platform policy as specified by
Dan Handley610e7e12018-03-01 18:44:00 +00002002the function ``plat_get_image_source()``. For the Arm development platforms, this
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002003means the platform will attempt to load images from a Firmware Image Package
2004located at the start of NOR FLASH0.
2005
Dan Handley610e7e12018-03-01 18:44:00 +00002006The Arm development platforms' policy is to only allow loading of a known set of
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002007images. The platform policy can be modified to allow additional images.
2008
Dan Handley610e7e12018-03-01 18:44:00 +00002009Use of coherent memory in TF-A
2010------------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002011
2012There might be loss of coherency when physical memory with mismatched
2013shareability, cacheability and memory attributes is accessed by multiple CPUs
Dan Handley610e7e12018-03-01 18:44:00 +00002014(refer to section B2.9 of `Arm ARM`_ for more details). This possibility occurs
2015in TF-A during power up/down sequences when coherency, MMU and caches are
2016turned on/off incrementally.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002017
Dan Handley610e7e12018-03-01 18:44:00 +00002018TF-A defines coherent memory as a region of memory with Device nGnRE attributes
2019in the translation tables. The translation granule size in TF-A is 4KB. This
2020is the smallest possible size of the coherent memory region.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002021
2022By default, all data structures which are susceptible to accesses with
2023mismatched attributes from various CPUs are allocated in a coherent memory
Paul Beesleyf8640672019-04-12 14:19:42 +01002024region (refer to section 2.1 of :ref:`Porting Guide`). The coherent memory
2025region accesses are Outer Shareable, non-cacheable and they can be accessed with
2026the Device nGnRE attributes when the MMU is turned on. Hence, at the expense of
2027at least an extra page of memory, TF-A is able to work around coherency issues
2028due to mismatched memory attributes.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002029
2030The alternative to the above approach is to allocate the susceptible data
2031structures in Normal WriteBack WriteAllocate Inner shareable memory. This
2032approach requires the data structures to be designed so that it is possible to
2033work around the issue of mismatched memory attributes by performing software
2034cache maintenance on them.
2035
Dan Handley610e7e12018-03-01 18:44:00 +00002036Disabling the use of coherent memory in TF-A
2037~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002038
2039It might be desirable to avoid the cost of allocating coherent memory on
Dan Handley610e7e12018-03-01 18:44:00 +00002040platforms which are memory constrained. TF-A enables inclusion of coherent
2041memory in firmware images through the build flag ``USE_COHERENT_MEM``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002042This flag is enabled by default. It can be disabled to choose the second
2043approach described above.
2044
2045The below sections analyze the data structures allocated in the coherent memory
2046region and the changes required to allocate them in normal memory.
2047
2048Coherent memory usage in PSCI implementation
2049~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2050
2051The ``psci_non_cpu_pd_nodes`` data structure stores the platform's power domain
2052tree information for state management of power domains. By default, this data
Dan Handley610e7e12018-03-01 18:44:00 +00002053structure is allocated in the coherent memory region in TF-A because it can be
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002054accessed by multiple CPUs, either with caches enabled or disabled.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002055
2056.. code:: c
2057
2058 typedef struct non_cpu_pwr_domain_node {
2059 /*
2060 * Index of the first CPU power domain node level 0 which has this node
2061 * as its parent.
2062 */
2063 unsigned int cpu_start_idx;
2064
2065 /*
2066 * Number of CPU power domains which are siblings of the domain indexed
2067 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx
2068 * -> cpu_start_idx + ncpus' have this node as their parent.
2069 */
2070 unsigned int ncpus;
2071
2072 /*
2073 * Index of the parent power domain node.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002074 */
2075 unsigned int parent_node;
2076
2077 plat_local_state_t local_state;
2078
2079 unsigned char level;
2080
2081 /* For indexing the psci_lock array*/
2082 unsigned char lock_index;
2083 } non_cpu_pd_node_t;
2084
2085In order to move this data structure to normal memory, the use of each of its
2086fields must be analyzed. Fields like ``cpu_start_idx``, ``ncpus``, ``parent_node``
2087``level`` and ``lock_index`` are only written once during cold boot. Hence removing
2088them from coherent memory involves only doing a clean and invalidate of the
2089cache lines after these fields are written.
2090
2091The field ``local_state`` can be concurrently accessed by multiple CPUs in
2092different cache states. A Lamport's Bakery lock ``psci_locks`` is used to ensure
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002093mutual exclusion to this field and a clean and invalidate is needed after it
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002094is written.
2095
2096Bakery lock data
2097~~~~~~~~~~~~~~~~
2098
2099The bakery lock data structure ``bakery_lock_t`` is allocated in coherent memory
2100and is accessed by multiple CPUs with mismatched attributes. ``bakery_lock_t`` is
2101defined as follows:
2102
2103.. code:: c
2104
2105 typedef struct bakery_lock {
2106 /*
2107 * The lock_data is a bit-field of 2 members:
2108 * Bit[0] : choosing. This field is set when the CPU is
2109 * choosing its bakery number.
2110 * Bits[1 - 15] : number. This is the bakery number allocated.
2111 */
2112 volatile uint16_t lock_data[BAKERY_LOCK_MAX_CPUS];
2113 } bakery_lock_t;
2114
2115It is a characteristic of Lamport's Bakery algorithm that the volatile per-CPU
2116fields can be read by all CPUs but only written to by the owning CPU.
2117
2118Depending upon the data cache line size, the per-CPU fields of the
2119``bakery_lock_t`` structure for multiple CPUs may exist on a single cache line.
2120These per-CPU fields can be read and written during lock contention by multiple
2121CPUs with mismatched memory attributes. Since these fields are a part of the
2122lock implementation, they do not have access to any other locking primitive to
2123safeguard against the resulting coherency issues. As a result, simple software
2124cache maintenance is not enough to allocate them in coherent memory. Consider
2125the following example.
2126
2127CPU0 updates its per-CPU field with data cache enabled. This write updates a
2128local cache line which contains a copy of the fields for other CPUs as well. Now
2129CPU1 updates its per-CPU field of the ``bakery_lock_t`` structure with data cache
2130disabled. CPU1 then issues a DCIVAC operation to invalidate any stale copies of
2131its field in any other cache line in the system. This operation will invalidate
2132the update made by CPU0 as well.
2133
2134To use bakery locks when ``USE_COHERENT_MEM`` is disabled, the lock data structure
2135has been redesigned. The changes utilise the characteristic of Lamport's Bakery
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002136algorithm mentioned earlier. The bakery_lock structure only allocates the memory
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002137for a single CPU. The macro ``DEFINE_BAKERY_LOCK`` allocates all the bakery locks
2138needed for a CPU into a section ``bakery_lock``. The linker allocates the memory
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002139for other cores by using the total size allocated for the bakery_lock section
2140and multiplying it with (PLATFORM_CORE_COUNT - 1). This enables software to
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002141perform software cache maintenance on the lock data structure without running
2142into coherency issues associated with mismatched attributes.
2143
2144The bakery lock data structure ``bakery_info_t`` is defined for use when
2145``USE_COHERENT_MEM`` is disabled as follows:
2146
2147.. code:: c
2148
2149 typedef struct bakery_info {
2150 /*
2151 * The lock_data is a bit-field of 2 members:
2152 * Bit[0] : choosing. This field is set when the CPU is
2153 * choosing its bakery number.
2154 * Bits[1 - 15] : number. This is the bakery number allocated.
2155 */
2156 volatile uint16_t lock_data;
2157 } bakery_info_t;
2158
2159The ``bakery_info_t`` represents a single per-CPU field of one lock and
2160the combination of corresponding ``bakery_info_t`` structures for all CPUs in the
2161system represents the complete bakery lock. The view in memory for a system
2162with n bakery locks are:
2163
2164::
2165
2166 bakery_lock section start
2167 |----------------|
2168 | `bakery_info_t`| <-- Lock_0 per-CPU field
2169 | Lock_0 | for CPU0
2170 |----------------|
2171 | `bakery_info_t`| <-- Lock_1 per-CPU field
2172 | Lock_1 | for CPU0
2173 |----------------|
2174 | .... |
2175 |----------------|
2176 | `bakery_info_t`| <-- Lock_N per-CPU field
2177 | Lock_N | for CPU0
2178 ------------------
2179 | XXXXX |
2180 | Padding to |
2181 | next Cache WB | <--- Calculate PERCPU_BAKERY_LOCK_SIZE, allocate
2182 | Granule | continuous memory for remaining CPUs.
2183 ------------------
2184 | `bakery_info_t`| <-- Lock_0 per-CPU field
2185 | Lock_0 | for CPU1
2186 |----------------|
2187 | `bakery_info_t`| <-- Lock_1 per-CPU field
2188 | Lock_1 | for CPU1
2189 |----------------|
2190 | .... |
2191 |----------------|
2192 | `bakery_info_t`| <-- Lock_N per-CPU field
2193 | Lock_N | for CPU1
2194 ------------------
2195 | XXXXX |
2196 | Padding to |
2197 | next Cache WB |
2198 | Granule |
2199 ------------------
2200
2201Consider a system of 2 CPUs with 'N' bakery locks as shown above. For an
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002202operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002203``bakery_lock`` section need to be fetched and appropriate cache operations need
2204to be performed for each access.
2205
Dan Handley610e7e12018-03-01 18:44:00 +00002206On Arm Platforms, bakery locks are used in psci (``psci_locks``) and power controller
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002207driver (``arm_lock``).
2208
2209Non Functional Impact of removing coherent memory
2210~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2211
2212Removal of the coherent memory region leads to the additional software overhead
2213of performing cache maintenance for the affected data structures. However, since
2214the memory where the data structures are allocated is cacheable, the overhead is
2215mostly mitigated by an increase in performance.
2216
2217There is however a performance impact for bakery locks, due to:
2218
2219- Additional cache maintenance operations, and
2220- Multiple cache line reads for each lock operation, since the bakery locks
2221 for each CPU are distributed across different cache lines.
2222
2223The implementation has been optimized to minimize this additional overhead.
2224Measurements indicate that when bakery locks are allocated in Normal memory, the
2225minimum latency of acquiring a lock is on an average 3-4 micro seconds whereas
2226in Device memory the same is 2 micro seconds. The measurements were done on the
Dan Handley610e7e12018-03-01 18:44:00 +00002227Juno Arm development platform.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002228
2229As mentioned earlier, almost a page of memory can be saved by disabling
2230``USE_COHERENT_MEM``. Each platform needs to consider these trade-offs to decide
2231whether coherent memory should be used. If a platform disables
2232``USE_COHERENT_MEM`` and needs to use bakery locks in the porting layer, it can
2233optionally define macro ``PLAT_PERCPU_BAKERY_LOCK_SIZE`` (see the
Paul Beesleyf8640672019-04-12 14:19:42 +01002234:ref:`Porting Guide`). Refer to the reference platform code for examples.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002235
2236Isolating code and read-only data on separate memory pages
2237----------------------------------------------------------
2238
Dan Handley610e7e12018-03-01 18:44:00 +00002239In the Armv8-A VMSA, translation table entries include fields that define the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002240properties of the target memory region, such as its access permissions. The
2241smallest unit of memory that can be addressed by a translation table entry is
2242a memory page. Therefore, if software needs to set different permissions on two
2243memory regions then it needs to map them using different memory pages.
2244
2245The default memory layout for each BL image is as follows:
2246
2247::
2248
2249 | ... |
2250 +-------------------+
2251 | Read-write data |
2252 +-------------------+ Page boundary
2253 | <Padding> |
2254 +-------------------+
2255 | Exception vectors |
2256 +-------------------+ 2 KB boundary
2257 | <Padding> |
2258 +-------------------+
2259 | Read-only data |
2260 +-------------------+
2261 | Code |
2262 +-------------------+ BLx_BASE
2263
Paul Beesleyba3ed402019-03-13 16:20:44 +00002264.. note::
2265 The 2KB alignment for the exception vectors is an architectural
2266 requirement.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002267
2268The read-write data start on a new memory page so that they can be mapped with
2269read-write permissions, whereas the code and read-only data below are configured
2270as read-only.
2271
2272However, the read-only data are not aligned on a page boundary. They are
2273contiguous to the code. Therefore, the end of the code section and the beginning
2274of the read-only data one might share a memory page. This forces both to be
2275mapped with the same memory attributes. As the code needs to be executable, this
2276means that the read-only data stored on the same memory page as the code are
2277executable as well. This could potentially be exploited as part of a security
2278attack.
2279
2280TF provides the build flag ``SEPARATE_CODE_AND_RODATA`` to isolate the code and
2281read-only data on separate memory pages. This in turn allows independent control
2282of the access permissions for the code and read-only data. In this case,
2283platform code gets a finer-grained view of the image layout and can
2284appropriately map the code region as executable and the read-only data as
2285execute-never.
2286
2287This has an impact on memory footprint, as padding bytes need to be introduced
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002288between the code and read-only data to ensure the segregation of the two. To
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002289limit the memory cost, this flag also changes the memory layout such that the
2290code and exception vectors are now contiguous, like so:
2291
2292::
2293
2294 | ... |
2295 +-------------------+
2296 | Read-write data |
2297 +-------------------+ Page boundary
2298 | <Padding> |
2299 +-------------------+
2300 | Read-only data |
2301 +-------------------+ Page boundary
2302 | <Padding> |
2303 +-------------------+
2304 | Exception vectors |
2305 +-------------------+ 2 KB boundary
2306 | <Padding> |
2307 +-------------------+
2308 | Code |
2309 +-------------------+ BLx_BASE
2310
2311With this more condensed memory layout, the separation of read-only data will
2312add zero or one page to the memory footprint of each BL image. Each platform
2313should consider the trade-off between memory footprint and security.
2314
Dan Handley610e7e12018-03-01 18:44:00 +00002315This build flag is disabled by default, minimising memory footprint. On Arm
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002316platforms, it is enabled.
2317
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002318Publish and Subscribe Framework
2319-------------------------------
2320
2321The Publish and Subscribe Framework allows EL3 components to define and publish
2322events, to which other EL3 components can subscribe.
2323
2324The following macros are provided by the framework:
2325
2326- ``REGISTER_PUBSUB_EVENT(event)``: Defines an event, and takes one argument,
2327 the event name, which must be a valid C identifier. All calls to
2328 ``REGISTER_PUBSUB_EVENT`` macro must be placed in the file
2329 ``pubsub_events.h``.
2330
2331- ``PUBLISH_EVENT_ARG(event, arg)``: Publishes a defined event, by iterating
2332 subscribed handlers and calling them in turn. The handlers will be passed the
2333 parameter ``arg``. The expected use-case is to broadcast an event.
2334
2335- ``PUBLISH_EVENT(event)``: Like ``PUBLISH_EVENT_ARG``, except that the value
2336 ``NULL`` is passed to subscribed handlers.
2337
2338- ``SUBSCRIBE_TO_EVENT(event, handler)``: Registers the ``handler`` to
2339 subscribe to ``event``. The handler will be executed whenever the ``event``
2340 is published.
2341
2342- ``for_each_subscriber(event, subscriber)``: Iterates through all handlers
2343 subscribed for ``event``. ``subscriber`` must be a local variable of type
2344 ``pubsub_cb_t *``, and will point to each subscribed handler in turn during
2345 iteration. This macro can be used for those patterns that none of the
2346 ``PUBLISH_EVENT_*()`` macros cover.
2347
2348Publishing an event that wasn't defined using ``REGISTER_PUBSUB_EVENT`` will
2349result in build error. Subscribing to an undefined event however won't.
2350
2351Subscribed handlers must be of type ``pubsub_cb_t``, with following function
2352signature:
2353
Paul Beesley493e3492019-03-13 15:11:04 +00002354.. code:: c
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002355
2356 typedef void* (*pubsub_cb_t)(const void *arg);
2357
2358There may be arbitrary number of handlers registered to the same event. The
2359order in which subscribed handlers are notified when that event is published is
2360not defined. Subscribed handlers may be executed in any order; handlers should
2361not assume any relative ordering amongst them.
2362
2363Publishing an event on a PE will result in subscribed handlers executing on that
2364PE only; it won't cause handlers to execute on a different PE.
2365
2366Note that publishing an event on a PE blocks until all the subscribed handlers
2367finish executing on the PE.
2368
Dan Handley610e7e12018-03-01 18:44:00 +00002369TF-A generic code publishes and subscribes to some events within. Platform
2370ports are discouraged from subscribing to them. These events may be withdrawn,
2371renamed, or have their semantics altered in the future. Platforms may however
2372register, publish, and subscribe to platform-specific events.
Dimitris Papastamosa7921b92017-10-13 15:27:58 +01002373
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002374Publish and Subscribe Example
2375~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2376
2377A publisher that wants to publish event ``foo`` would:
2378
2379- Define the event ``foo`` in the ``pubsub_events.h``.
2380
Paul Beesley493e3492019-03-13 15:11:04 +00002381 .. code:: c
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002382
2383 REGISTER_PUBSUB_EVENT(foo);
2384
2385- Depending on the nature of event, use one of ``PUBLISH_EVENT_*()`` macros to
2386 publish the event at the appropriate path and time of execution.
2387
2388A subscriber that wants to subscribe to event ``foo`` published above would
2389implement:
2390
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002391.. code:: c
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002392
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002393 void *foo_handler(const void *arg)
2394 {
2395 void *result;
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002396
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002397 /* Do handling ... */
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002398
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002399 return result;
2400 }
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002401
Sandrine Bailleuxf5a91002019-02-08 10:50:28 +01002402 SUBSCRIBE_TO_EVENT(foo, foo_handler);
Jeenu Viswambharane3f22002017-09-22 08:32:10 +01002403
Daniel Boulby468f0d72018-09-18 11:45:51 +01002404
2405Reclaiming the BL31 initialization code
2406~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2407
2408A significant amount of the code used for the initialization of BL31 is never
2409needed again after boot time. In order to reduce the runtime memory
2410footprint, the memory used for this code can be reclaimed after initialization
2411has finished and be used for runtime data.
2412
2413The build option ``RECLAIM_INIT_CODE`` can be set to mark this boot time code
2414with a ``.text.init.*`` attribute which can be filtered and placed suitably
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002415within the BL image for later reclamation by the platform. The platform can
2416specify the filter and the memory region for this init section in BL31 via the
Daniel Boulby468f0d72018-09-18 11:45:51 +01002417plat.ld.S linker script. For example, on the FVP, this section is placed
2418overlapping the secondary CPU stacks so that after the cold boot is done, this
2419memory can be reclaimed for the stacks. The init memory section is initially
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002420mapped with ``RO``, ``EXECUTE`` attributes. After BL31 initialization has
Daniel Boulby468f0d72018-09-18 11:45:51 +01002421completed, the FVP changes the attributes of this section to ``RW``,
2422``EXECUTE_NEVER`` allowing it to be used for runtime data. The memory attributes
2423are changed within the ``bl31_plat_runtime_setup`` platform hook. The init
2424section section can be reclaimed for any data which is accessed after cold
2425boot initialization and it is upto the platform to make the decision.
2426
Paul Beesleyf8640672019-04-12 14:19:42 +01002427.. _firmware_design_pmf:
2428
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002429Performance Measurement Framework
2430---------------------------------
2431
2432The Performance Measurement Framework (PMF) facilitates collection of
Dan Handley610e7e12018-03-01 18:44:00 +00002433timestamps by registered services and provides interfaces to retrieve them
2434from within TF-A. A platform can choose to expose appropriate SMCs to
2435retrieve these collected timestamps.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002436
2437By default, the global physical counter is used for the timestamp
2438value and is read via ``CNTPCT_EL0``. The framework allows to retrieve
2439timestamps captured by other CPUs.
2440
2441Timestamp identifier format
2442~~~~~~~~~~~~~~~~~~~~~~~~~~~
2443
2444A PMF timestamp is uniquely identified across the system via the
2445timestamp ID or ``tid``. The ``tid`` is composed as follows:
2446
2447::
2448
2449 Bits 0-7: The local timestamp identifier.
2450 Bits 8-9: Reserved.
2451 Bits 10-15: The service identifier.
2452 Bits 16-31: Reserved.
2453
2454#. The service identifier. Each PMF service is identified by a
2455 service name and a service identifier. Both the service name and
2456 identifier are unique within the system as a whole.
2457
2458#. The local timestamp identifier. This identifier is unique within a given
2459 service.
2460
2461Registering a PMF service
2462~~~~~~~~~~~~~~~~~~~~~~~~~
2463
2464To register a PMF service, the ``PMF_REGISTER_SERVICE()`` macro from ``pmf.h``
2465is used. The arguments required are the service name, the service ID,
2466the total number of local timestamps to be captured and a set of flags.
2467
2468The ``flags`` field can be specified as a bitwise-OR of the following values:
2469
2470::
2471
2472 PMF_STORE_ENABLE: The timestamp is stored in memory for later retrieval.
2473 PMF_DUMP_ENABLE: The timestamp is dumped on the serial console.
2474
2475The ``PMF_REGISTER_SERVICE()`` reserves memory to store captured
2476timestamps in a PMF specific linker section at build time.
2477Additionally, it defines necessary functions to capture and
2478retrieve a particular timestamp for the given service at runtime.
2479
Dan Handley610e7e12018-03-01 18:44:00 +00002480The macro ``PMF_REGISTER_SERVICE()`` only enables capturing PMF timestamps
2481from within TF-A. In order to retrieve timestamps from outside of TF-A, the
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002482``PMF_REGISTER_SERVICE_SMC()`` macro must be used instead. This macro
2483accepts the same set of arguments as the ``PMF_REGISTER_SERVICE()``
2484macro but additionally supports retrieving timestamps using SMCs.
2485
2486Capturing a timestamp
2487~~~~~~~~~~~~~~~~~~~~~
2488
2489PMF timestamps are stored in a per-service timestamp region. On a
2490system with multiple CPUs, each timestamp is captured and stored
2491in a per-CPU cache line aligned memory region.
2492
2493Having registered the service, the ``PMF_CAPTURE_TIMESTAMP()`` macro can be
2494used to capture a timestamp at the location where it is used. The macro
2495takes the service name, a local timestamp identifier and a flag as arguments.
2496
2497The ``flags`` field argument can be zero, or ``PMF_CACHE_MAINT`` which
2498instructs PMF to do cache maintenance following the capture. Cache
2499maintenance is required if any of the service's timestamps are captured
2500with data cache disabled.
2501
2502To capture a timestamp in assembly code, the caller should use
2503``pmf_calc_timestamp_addr`` macro (defined in ``pmf_asm_macros.S``) to
2504calculate the address of where the timestamp would be stored. The
2505caller should then read ``CNTPCT_EL0`` register to obtain the timestamp
2506and store it at the determined address for later retrieval.
2507
2508Retrieving a timestamp
2509~~~~~~~~~~~~~~~~~~~~~~
2510
Dan Handley610e7e12018-03-01 18:44:00 +00002511From within TF-A, timestamps for individual CPUs can be retrieved using either
2512``PMF_GET_TIMESTAMP_BY_MPIDR()`` or ``PMF_GET_TIMESTAMP_BY_INDEX()`` macros.
2513These macros accept the CPU's MPIDR value, or its ordinal position
2514respectively.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002515
Dan Handley610e7e12018-03-01 18:44:00 +00002516From outside TF-A, timestamps for individual CPUs can be retrieved by calling
2517into ``pmf_smc_handler()``.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002518
Paul Beesley493e3492019-03-13 15:11:04 +00002519::
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002520
2521 Interface : pmf_smc_handler()
2522 Argument : unsigned int smc_fid, u_register_t x1,
2523 u_register_t x2, u_register_t x3,
2524 u_register_t x4, void *cookie,
2525 void *handle, u_register_t flags
2526 Return : uintptr_t
2527
2528 smc_fid: Holds the SMC identifier which is either `PMF_SMC_GET_TIMESTAMP_32`
2529 when the caller of the SMC is running in AArch32 mode
2530 or `PMF_SMC_GET_TIMESTAMP_64` when the caller is running in AArch64 mode.
2531 x1: Timestamp identifier.
2532 x2: The `mpidr` of the CPU for which the timestamp has to be retrieved.
2533 This can be the `mpidr` of a different core to the one initiating
2534 the SMC. In that case, service specific cache maintenance may be
2535 required to ensure the updated copy of the timestamp is returned.
2536 x3: A flags value that is either 0 or `PMF_CACHE_MAINT`. If
2537 `PMF_CACHE_MAINT` is passed, then the PMF code will perform a
2538 cache invalidate before reading the timestamp. This ensures
2539 an updated copy is returned.
2540
2541The remaining arguments, ``x4``, ``cookie``, ``handle`` and ``flags`` are unused
2542in this implementation.
2543
2544PMF code structure
2545~~~~~~~~~~~~~~~~~~
2546
2547#. ``pmf_main.c`` consists of core functions that implement service registration,
2548 initialization, storing, dumping and retrieving timestamps.
2549
2550#. ``pmf_smc.c`` contains the SMC handling for registered PMF services.
2551
2552#. ``pmf.h`` contains the public interface to Performance Measurement Framework.
2553
2554#. ``pmf_asm_macros.S`` consists of macros to facilitate capturing timestamps in
2555 assembly code.
2556
2557#. ``pmf_helpers.h`` is an internal header used by ``pmf.h``.
2558
Dan Handley610e7e12018-03-01 18:44:00 +00002559Armv8-A Architecture Extensions
2560-------------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002561
Dan Handley610e7e12018-03-01 18:44:00 +00002562TF-A makes use of Armv8-A Architecture Extensions where applicable. This
2563section lists the usage of Architecture Extensions, and build flags
2564controlling them.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002565
2566In general, and unless individually mentioned, the build options
Alexei Fedorovb567e5d2019-03-11 16:51:47 +00002567``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` select the Architecture Extension to
Dan Handley610e7e12018-03-01 18:44:00 +00002568target when building TF-A. Subsequent Arm Architecture Extensions are backward
2569compatible with previous versions.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002570
2571The build system only requires that ``ARM_ARCH_MAJOR`` and ``ARM_ARCH_MINOR`` have a
2572valid numeric value. These build options only control whether or not
Dan Handley610e7e12018-03-01 18:44:00 +00002573Architecture Extension-specific code is included in the build. Otherwise, TF-A
2574targets the base Armv8.0-A architecture; i.e. as if ``ARM_ARCH_MAJOR`` == 8
2575and ``ARM_ARCH_MINOR`` == 0, which are also their respective default values.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002576
Paul Beesleyd2fcc4e2019-05-29 13:59:40 +01002577.. seealso:: :ref:`Build Options`
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002578
2579For details on the Architecture Extension and available features, please refer
2580to the respective Architecture Extension Supplement.
2581
Dan Handley610e7e12018-03-01 18:44:00 +00002582Armv8.1-A
2583~~~~~~~~~
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002584
2585This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` >= 8, or when
2586``ARM_ARCH_MAJOR`` == 8 and ``ARM_ARCH_MINOR`` >= 1.
2587
Soby Mathewad042012019-09-25 14:03:41 +01002588- By default, a load-/store-exclusive instruction pair is used to implement
2589 spinlocks. The ``USE_SPINLOCK_CAS`` build option when set to 1 selects the
2590 spinlock implementation using the ARMv8.1-LSE Compare and Swap instruction.
2591 Notice this instruction is only available in AArch64 execution state, so
2592 the option is only available to AArch64 builds.
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002593
Dan Handley610e7e12018-03-01 18:44:00 +00002594Armv8.2-A
2595~~~~~~~~~
Isla Mitchellc4a1a072017-08-07 11:20:13 +01002596
Antonio Nino Diaz633703a2019-02-19 13:14:06 +00002597- The presence of ARMv8.2-TTCNP is detected at runtime. When it is present, the
2598 Common not Private (TTBRn_ELx.CnP) bit is enabled to indicate that multiple
Sandrine Bailleuxfee6e262018-01-29 14:48:15 +01002599 Processing Elements in the same Inner Shareable domain use the same
2600 translation table entries for a given stage of translation for a particular
2601 translation regime.
Isla Mitchellc4a1a072017-08-07 11:20:13 +01002602
Jeenu Viswambharancbad6612018-08-15 14:29:29 +01002603Armv8.3-A
2604~~~~~~~~~
2605
Antonio Nino Diaz594811b2019-01-31 11:58:00 +00002606- Pointer authentication features of Armv8.3-A are unconditionally enabled in
2607 the Non-secure world so that lower ELs are allowed to use them without
2608 causing a trap to EL3.
2609
2610 In order to enable the Secure world to use it, ``CTX_INCLUDE_PAUTH_REGS``
2611 must be set to 1. This will add all pointer authentication system registers
2612 to the context that is saved when doing a world switch.
Jeenu Viswambharancbad6612018-08-15 14:29:29 +01002613
Alexei Fedorov2831d582019-03-13 11:05:07 +00002614 The TF-A itself has support for pointer authentication at runtime
Alexei Fedorov90f2e882019-05-24 12:17:09 +01002615 that can be enabled by setting ``BRANCH_PROTECTION`` option to non-zero and
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002616 ``CTX_INCLUDE_PAUTH_REGS`` to 1. This enables pointer authentication in BL1,
2617 BL2, BL31, and the TSP if it is used.
2618
Alexei Fedorov2831d582019-03-13 11:05:07 +00002619 These options are experimental features.
2620
2621 Note that Pointer Authentication is enabled for Non-secure world irrespective
2622 of the value of these build flags if the CPU supports it.
2623
Alexei Fedorovb567e5d2019-03-11 16:51:47 +00002624 If ``ARM_ARCH_MAJOR == 8`` and ``ARM_ARCH_MINOR >= 3`` the code footprint of
2625 enabling PAuth is lower because the compiler will use the optimized
2626 PAuth instructions rather than the backwards-compatible ones.
2627
Alexei Fedorov90f2e882019-05-24 12:17:09 +01002628Armv8.5-A
2629~~~~~~~~~
2630
2631- Branch Target Identification feature is selected by ``BRANCH_PROTECTION``
Justin Chadwell55c73512019-07-18 16:16:32 +01002632 option set to 1. This option defaults to 0 and this is an experimental
2633 feature.
2634
2635- Memory Tagging Extension feature is unconditionally enabled for both worlds
2636 (at EL0 and S-EL0) if it is only supported at EL0. If instead it is
2637 implemented at all ELs, it is unconditionally enabled for only the normal
2638 world. To enable it for the secure world as well, the build option
2639 ``CTX_INCLUDE_MTE_REGS`` is required. If the hardware does not implement
2640 MTE support at all, it is always disabled, no matter what build options
2641 are used.
Alexei Fedorov90f2e882019-05-24 12:17:09 +01002642
Dan Handley610e7e12018-03-01 18:44:00 +00002643Armv7-A
2644~~~~~~~
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002645
2646This Architecture Extension is targeted when ``ARM_ARCH_MAJOR`` == 7.
2647
Dan Handley610e7e12018-03-01 18:44:00 +00002648There are several Armv7-A extensions available. Obviously the TrustZone
2649extension is mandatory to support the TF-A bootloader and runtime services.
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002650
Dan Handley610e7e12018-03-01 18:44:00 +00002651Platform implementing an Armv7-A system can to define from its target
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002652Cortex-A architecture through ``ARM_CORTEX_A<X> = yes`` in their
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002653``platform.mk`` script. For example ``ARM_CORTEX_A15=yes`` for a
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002654Cortex-A15 target.
2655
2656Platform can also set ``ARM_WITH_NEON=yes`` to enable neon support.
Paul Beesleyf2ec7142019-10-04 16:17:46 +00002657Note that using neon at runtime has constraints on non secure world context.
Dan Handley610e7e12018-03-01 18:44:00 +00002658TF-A does not yet provide VFP context management.
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002659
2660Directive ``ARM_CORTEX_A<x>`` and ``ARM_WITH_NEON`` are used to set
2661the toolchain target architecture directive.
2662
2663Platform may choose to not define straight the toolchain target architecture
2664directive by defining ``MARCH32_DIRECTIVE``.
2665I.e:
2666
Paul Beesley493e3492019-03-13 15:11:04 +00002667.. code:: make
Etienne Carriere1374fcb2017-11-08 13:48:40 +01002668
2669 MARCH32_DIRECTIVE := -mach=armv7-a
2670
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002671Code Structure
2672--------------
2673
Dan Handley610e7e12018-03-01 18:44:00 +00002674TF-A code is logically divided between the three boot loader stages mentioned
2675in the previous sections. The code is also divided into the following
2676categories (present as directories in the source code):
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002677
2678- **Platform specific.** Choice of architecture specific code depends upon
2679 the platform.
2680- **Common code.** This is platform and architecture agnostic code.
2681- **Library code.** This code comprises of functionality commonly used by all
2682 other code. The PSCI implementation and other EL3 runtime frameworks reside
2683 as Library components.
2684- **Stage specific.** Code specific to a boot stage.
2685- **Drivers.**
2686- **Services.** EL3 runtime services (eg: SPD). Specific SPD services
2687 reside in the ``services/spd`` directory (e.g. ``services/spd/tspd``).
2688
2689Each boot loader stage uses code from one or more of the above mentioned
2690categories. Based upon the above, the code layout looks like this:
2691
2692::
2693
2694 Directory Used by BL1? Used by BL2? Used by BL31?
2695 bl1 Yes No No
2696 bl2 No Yes No
2697 bl31 No No Yes
2698 plat Yes Yes Yes
2699 drivers Yes No Yes
2700 common Yes Yes Yes
2701 lib Yes Yes Yes
2702 services No No Yes
2703
Sandrine Bailleux15530dd2019-02-08 15:26:36 +01002704The build system provides a non configurable build option IMAGE_BLx for each
2705boot loader stage (where x = BL stage). e.g. for BL1 , IMAGE_BL1 will be
Dan Handley610e7e12018-03-01 18:44:00 +00002706defined by the build system. This enables TF-A to compile certain code only
2707for specific boot loader stages
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002708
2709All assembler files have the ``.S`` extension. The linker source files for each
2710boot stage have the extension ``.ld.S``. These are processed by GCC to create the
2711linker scripts which have the extension ``.ld``.
2712
2713FDTs provide a description of the hardware platform and are used by the Linux
2714kernel at boot time. These can be found in the ``fdts`` directory.
2715
Paul Beesleyf8640672019-04-12 14:19:42 +01002716.. rubric:: References
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002717
Paul Beesleyf8640672019-04-12 14:19:42 +01002718- `Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D)`_
2719
2720- `Power State Coordination Interface PDD`_
2721
Sandrine Bailleuxd9202df2020-04-17 14:06:52 +02002722- `SMC Calling Convention`_
Paul Beesleyf8640672019-04-12 14:19:42 +01002723
2724- :ref:`Interrupt Management Framework`
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002725
2726--------------
2727
Petre-Ionut Tudor620a7022019-09-27 15:13:21 +01002728*Copyright (c) 2013-2020, Arm Limited and Contributors. All rights reserved.*
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002729
Paul Beesleyf8640672019-04-12 14:19:42 +01002730.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
laurenw-arm03e7e612020-04-16 10:02:17 -05002731.. _SMCCC: https://developer.arm.com/docs/den0028/latest
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002732.. _PSCI: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
2733.. _Power State Coordination Interface PDD: http://infocenter.arm.com/help/topic/com.arm.doc.den0022d/Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
Petre-Ionut Tudor620a7022019-09-27 15:13:21 +01002734.. _Arm ARM: https://developer.arm.com/docs/ddi0487/latest
laurenw-arm03e7e612020-04-16 10:02:17 -05002735.. _SMC Calling Convention: https://developer.arm.com/docs/den0028/latest
Sandrine Bailleux30918422019-04-24 10:41:24 +02002736.. _Trusted Board Boot Requirements CLIENT (TBBR-CLIENT) Armv8-A (ARM DEN0006D): https://developer.arm.com/docs/den0006/latest/trusted-board-boot-requirements-client-tbbr-client-armv8-a
Douglas Raillardd7c21b72017-06-28 15:23:03 +01002737
Paul Beesley814f8c02019-03-13 15:49:27 +00002738.. |Image 1| image:: ../resources/diagrams/rt-svc-descs-layout.png