Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Vikram Kanigiri | fbb1301 | 2016-02-15 11:54:14 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 7 | #include <arch_helpers.h> |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 8 | #include <arm_config.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 9 | #include <assert.h> |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 10 | #include <debug.h> |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 11 | #include <errno.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 12 | #include <mmio.h> |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 13 | #include <plat_arm.h> |
Isla Mitchell | d254879 | 2017-07-14 10:48:25 +0100 | [diff] [blame] | 14 | #include <platform.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 15 | #include <psci.h> |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 16 | #include <v2m_def.h> |
Dan Handley | 4d2e49d | 2014-04-11 11:52:12 +0100 | [diff] [blame] | 17 | #include "drivers/pwrc/fvp_pwrc.h" |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 18 | #include "fvp_def.h" |
| 19 | #include "fvp_private.h" |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 20 | |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 21 | |
Soby Mathew | 7799cf7 | 2015-04-16 14:49:09 +0100 | [diff] [blame] | 22 | #if ARM_RECOM_STATE_ID_ENC |
| 23 | /* |
| 24 | * The table storing the valid idle power states. Ensure that the |
| 25 | * array entries are populated in ascending order of state-id to |
| 26 | * enable us to use binary search during power state validation. |
| 27 | * The table must be terminated by a NULL entry. |
| 28 | */ |
| 29 | const unsigned int arm_pm_idle_states[] = { |
| 30 | /* State-id - 0x01 */ |
| 31 | arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET, |
| 32 | ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), |
| 33 | /* State-id - 0x02 */ |
| 34 | arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, |
| 35 | ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), |
| 36 | /* State-id - 0x22 */ |
| 37 | arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, |
| 38 | ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), |
| 39 | 0, |
| 40 | }; |
| 41 | #endif |
| 42 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 43 | /******************************************************************************* |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 44 | * Function which implements the common FVP specific operations to power down a |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 45 | * cluster in response to a CPU_OFF or CPU_SUSPEND request. |
| 46 | ******************************************************************************/ |
Sandrine Bailleux | a64a854 | 2015-03-05 10:54:34 +0000 | [diff] [blame] | 47 | static void fvp_cluster_pwrdwn_common(void) |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 48 | { |
| 49 | uint64_t mpidr = read_mpidr_el1(); |
| 50 | |
dp-arm | ee3457b | 2017-05-23 09:32:49 +0100 | [diff] [blame] | 51 | #if ENABLE_SPE_FOR_LOWER_ELS |
| 52 | /* |
| 53 | * On power down we need to disable statistical profiling extensions |
| 54 | * before exiting coherency. |
| 55 | */ |
| 56 | arm_disable_spe(); |
| 57 | #endif |
| 58 | |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 59 | /* Disable coherency if this cluster is to be turned off */ |
Vikram Kanigiri | fbb1301 | 2016-02-15 11:54:14 +0000 | [diff] [blame] | 60 | fvp_interconnect_disable(); |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 61 | |
| 62 | /* Program the power controller to turn the cluster off */ |
| 63 | fvp_pwrc_write_pcoffr(mpidr); |
| 64 | } |
| 65 | |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 66 | static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_state) |
| 67 | { |
| 68 | unsigned long mpidr; |
| 69 | |
| 70 | assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == |
| 71 | ARM_LOCAL_STATE_OFF); |
| 72 | |
| 73 | /* Get the mpidr for this cpu */ |
| 74 | mpidr = read_mpidr_el1(); |
| 75 | |
| 76 | /* Perform the common cluster specific operations */ |
| 77 | if (target_state->pwr_domain_state[ARM_PWR_LVL1] == |
| 78 | ARM_LOCAL_STATE_OFF) { |
| 79 | /* |
| 80 | * This CPU might have woken up whilst the cluster was |
| 81 | * attempting to power down. In this case the FVP power |
| 82 | * controller will have a pending cluster power off request |
| 83 | * which needs to be cleared by writing to the PPONR register. |
| 84 | * This prevents the power controller from interpreting a |
| 85 | * subsequent entry of this cpu into a simple wfi as a power |
| 86 | * down request. |
| 87 | */ |
| 88 | fvp_pwrc_write_pponr(mpidr); |
| 89 | |
| 90 | /* Enable coherency if this cluster was off */ |
Vikram Kanigiri | fbb1301 | 2016-02-15 11:54:14 +0000 | [diff] [blame] | 91 | fvp_interconnect_enable(); |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 92 | } |
| 93 | |
| 94 | /* |
| 95 | * Clear PWKUPR.WEN bit to ensure interrupts do not interfere |
| 96 | * with a cpu power down unless the bit is set again |
| 97 | */ |
| 98 | fvp_pwrc_clr_wen(mpidr); |
| 99 | } |
| 100 | |
| 101 | |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 102 | /******************************************************************************* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 103 | * FVP handler called when a CPU is about to enter standby. |
Vikram Kanigiri | 3b7c59b | 2014-03-21 11:57:10 +0000 | [diff] [blame] | 104 | ******************************************************************************/ |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 105 | void fvp_cpu_standby(plat_local_state_t cpu_state) |
Vikram Kanigiri | 3b7c59b | 2014-03-21 11:57:10 +0000 | [diff] [blame] | 106 | { |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 107 | |
| 108 | assert(cpu_state == ARM_LOCAL_STATE_RET); |
| 109 | |
Andrew Thoelke | 42e75a7 | 2014-04-28 12:28:39 +0100 | [diff] [blame] | 110 | /* |
| 111 | * Enter standby state |
| 112 | * dsb is good practice before using wfi to enter low power states |
| 113 | */ |
| 114 | dsb(); |
Vikram Kanigiri | 3b7c59b | 2014-03-21 11:57:10 +0000 | [diff] [blame] | 115 | wfi(); |
Vikram Kanigiri | 3b7c59b | 2014-03-21 11:57:10 +0000 | [diff] [blame] | 116 | } |
| 117 | |
| 118 | /******************************************************************************* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 119 | * FVP handler called when a power domain is about to be turned on. The |
| 120 | * mpidr determines the CPU to be turned on. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 121 | ******************************************************************************/ |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 122 | int fvp_pwr_domain_on(u_register_t mpidr) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 123 | { |
| 124 | int rc = PSCI_E_SUCCESS; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 125 | unsigned int psysr; |
| 126 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 127 | /* |
Sandrine Bailleux | 7175bde | 2015-12-08 14:18:24 +0000 | [diff] [blame] | 128 | * Ensure that we do not cancel an inflight power off request for the |
| 129 | * target cpu. That would leave it in a zombie wfi. Wait for it to power |
| 130 | * off and then program the power controller to turn that CPU on. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 131 | */ |
| 132 | do { |
| 133 | psysr = fvp_pwrc_read_psysr(mpidr); |
| 134 | } while (psysr & PSYSR_AFF_L0); |
| 135 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 136 | fvp_pwrc_write_pponr(mpidr); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 137 | return rc; |
| 138 | } |
| 139 | |
| 140 | /******************************************************************************* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 141 | * FVP handler called when a power domain is about to be turned off. The |
| 142 | * target_state encodes the power state that each level should transition to. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 143 | ******************************************************************************/ |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 144 | void fvp_pwr_domain_off(const psci_power_state_t *target_state) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 145 | { |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 146 | assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == |
| 147 | ARM_LOCAL_STATE_OFF); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 148 | |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 149 | /* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 150 | * If execution reaches this stage then this power domain will be |
| 151 | * suspended. Perform at least the cpu specific actions followed |
| 152 | * by the cluster specific operations if applicable. |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 153 | */ |
Jeenu Viswambharan | 6ad3548 | 2016-12-09 11:14:34 +0000 | [diff] [blame] | 154 | |
| 155 | /* Prevent interrupts from spuriously waking up this cpu */ |
| 156 | plat_arm_gic_cpuif_disable(); |
| 157 | |
| 158 | /* Turn redistributor off */ |
| 159 | plat_arm_gic_redistif_off(); |
| 160 | |
| 161 | /* Program the power controller to power off this cpu. */ |
| 162 | fvp_pwrc_write_ppoffr(read_mpidr_el1()); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 163 | |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 164 | if (target_state->pwr_domain_state[ARM_PWR_LVL1] == |
| 165 | ARM_LOCAL_STATE_OFF) |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 166 | fvp_cluster_pwrdwn_common(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 167 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 168 | } |
| 169 | |
| 170 | /******************************************************************************* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 171 | * FVP handler called when a power domain is about to be suspended. The |
| 172 | * target_state encodes the power state that each level should transition to. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 173 | ******************************************************************************/ |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 174 | void fvp_pwr_domain_suspend(const psci_power_state_t *target_state) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 175 | { |
Soby Mathew | ffb4ab1 | 2014-09-26 15:08:52 +0100 | [diff] [blame] | 176 | unsigned long mpidr; |
| 177 | |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 178 | /* |
| 179 | * FVP has retention only at cpu level. Just return |
| 180 | * as nothing is to be done for retention. |
| 181 | */ |
| 182 | if (target_state->pwr_domain_state[ARM_PWR_LVL0] == |
| 183 | ARM_LOCAL_STATE_RET) |
Soby Mathew | 74e52a7 | 2014-10-02 16:56:51 +0100 | [diff] [blame] | 184 | return; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 185 | |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 186 | assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == |
| 187 | ARM_LOCAL_STATE_OFF); |
| 188 | |
Soby Mathew | ffb4ab1 | 2014-09-26 15:08:52 +0100 | [diff] [blame] | 189 | /* Get the mpidr for this cpu */ |
| 190 | mpidr = read_mpidr_el1(); |
| 191 | |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 192 | /* Program the power controller to enable wakeup interrupts. */ |
| 193 | fvp_pwrc_set_wen(mpidr); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 194 | |
Jeenu Viswambharan | 6ad3548 | 2016-12-09 11:14:34 +0000 | [diff] [blame] | 195 | /* Prevent interrupts from spuriously waking up this cpu */ |
| 196 | plat_arm_gic_cpuif_disable(); |
| 197 | |
| 198 | /* |
| 199 | * The Redistributor is not powered off as it can potentially prevent |
| 200 | * wake up events reaching the CPUIF and/or might lead to losing |
| 201 | * register context. |
| 202 | */ |
| 203 | |
| 204 | /* Program the power controller to power off this cpu. */ |
| 205 | fvp_pwrc_write_ppoffr(read_mpidr_el1()); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 206 | |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 207 | /* Perform the common cluster specific operations */ |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 208 | if (target_state->pwr_domain_state[ARM_PWR_LVL1] == |
| 209 | ARM_LOCAL_STATE_OFF) |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 210 | fvp_cluster_pwrdwn_common(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 211 | } |
| 212 | |
| 213 | /******************************************************************************* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 214 | * FVP handler called when a power domain has just been powered on after |
| 215 | * being turned off earlier. The target_state encodes the low power state that |
| 216 | * each level has woken up from. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 217 | ******************************************************************************/ |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 218 | void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 219 | { |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 220 | fvp_power_domain_on_finish_common(target_state); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 221 | |
Achin Gupta | 8587639 | 2014-07-31 17:45:51 +0100 | [diff] [blame] | 222 | /* Enable the gic cpu interface */ |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 223 | plat_arm_gic_pcpu_init(); |
| 224 | |
| 225 | /* Program the gic per-cpu distributor or re-distributor interface */ |
| 226 | plat_arm_gic_cpuif_enable(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 227 | } |
| 228 | |
| 229 | /******************************************************************************* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 230 | * FVP handler called when a power domain has just been powered on after |
| 231 | * having been suspended earlier. The target_state encodes the low power state |
| 232 | * that each level has woken up from. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 233 | * TODO: At the moment we reuse the on finisher and reinitialize the secure |
| 234 | * context. Need to implement a separate suspend finisher. |
| 235 | ******************************************************************************/ |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 236 | void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 237 | { |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 238 | /* |
| 239 | * Nothing to be done on waking up from retention from CPU level. |
| 240 | */ |
| 241 | if (target_state->pwr_domain_state[ARM_PWR_LVL0] == |
| 242 | ARM_LOCAL_STATE_RET) |
| 243 | return; |
| 244 | |
Soby Mathew | 12012dd | 2015-10-26 14:01:53 +0000 | [diff] [blame] | 245 | fvp_power_domain_on_finish_common(target_state); |
| 246 | |
| 247 | /* Enable the gic cpu interface */ |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 248 | plat_arm_gic_cpuif_enable(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 249 | } |
| 250 | |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 251 | /******************************************************************************* |
| 252 | * FVP handlers to shutdown/reboot the system |
| 253 | ******************************************************************************/ |
| 254 | static void __dead2 fvp_system_off(void) |
| 255 | { |
| 256 | /* Write the System Configuration Control Register */ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 257 | mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, |
| 258 | V2M_CFGCTRL_START | |
| 259 | V2M_CFGCTRL_RW | |
| 260 | V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN)); |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 261 | wfi(); |
| 262 | ERROR("FVP System Off: operation not handled.\n"); |
| 263 | panic(); |
| 264 | } |
| 265 | |
| 266 | static void __dead2 fvp_system_reset(void) |
| 267 | { |
| 268 | /* Write the System Configuration Control Register */ |
Dan Handley | 2b6b574 | 2015-03-19 19:17:53 +0000 | [diff] [blame] | 269 | mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, |
| 270 | V2M_CFGCTRL_START | |
| 271 | V2M_CFGCTRL_RW | |
| 272 | V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT)); |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 273 | wfi(); |
| 274 | ERROR("FVP System Reset: operation not handled.\n"); |
| 275 | panic(); |
| 276 | } |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 277 | |
Jeenu Viswambharan | 095529a | 2016-08-04 09:43:15 +0100 | [diff] [blame] | 278 | static int fvp_node_hw_state(u_register_t target_cpu, |
| 279 | unsigned int power_level) |
| 280 | { |
| 281 | unsigned int psysr; |
| 282 | int ret; |
| 283 | |
| 284 | /* |
| 285 | * The format of 'power_level' is implementation-defined, but 0 must |
| 286 | * mean a CPU. We also allow 1 to denote the cluster |
| 287 | */ |
| 288 | if (power_level != ARM_PWR_LVL0 && power_level != ARM_PWR_LVL1) |
| 289 | return PSCI_E_INVALID_PARAMS; |
| 290 | |
| 291 | /* |
| 292 | * Read the status of the given MPDIR from FVP power controller. The |
| 293 | * power controller only gives us on/off status, so map that to expected |
| 294 | * return values of the PSCI call |
| 295 | */ |
| 296 | psysr = fvp_pwrc_read_psysr(target_cpu); |
| 297 | if (psysr == PSYSR_INVALID) |
| 298 | return PSCI_E_INVALID_PARAMS; |
| 299 | |
| 300 | switch (power_level) { |
| 301 | case ARM_PWR_LVL0: |
| 302 | ret = (psysr & PSYSR_AFF_L0) ? HW_ON : HW_OFF; |
| 303 | break; |
| 304 | case ARM_PWR_LVL1: |
| 305 | ret = (psysr & PSYSR_AFF_L1) ? HW_ON : HW_OFF; |
| 306 | break; |
Jeenu Viswambharan | 095529a | 2016-08-04 09:43:15 +0100 | [diff] [blame] | 307 | } |
| 308 | |
| 309 | return ret; |
| 310 | } |
| 311 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 312 | /******************************************************************************* |
Soby Mathew | feac8fc | 2015-09-29 15:47:16 +0100 | [diff] [blame] | 313 | * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard |
| 314 | * platform layer will take care of registering the handlers with PSCI. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 315 | ******************************************************************************/ |
Soby Mathew | 0b4c5a3 | 2016-10-21 17:51:22 +0100 | [diff] [blame] | 316 | plat_psci_ops_t plat_arm_psci_pm_ops = { |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 317 | .cpu_standby = fvp_cpu_standby, |
| 318 | .pwr_domain_on = fvp_pwr_domain_on, |
| 319 | .pwr_domain_off = fvp_pwr_domain_off, |
| 320 | .pwr_domain_suspend = fvp_pwr_domain_suspend, |
| 321 | .pwr_domain_on_finish = fvp_pwr_domain_on_finish, |
| 322 | .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish, |
Juan Castillo | 4dc4a47 | 2014-08-12 11:17:06 +0100 | [diff] [blame] | 323 | .system_off = fvp_system_off, |
Soby Mathew | 74e52a7 | 2014-10-02 16:56:51 +0100 | [diff] [blame] | 324 | .system_reset = fvp_system_reset, |
Soby Mathew | 0d9e852 | 2015-07-15 13:36:24 +0100 | [diff] [blame] | 325 | .validate_power_state = arm_validate_power_state, |
Jeenu Viswambharan | 095529a | 2016-08-04 09:43:15 +0100 | [diff] [blame] | 326 | .validate_ns_entrypoint = arm_validate_ns_entrypoint, |
| 327 | .get_node_hw_state = fvp_node_hw_state |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 328 | }; |