Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 1 | /* |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 5 | */ |
| 6 | #include <arch.h> |
| 7 | #include <asm_macros.S> |
| 8 | #include <assert_macros.S> |
| 9 | #include <cortex_a72.h> |
| 10 | #include <cpu_macros.S> |
| 11 | #include <plat_macros.S> |
| 12 | |
| 13 | /* --------------------------------------------- |
| 14 | * Disable L1 data cache and unified L2 cache |
| 15 | * --------------------------------------------- |
| 16 | */ |
| 17 | func cortex_a72_disable_dcache |
| 18 | mrs x1, sctlr_el3 |
| 19 | bic x1, x1, #SCTLR_C_BIT |
| 20 | msr sctlr_el3, x1 |
| 21 | isb |
| 22 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 23 | endfunc cortex_a72_disable_dcache |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 24 | |
| 25 | /* --------------------------------------------- |
| 26 | * Disable all types of L2 prefetches. |
| 27 | * --------------------------------------------- |
| 28 | */ |
| 29 | func cortex_a72_disable_l2_prefetch |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 30 | mrs x0, CORTEX_A72_ECTLR_EL1 |
| 31 | orr x0, x0, #CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT |
| 32 | mov x1, #CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK |
| 33 | orr x1, x1, #CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 34 | bic x0, x0, x1 |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 35 | msr CORTEX_A72_ECTLR_EL1, x0 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 36 | isb |
| 37 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 38 | endfunc cortex_a72_disable_l2_prefetch |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 39 | |
| 40 | /* --------------------------------------------- |
| 41 | * Disable the load-store hardware prefetcher. |
| 42 | * --------------------------------------------- |
| 43 | */ |
| 44 | func cortex_a72_disable_hw_prefetcher |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 45 | mrs x0, CORTEX_A72_CPUACTLR_EL1 |
| 46 | orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH |
| 47 | msr CORTEX_A72_CPUACTLR_EL1, x0 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 48 | isb |
| 49 | dsb ish |
| 50 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 51 | endfunc cortex_a72_disable_hw_prefetcher |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 52 | |
| 53 | /* --------------------------------------------- |
| 54 | * Disable intra-cluster coherency |
| 55 | * --------------------------------------------- |
| 56 | */ |
| 57 | func cortex_a72_disable_smp |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 58 | mrs x0, CORTEX_A72_ECTLR_EL1 |
| 59 | bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT |
| 60 | msr CORTEX_A72_ECTLR_EL1, x0 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 61 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 62 | endfunc cortex_a72_disable_smp |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 63 | |
| 64 | /* --------------------------------------------- |
| 65 | * Disable debug interfaces |
| 66 | * --------------------------------------------- |
| 67 | */ |
| 68 | func cortex_a72_disable_ext_debug |
| 69 | mov x0, #1 |
| 70 | msr osdlr_el1, x0 |
| 71 | isb |
| 72 | dsb sy |
| 73 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 74 | endfunc cortex_a72_disable_ext_debug |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 75 | |
| 76 | /* ------------------------------------------------- |
| 77 | * The CPU Ops reset function for Cortex-A72. |
| 78 | * ------------------------------------------------- |
| 79 | */ |
| 80 | func cortex_a72_reset_func |
| 81 | /* --------------------------------------------- |
| 82 | * As a bare minimum enable the SMP bit. |
| 83 | * --------------------------------------------- |
| 84 | */ |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 85 | mrs x0, CORTEX_A72_ECTLR_EL1 |
| 86 | orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT |
| 87 | msr CORTEX_A72_ECTLR_EL1, x0 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 88 | isb |
| 89 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 90 | endfunc cortex_a72_reset_func |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 91 | |
| 92 | /* ---------------------------------------------------- |
| 93 | * The CPU Ops core power down function for Cortex-A72. |
| 94 | * ---------------------------------------------------- |
| 95 | */ |
| 96 | func cortex_a72_core_pwr_dwn |
| 97 | mov x18, x30 |
| 98 | |
| 99 | /* --------------------------------------------- |
| 100 | * Turn off caches. |
| 101 | * --------------------------------------------- |
| 102 | */ |
| 103 | bl cortex_a72_disable_dcache |
| 104 | |
| 105 | /* --------------------------------------------- |
| 106 | * Disable the L2 prefetches. |
| 107 | * --------------------------------------------- |
| 108 | */ |
| 109 | bl cortex_a72_disable_l2_prefetch |
| 110 | |
| 111 | /* --------------------------------------------- |
| 112 | * Disable the load-store hardware prefetcher. |
| 113 | * --------------------------------------------- |
| 114 | */ |
| 115 | bl cortex_a72_disable_hw_prefetcher |
| 116 | |
| 117 | /* --------------------------------------------- |
| 118 | * Flush L1 caches. |
| 119 | * --------------------------------------------- |
| 120 | */ |
| 121 | mov x0, #DCCISW |
| 122 | bl dcsw_op_level1 |
| 123 | |
| 124 | /* --------------------------------------------- |
| 125 | * Come out of intra cluster coherency |
| 126 | * --------------------------------------------- |
| 127 | */ |
| 128 | bl cortex_a72_disable_smp |
| 129 | |
| 130 | /* --------------------------------------------- |
| 131 | * Force the debug interfaces to be quiescent |
| 132 | * --------------------------------------------- |
| 133 | */ |
| 134 | mov x30, x18 |
| 135 | b cortex_a72_disable_ext_debug |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 136 | endfunc cortex_a72_core_pwr_dwn |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 137 | |
| 138 | /* ------------------------------------------------------- |
| 139 | * The CPU Ops cluster power down function for Cortex-A72. |
| 140 | * ------------------------------------------------------- |
| 141 | */ |
| 142 | func cortex_a72_cluster_pwr_dwn |
| 143 | mov x18, x30 |
| 144 | |
| 145 | /* --------------------------------------------- |
| 146 | * Turn off caches. |
| 147 | * --------------------------------------------- |
| 148 | */ |
| 149 | bl cortex_a72_disable_dcache |
| 150 | |
| 151 | /* --------------------------------------------- |
| 152 | * Disable the L2 prefetches. |
| 153 | * --------------------------------------------- |
| 154 | */ |
| 155 | bl cortex_a72_disable_l2_prefetch |
| 156 | |
| 157 | /* --------------------------------------------- |
| 158 | * Disable the load-store hardware prefetcher. |
| 159 | * --------------------------------------------- |
| 160 | */ |
| 161 | bl cortex_a72_disable_hw_prefetcher |
| 162 | |
| 163 | #if !SKIP_A72_L1_FLUSH_PWR_DWN |
| 164 | /* --------------------------------------------- |
| 165 | * Flush L1 caches. |
| 166 | * --------------------------------------------- |
| 167 | */ |
| 168 | mov x0, #DCCISW |
| 169 | bl dcsw_op_level1 |
| 170 | #endif |
| 171 | |
| 172 | /* --------------------------------------------- |
| 173 | * Disable the optional ACP. |
| 174 | * --------------------------------------------- |
| 175 | */ |
| 176 | bl plat_disable_acp |
| 177 | |
| 178 | /* ------------------------------------------------- |
| 179 | * Flush the L2 caches. |
| 180 | * ------------------------------------------------- |
| 181 | */ |
| 182 | mov x0, #DCCISW |
| 183 | bl dcsw_op_level2 |
| 184 | |
| 185 | /* --------------------------------------------- |
| 186 | * Come out of intra cluster coherency |
| 187 | * --------------------------------------------- |
| 188 | */ |
| 189 | bl cortex_a72_disable_smp |
| 190 | |
| 191 | /* --------------------------------------------- |
| 192 | * Force the debug interfaces to be quiescent |
| 193 | * --------------------------------------------- |
| 194 | */ |
| 195 | mov x30, x18 |
| 196 | b cortex_a72_disable_ext_debug |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 197 | endfunc cortex_a72_cluster_pwr_dwn |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 198 | |
| 199 | /* --------------------------------------------- |
| 200 | * This function provides cortex_a72 specific |
| 201 | * register information for crash reporting. |
| 202 | * It needs to return with x6 pointing to |
| 203 | * a list of register names in ascii and |
| 204 | * x8 - x15 having values of registers to be |
| 205 | * reported. |
| 206 | * --------------------------------------------- |
| 207 | */ |
| 208 | .section .rodata.cortex_a72_regs, "aS" |
| 209 | cortex_a72_regs: /* The ascii list of register names to be reported */ |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 210 | .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 211 | |
| 212 | func cortex_a72_cpu_reg_dump |
| 213 | adr x6, cortex_a72_regs |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 214 | mrs x8, CORTEX_A72_ECTLR_EL1 |
| 215 | mrs x9, CORTEX_A72_MERRSR_EL1 |
| 216 | mrs x10, CORTEX_A72_L2MERRSR_EL1 |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 217 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 218 | endfunc cortex_a72_cpu_reg_dump |
Vikram Kanigiri | c47e011 | 2015-02-17 11:50:28 +0000 | [diff] [blame] | 219 | |
| 220 | |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 221 | declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \ |
| 222 | cortex_a72_reset_func, \ |
| 223 | cortex_a72_core_pwr_dwn, \ |
| 224 | cortex_a72_cluster_pwr_dwn |