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Paul Beesleyf3653a62019-05-22 11:22:44 +01001Xilinx Zynq UltraScale+ MPSoC
2=============================
Douglas Raillardd7c21b72017-06-28 15:23:03 +01003
Dan Handley610e7e12018-03-01 18:44:00 +00004Trusted Firmware-A (TF-A) implements the EL3 firmware layer for Xilinx Zynq
Douglas Raillardd7c21b72017-06-28 15:23:03 +01005UltraScale + MPSoC.
Dan Handley610e7e12018-03-01 18:44:00 +00006The platform only uses the runtime part of TF-A as ZynqMP already has a
Douglas Raillardd7c21b72017-06-28 15:23:03 +01007BootROM (BL1) and FSBL (BL2).
8
Dan Handley610e7e12018-03-01 18:44:00 +00009BL31 is TF-A.
Douglas Raillardd7c21b72017-06-28 15:23:03 +010010BL32 is an optional Secure Payload.
11BL33 is the non-secure world software (U-Boot, Linux etc).
12
13To build:
14
15.. code:: bash
16
Venkatesh Yadav Abbarapu476336b2022-04-11 09:13:17 +053017 make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 bl31
Douglas Raillardd7c21b72017-06-28 15:23:03 +010018
19To build bl32 TSP you have to rebuild bl31 too:
20
21.. code:: bash
22
Venkatesh Yadav Abbarapu476336b2022-04-11 09:13:17 +053023 make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd RESET_TO_BL31=1 bl31 bl32
Douglas Raillardd7c21b72017-06-28 15:23:03 +010024
Venkatesh Yadav Abbarapu34fbf1f2020-11-27 04:45:01 -070025To build TF-A for JTAG DCC console:
26
27.. code:: bash
28
29 make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 bl31 ZYNQMP_CONSOLE=dcc
30
Douglas Raillardd7c21b72017-06-28 15:23:03 +010031ZynqMP platform specific build options
Paul Beesleyf3653a62019-05-22 11:22:44 +010032--------------------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +010033
34- ``ZYNQMP_ATF_MEM_BASE``: Specifies the base address of the bl31 binary.
35- ``ZYNQMP_ATF_MEM_SIZE``: Specifies the size of the memory region of the bl31 binary.
36- ``ZYNQMP_BL32_MEM_BASE``: Specifies the base address of the bl32 binary.
37- ``ZYNQMP_BL32_MEM_SIZE``: Specifies the size of the memory region of the bl32 binary.
38
39- ``ZYNQMP_CONSOLE``: Select the console driver. Options:
40
41 - ``cadence``, ``cadence0``: Cadence UART 0
42 - ``cadence1`` : Cadence UART 1
43
Akshay Belsare69c6a592023-02-15 10:49:52 +053044ZynqMP Debug behavior
45---------------------
46
47With DEBUG=1, TF-A for ZynqMP uses DDR memory range instead of OCM memory range
48due to size constraints.
49For DEBUG=1 configuration for ZynqMP the BL31_BASE is set to the DDR location
50of 0x1000 and BL31_LIMIT is set to DDR location of 0x7FFFF.
51
52If the user wants to move the bl31 to a different DDR location, user can provide
53the DDR address location in the build command as follows,
54
55make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 DEBUG=1 \
56 ZYNQMP_ATF_MEM_BASE=<DDR address> ZYNQMP_ATF_MEM_SIZE=<size> bl31
57
58
Dan Handley610e7e12018-03-01 18:44:00 +000059FSBL->TF-A Parameter Passing
Paul Beesleyf3653a62019-05-22 11:22:44 +010060----------------------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +010061
Dan Handley610e7e12018-03-01 18:44:00 +000062The FSBL populates a data structure with image information for TF-A. TF-A uses
63that data to hand off to the loaded images. The address of the handoff data
Douglas Raillardd7c21b72017-06-28 15:23:03 +010064structure is passed in the ``PMU_GLOBAL.GLOBAL_GEN_STORAGE6`` register. The
Dan Handley610e7e12018-03-01 18:44:00 +000065register is free to be used by other software once TF-A has brought up
Douglas Raillardd7c21b72017-06-28 15:23:03 +010066further firmware images.
67
68Power Domain Tree
Paul Beesleyf3653a62019-05-22 11:22:44 +010069-----------------
Douglas Raillardd7c21b72017-06-28 15:23:03 +010070
Dan Handley610e7e12018-03-01 18:44:00 +000071The following power domain tree represents the power domain model used by TF-A
72for ZynqMP:
Douglas Raillardd7c21b72017-06-28 15:23:03 +010073
74::
75
76 +-+
77 |0|
78 +-+
79 +-------+---+---+-------+
80 | | | |
81 | | | |
82 v v v v
83 +-+ +-+ +-+ +-+
84 |0| |1| |2| |3|
85 +-+ +-+ +-+ +-+
86
87The 4 leaf power domains represent the individual A53 cores, while resources
88common to the cluster are grouped in the power domain on the top.
Amit Nagalf7ecba32023-02-15 18:43:55 +053089
90CUSTOM SIP service support
91--------------------------
92
93- Dedicated SMC FID ZYNQMP_SIP_SVC_CUSTOM(0x82002000)(32-bit)/
94 (0xC2002000)(64-bit) to be used by a custom package for
95 providing CUSTOM SIP service.
96
97- by default platform provides bare minimum definition for
98 custom_smc_handler in this service.
99
100- to use this service, custom package should implement their
101 smc handler with the name custom_smc_handler. once custom package is
102 included in TF-A build, their definition of custom_smc_handler is
103 enabled.
104
105Custom package makefile fragment inclusion in TF-A build
106--------------------------------------------------------
107
108- custom package is not directly part of TF-A source.
109
110- <CUSTOM_PKG_PATH> is the location at which user clones a
111 custom package locally.
112
113- custom package needs to implement makefile fragment named
114 custom_pkg.mk so as to get included in TF-A build.
115
116- custom_pkg.mk specify all the rules to include custom package
117 specific header files, dependent libs, source files that are
118 supposed to be included in TF-A build.
119
120- when <CUSTOM_PKG_PATH> is specified in TF-A build command,
121 custom_pkg.mk is included from <CUSTOM_PKG_PATH> in TF-A build.
122
123- TF-A build command:
124 make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1
125 bl31 CUSTOM_PKG_PATH=<...>