Paul Beesley | f3653a6 | 2019-05-22 11:22:44 +0100 | [diff] [blame] | 1 | Xilinx Zynq UltraScale+ MPSoC |
| 2 | ============================= |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 3 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 4 | Trusted Firmware-A (TF-A) implements the EL3 firmware layer for Xilinx Zynq |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 5 | UltraScale + MPSoC. |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 6 | The platform only uses the runtime part of TF-A as ZynqMP already has a |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 7 | BootROM (BL1) and FSBL (BL2). |
| 8 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 9 | BL31 is TF-A. |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 10 | BL32 is an optional Secure Payload. |
| 11 | BL33 is the non-secure world software (U-Boot, Linux etc). |
| 12 | |
| 13 | To build: |
| 14 | |
| 15 | .. code:: bash |
| 16 | |
Venkatesh Yadav Abbarapu | 476336b | 2022-04-11 09:13:17 +0530 | [diff] [blame] | 17 | make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 bl31 |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 18 | |
| 19 | To build bl32 TSP you have to rebuild bl31 too: |
| 20 | |
| 21 | .. code:: bash |
| 22 | |
Venkatesh Yadav Abbarapu | 476336b | 2022-04-11 09:13:17 +0530 | [diff] [blame] | 23 | make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp SPD=tspd RESET_TO_BL31=1 bl31 bl32 |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 24 | |
Venkatesh Yadav Abbarapu | 34fbf1f | 2020-11-27 04:45:01 -0700 | [diff] [blame] | 25 | To build TF-A for JTAG DCC console: |
| 26 | |
| 27 | .. code:: bash |
| 28 | |
| 29 | make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 bl31 ZYNQMP_CONSOLE=dcc |
| 30 | |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 31 | ZynqMP platform specific build options |
Paul Beesley | f3653a6 | 2019-05-22 11:22:44 +0100 | [diff] [blame] | 32 | -------------------------------------- |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 33 | |
| 34 | - ``ZYNQMP_ATF_MEM_BASE``: Specifies the base address of the bl31 binary. |
| 35 | - ``ZYNQMP_ATF_MEM_SIZE``: Specifies the size of the memory region of the bl31 binary. |
| 36 | - ``ZYNQMP_BL32_MEM_BASE``: Specifies the base address of the bl32 binary. |
| 37 | - ``ZYNQMP_BL32_MEM_SIZE``: Specifies the size of the memory region of the bl32 binary. |
| 38 | |
| 39 | - ``ZYNQMP_CONSOLE``: Select the console driver. Options: |
| 40 | |
| 41 | - ``cadence``, ``cadence0``: Cadence UART 0 |
| 42 | - ``cadence1`` : Cadence UART 1 |
| 43 | |
Akshay Belsare | 69c6a59 | 2023-02-15 10:49:52 +0530 | [diff] [blame] | 44 | ZynqMP Debug behavior |
| 45 | --------------------- |
| 46 | |
| 47 | With DEBUG=1, TF-A for ZynqMP uses DDR memory range instead of OCM memory range |
| 48 | due to size constraints. |
| 49 | For DEBUG=1 configuration for ZynqMP the BL31_BASE is set to the DDR location |
| 50 | of 0x1000 and BL31_LIMIT is set to DDR location of 0x7FFFF. |
| 51 | |
| 52 | If the user wants to move the bl31 to a different DDR location, user can provide |
| 53 | the DDR address location in the build command as follows, |
| 54 | |
| 55 | make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 DEBUG=1 \ |
| 56 | ZYNQMP_ATF_MEM_BASE=<DDR address> ZYNQMP_ATF_MEM_SIZE=<size> bl31 |
| 57 | |
| 58 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 59 | FSBL->TF-A Parameter Passing |
Paul Beesley | f3653a6 | 2019-05-22 11:22:44 +0100 | [diff] [blame] | 60 | ---------------------------- |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 61 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 62 | The FSBL populates a data structure with image information for TF-A. TF-A uses |
| 63 | that data to hand off to the loaded images. The address of the handoff data |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 64 | structure is passed in the ``PMU_GLOBAL.GLOBAL_GEN_STORAGE6`` register. The |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 65 | register is free to be used by other software once TF-A has brought up |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 66 | further firmware images. |
| 67 | |
| 68 | Power Domain Tree |
Paul Beesley | f3653a6 | 2019-05-22 11:22:44 +0100 | [diff] [blame] | 69 | ----------------- |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 70 | |
Dan Handley | 610e7e1 | 2018-03-01 18:44:00 +0000 | [diff] [blame] | 71 | The following power domain tree represents the power domain model used by TF-A |
| 72 | for ZynqMP: |
Douglas Raillard | d7c21b7 | 2017-06-28 15:23:03 +0100 | [diff] [blame] | 73 | |
| 74 | :: |
| 75 | |
| 76 | +-+ |
| 77 | |0| |
| 78 | +-+ |
| 79 | +-------+---+---+-------+ |
| 80 | | | | | |
| 81 | | | | | |
| 82 | v v v v |
| 83 | +-+ +-+ +-+ +-+ |
| 84 | |0| |1| |2| |3| |
| 85 | +-+ +-+ +-+ +-+ |
| 86 | |
| 87 | The 4 leaf power domains represent the individual A53 cores, while resources |
| 88 | common to the cluster are grouped in the power domain on the top. |
Amit Nagal | f7ecba3 | 2023-02-15 18:43:55 +0530 | [diff] [blame] | 89 | |
| 90 | CUSTOM SIP service support |
| 91 | -------------------------- |
| 92 | |
| 93 | - Dedicated SMC FID ZYNQMP_SIP_SVC_CUSTOM(0x82002000)(32-bit)/ |
| 94 | (0xC2002000)(64-bit) to be used by a custom package for |
| 95 | providing CUSTOM SIP service. |
| 96 | |
| 97 | - by default platform provides bare minimum definition for |
| 98 | custom_smc_handler in this service. |
| 99 | |
| 100 | - to use this service, custom package should implement their |
| 101 | smc handler with the name custom_smc_handler. once custom package is |
| 102 | included in TF-A build, their definition of custom_smc_handler is |
| 103 | enabled. |
| 104 | |
| 105 | Custom package makefile fragment inclusion in TF-A build |
| 106 | -------------------------------------------------------- |
| 107 | |
| 108 | - custom package is not directly part of TF-A source. |
| 109 | |
| 110 | - <CUSTOM_PKG_PATH> is the location at which user clones a |
| 111 | custom package locally. |
| 112 | |
| 113 | - custom package needs to implement makefile fragment named |
| 114 | custom_pkg.mk so as to get included in TF-A build. |
| 115 | |
| 116 | - custom_pkg.mk specify all the rules to include custom package |
| 117 | specific header files, dependent libs, source files that are |
| 118 | supposed to be included in TF-A build. |
| 119 | |
| 120 | - when <CUSTOM_PKG_PATH> is specified in TF-A build command, |
| 121 | custom_pkg.mk is included from <CUSTOM_PKG_PATH> in TF-A build. |
| 122 | |
| 123 | - TF-A build command: |
| 124 | make CROSS_COMPILE=aarch64-none-elf- PLAT=zynqmp RESET_TO_BL31=1 |
| 125 | bl31 CUSTOM_PKG_PATH=<...> |