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git01.mediatek.com / filogic / atf / bc0fddec2b7cd5164bc49e767f041b93aef6d8a9 / . / plat / nvidia / tegra / include / t132 / tegra_def.h
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Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]1/*
Steven Kao0cb8b332018-02-09 20:50:02 +0800[diff] [blame]2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Varun Wadekar1b0c1242018-05-15 11:24:59 -0700[diff] [blame]3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]4 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]5 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]6 */
7
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]8#ifndef TEGRA_DEF_H
9#define TEGRA_DEF_H
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]10
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]11#include <lib/utils_def.h>
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]12
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]13/*******************************************************************************
14 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
15 * call as the `state-id` field in the 'power state' parameter.
16 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]17#define PSTATE_ID_SOC_POWERDN U(0xD)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]18
19/*******************************************************************************
Varun Wadekar3ce54992016-01-19 13:55:19 -0800[diff] [blame]20 * Platform power states (used by PSCI framework)
21 *
22 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
23 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
24 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]25#define PLAT_MAX_RET_STATE U(1)
26#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
Varun Wadekar3ce54992016-01-19 13:55:19 -0800[diff] [blame]27
28/*******************************************************************************
Steven Kao0cb8b332018-02-09 20:50:02 +0800[diff] [blame]29 * Chip specific page table and MMU setup constants
30 ******************************************************************************/
31#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
32#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
33
34/*******************************************************************************
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]35 * GIC memory map
36 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]37#define TEGRA_GICD_BASE U(0x50041000)
38#define TEGRA_GICC_BASE U(0x50042000)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]39
40/*******************************************************************************
41 * Tegra micro-seconds timer constants
42 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]43#define TEGRA_TMRUS_BASE U(0x60005010)
44#define TEGRA_TMRUS_SIZE U(0x1000)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]45
46/*******************************************************************************
47 * Tegra Clock and Reset Controller constants
48 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]49#define TEGRA_CAR_RESET_BASE U(0x60006000)
Varun Wadekara59a7c52017-04-26 08:31:50 -0700[diff] [blame]50#define TEGRA_GPU_RESET_REG_OFFSET U(0x28C)
Jeetesh Burman48fef882018-01-22 15:40:08 +0530[diff] [blame]51#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290)
Varun Wadekara59a7c52017-04-26 08:31:50 -0700[diff] [blame]52#define GPU_RESET_BIT (U(1) << 24)
Jeetesh Burman48fef882018-01-22 15:40:08 +0530[diff] [blame]53#define GPU_SET_BIT (U(1) << 24)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]54
55/*******************************************************************************
56 * Tegra Flow Controller constants
57 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]58#define TEGRA_FLOWCTRL_BASE U(0x60007000)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]59
60/*******************************************************************************
61 * Tegra Secure Boot Controller constants
62 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]63#define TEGRA_SB_BASE U(0x6000C200)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]64
65/*******************************************************************************
66 * Tegra Exception Vectors constants
67 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]68#define TEGRA_EVP_BASE U(0x6000F000)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]69
70/*******************************************************************************
Varun Wadekar28dcc212016-07-20 10:28:51 -0700[diff] [blame]71 * Tegra Miscellaneous register constants
72 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]73#define TEGRA_MISC_BASE U(0x70000000)
74#define HARDWARE_REVISION_OFFSET U(0x804)
Varun Wadekar28dcc212016-07-20 10:28:51 -0700[diff] [blame]75
76/*******************************************************************************
Varun Wadekard2014c62015-10-29 10:37:28 +0530[diff] [blame]77 * Tegra UART controller base addresses
78 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]79#define TEGRA_UARTA_BASE U(0x70006000)
80#define TEGRA_UARTB_BASE U(0x70006040)
81#define TEGRA_UARTC_BASE U(0x70006200)
82#define TEGRA_UARTD_BASE U(0x70006300)
83#define TEGRA_UARTE_BASE U(0x70006400)
Varun Wadekard2014c62015-10-29 10:37:28 +0530[diff] [blame]84
85/*******************************************************************************
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]86 * Tegra Power Mgmt Controller constants
87 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]88#define TEGRA_PMC_BASE U(0x7000E400)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]89
90/*******************************************************************************
91 * Tegra Memory Controller constants
92 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]93#define TEGRA_MC_BASE U(0x70019000)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]94
Harvey Hsieh359be952017-08-21 15:01:53 +0800[diff] [blame]95/* Memory Controller Interrupt Status */
96#define MC_INTSTATUS 0x00U
97
Varun Wadekar64443ca2016-12-12 16:14:57 -0800[diff] [blame]98/* TZDRAM carveout configuration registers */
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]99#define MC_SECURITY_CFG0_0 U(0x70)
100#define MC_SECURITY_CFG1_0 U(0x74)
101#define MC_SECURITY_CFG3_0 U(0x9BC)
Varun Wadekar64443ca2016-12-12 16:14:57 -0800[diff] [blame]102
103/* Video Memory carveout configuration registers */
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]104#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
105#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
106#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
Varun Wadekar64443ca2016-12-12 16:14:57 -0800[diff] [blame]107
Varun Wadekar0dc91812015-12-30 15:06:41 -0800[diff] [blame]108/*******************************************************************************
109 * Tegra TZRAM constants
110 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]111#define TEGRA_TZRAM_BASE U(0x7C010000)
112#define TEGRA_TZRAM_SIZE U(0x10000)
Varun Wadekar0dc91812015-12-30 15:06:41 -0800[diff] [blame]113
Varun Wadekar1b0c1242018-05-15 11:24:59 -0700[diff] [blame]114/*******************************************************************************
115 * Tegra DRAM memory base address
116 ******************************************************************************/
117#define TEGRA_DRAM_BASE ULL(0x80000000)
118#define TEGRA_DRAM_END ULL(0x27FFFFFFF)
119
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]120#endif /* TEGRA_DEF_H */