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git01.mediatek.com / filogic / atf / 28dcc21d9663b1fa63539d3b30309b44c86c4630 / . / plat / nvidia / tegra / include / t132 / tegra_def.h
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Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]1/*
Varun Wadekar0dc91812015-12-30 15:06:41 -0800[diff] [blame]2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __TEGRA_DEF_H__
32#define __TEGRA_DEF_H__
33
34#include <platform_def.h>
35
36/*******************************************************************************
37 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
38 * call as the `state-id` field in the 'power state' parameter.
39 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530[diff] [blame]40#define PSTATE_ID_SOC_POWERDN 0xD
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]41
42/*******************************************************************************
Varun Wadekar3ce54992016-01-19 13:55:19 -0800[diff] [blame]43 * Platform power states (used by PSCI framework)
44 *
45 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
46 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
47 ******************************************************************************/
48#define PLAT_MAX_RET_STATE 1
49#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1)
50
51/*******************************************************************************
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]52 * GIC memory map
53 ******************************************************************************/
54#define TEGRA_GICD_BASE 0x50041000
55#define TEGRA_GICC_BASE 0x50042000
56
57/*******************************************************************************
58 * Tegra micro-seconds timer constants
59 ******************************************************************************/
60#define TEGRA_TMRUS_BASE 0x60005010
61
62/*******************************************************************************
63 * Tegra Clock and Reset Controller constants
64 ******************************************************************************/
65#define TEGRA_CAR_RESET_BASE 0x60006000
66
67/*******************************************************************************
68 * Tegra Flow Controller constants
69 ******************************************************************************/
70#define TEGRA_FLOWCTRL_BASE 0x60007000
71
72/*******************************************************************************
73 * Tegra Secure Boot Controller constants
74 ******************************************************************************/
75#define TEGRA_SB_BASE 0x6000C200
76
77/*******************************************************************************
78 * Tegra Exception Vectors constants
79 ******************************************************************************/
80#define TEGRA_EVP_BASE 0x6000F000
81
82/*******************************************************************************
Varun Wadekar28dcc212016-07-20 10:28:51 -0700[diff] [blame^]83 * Tegra Miscellaneous register constants
84 ******************************************************************************/
85#define TEGRA_MISC_BASE 0x70000000
86#define HARDWARE_REVISION_OFFSET 0x804
87
88/*******************************************************************************
Varun Wadekard2014c62015-10-29 10:37:28 +0530[diff] [blame]89 * Tegra UART controller base addresses
90 ******************************************************************************/
91#define TEGRA_UARTA_BASE 0x70006000
92#define TEGRA_UARTB_BASE 0x70006040
93#define TEGRA_UARTC_BASE 0x70006200
94#define TEGRA_UARTD_BASE 0x70006300
95#define TEGRA_UARTE_BASE 0x70006400
96
97/*******************************************************************************
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]98 * Tegra Power Mgmt Controller constants
99 ******************************************************************************/
100#define TEGRA_PMC_BASE 0x7000E400
101
102/*******************************************************************************
103 * Tegra Memory Controller constants
104 ******************************************************************************/
105#define TEGRA_MC_BASE 0x70019000
106
Varun Wadekar0dc91812015-12-30 15:06:41 -0800[diff] [blame]107/*******************************************************************************
108 * Tegra TZRAM constants
109 ******************************************************************************/
110#define TEGRA_TZRAM_BASE 0x7C010000
111#define TEGRA_TZRAM_SIZE 0x10000
112
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]113#endif /* __TEGRA_DEF_H__ */