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git01.mediatek.com / filogic / atf / 48fef88ef977592deffd6fe53154190c75f98cc9 / . / plat / nvidia / tegra / include / t132 / tegra_def.h
blob: 2fe321b223887c74bdadcb54481318b568a0010a [file] [log] [blame]
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]1/*
Steven Kao4d160ac2016-12-23 16:05:13 +0800[diff] [blame]2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]7#ifndef TEGRA_DEF_H
8#define TEGRA_DEF_H
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]10#include <lib/utils_def.h>
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]11
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]12/*******************************************************************************
13 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
14 * call as the `state-id` field in the 'power state' parameter.
15 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]16#define PSTATE_ID_SOC_POWERDN U(0xD)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]17
18/*******************************************************************************
Varun Wadekar3ce54992016-01-19 13:55:19 -0800[diff] [blame]19 * Platform power states (used by PSCI framework)
20 *
21 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
22 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
23 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]24#define PLAT_MAX_RET_STATE U(1)
25#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
Varun Wadekar3ce54992016-01-19 13:55:19 -0800[diff] [blame]26
27/*******************************************************************************
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]28 * GIC memory map
29 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]30#define TEGRA_GICD_BASE U(0x50041000)
31#define TEGRA_GICC_BASE U(0x50042000)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]32
33/*******************************************************************************
34 * Tegra micro-seconds timer constants
35 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]36#define TEGRA_TMRUS_BASE U(0x60005010)
37#define TEGRA_TMRUS_SIZE U(0x1000)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]38
39/*******************************************************************************
40 * Tegra Clock and Reset Controller constants
41 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]42#define TEGRA_CAR_RESET_BASE U(0x60006000)
Varun Wadekara59a7c52017-04-26 08:31:50 -0700[diff] [blame]43#define TEGRA_GPU_RESET_REG_OFFSET U(0x28C)
Jeetesh Burman48fef882018-01-22 15:40:08 +0530[diff] [blame^]44#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290)
Varun Wadekara59a7c52017-04-26 08:31:50 -0700[diff] [blame]45#define GPU_RESET_BIT (U(1) << 24)
Jeetesh Burman48fef882018-01-22 15:40:08 +0530[diff] [blame^]46#define GPU_SET_BIT (U(1) << 24)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]47
48/*******************************************************************************
49 * Tegra Flow Controller constants
50 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]51#define TEGRA_FLOWCTRL_BASE U(0x60007000)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]52
53/*******************************************************************************
54 * Tegra Secure Boot Controller constants
55 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]56#define TEGRA_SB_BASE U(0x6000C200)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]57
58/*******************************************************************************
59 * Tegra Exception Vectors constants
60 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]61#define TEGRA_EVP_BASE U(0x6000F000)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]62
63/*******************************************************************************
Varun Wadekar28dcc212016-07-20 10:28:51 -0700[diff] [blame]64 * Tegra Miscellaneous register constants
65 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]66#define TEGRA_MISC_BASE U(0x70000000)
67#define HARDWARE_REVISION_OFFSET U(0x804)
Varun Wadekar28dcc212016-07-20 10:28:51 -0700[diff] [blame]68
69/*******************************************************************************
Varun Wadekard2014c62015-10-29 10:37:28 +0530[diff] [blame]70 * Tegra UART controller base addresses
71 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]72#define TEGRA_UARTA_BASE U(0x70006000)
73#define TEGRA_UARTB_BASE U(0x70006040)
74#define TEGRA_UARTC_BASE U(0x70006200)
75#define TEGRA_UARTD_BASE U(0x70006300)
76#define TEGRA_UARTE_BASE U(0x70006400)
Varun Wadekard2014c62015-10-29 10:37:28 +0530[diff] [blame]77
78/*******************************************************************************
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]79 * Tegra Power Mgmt Controller constants
80 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]81#define TEGRA_PMC_BASE U(0x7000E400)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]82
83/*******************************************************************************
84 * Tegra Memory Controller constants
85 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]86#define TEGRA_MC_BASE U(0x70019000)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]87
Harvey Hsieh359be952017-08-21 15:01:53 +0800[diff] [blame]88/* Memory Controller Interrupt Status */
89#define MC_INTSTATUS 0x00U
90
Varun Wadekar64443ca2016-12-12 16:14:57 -0800[diff] [blame]91/* TZDRAM carveout configuration registers */
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]92#define MC_SECURITY_CFG0_0 U(0x70)
93#define MC_SECURITY_CFG1_0 U(0x74)
94#define MC_SECURITY_CFG3_0 U(0x9BC)
Varun Wadekar64443ca2016-12-12 16:14:57 -0800[diff] [blame]95
96/* Video Memory carveout configuration registers */
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]97#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
98#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
99#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
Varun Wadekar64443ca2016-12-12 16:14:57 -0800[diff] [blame]100
Varun Wadekar0dc91812015-12-30 15:06:41 -0800[diff] [blame]101/*******************************************************************************
102 * Tegra TZRAM constants
103 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]104#define TEGRA_TZRAM_BASE U(0x7C010000)
105#define TEGRA_TZRAM_SIZE U(0x10000)
Varun Wadekar0dc91812015-12-30 15:06:41 -0800[diff] [blame]106
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]107#endif /* TEGRA_DEF_H */