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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +01002 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Dan Handley2b6b5742015-03-19 19:17:53 +00007#include <arm_config.h>
8#include <arm_def.h>
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +01009#include <assert.h>
10#include <cci.h>
Soby Mathew7356b1e2016-03-24 10:12:42 +000011#include <ccn.h>
Dan Handley714a0d22014-04-09 13:13:04 +010012#include <debug.h>
Achin Gupta1fa7eb62015-11-03 14:18:34 +000013#include <gicv2.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010014#include <mmio.h>
Dan Handley2b6b5742015-03-19 19:17:53 +000015#include <plat_arm.h>
16#include <v2m_def.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010017#include "../fvp_def.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010018
Achin Gupta1fa7eb62015-11-03 14:18:34 +000019/* Defines for GIC Driver build time selection */
20#define FVP_GICV2 1
21#define FVP_GICV3 2
22#define FVP_GICV3_LEGACY 3
23
Achin Gupta4f6ad662013-10-25 09:08:21 +010024/*******************************************************************************
Dan Handley2b6b5742015-03-19 19:17:53 +000025 * arm_config holds the characteristics of the differences between the three FVP
26 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
Vikram Kanigirifbb13012016-02-15 11:54:14 +000027 * at each boot stage by the primary before enabling the MMU (to allow
28 * interconnect configuration) & used thereafter. Each BL will have its own copy
29 * to allow independent operation.
Achin Gupta4f6ad662013-10-25 09:08:21 +010030 ******************************************************************************/
Dan Handley2b6b5742015-03-19 19:17:53 +000031arm_config_t arm_config;
Soby Mathewb08bc042014-09-03 17:48:44 +010032
33#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
34 DEVICE0_SIZE, \
35 MT_DEVICE | MT_RW | MT_SECURE)
36
37#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
38 DEVICE1_SIZE, \
39 MT_DEVICE | MT_RW | MT_SECURE)
40
Sandrine Bailleuxd9160a52017-05-26 15:48:10 +010041/*
42 * Need to be mapped with write permissions in order to set a new non-volatile
43 * counter value.
44 */
Juan Castillo31a68f02015-04-14 12:49:03 +010045#define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \
46 DEVICE2_SIZE, \
Antonio Nino Diaz9d602fe2016-05-20 14:14:16 +010047 MT_DEVICE | MT_RW | MT_SECURE)
Juan Castillo31a68f02015-04-14 12:49:03 +010048
49
Jon Medhurstb1eb0932014-02-26 16:27:53 +000050/*
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010051 * Table of memory regions for various BL stages to map using the MMU.
52 * This doesn't include Trusted SRAM as arm_setup_page_tables() already
53 * takes care of mapping it.
Sandrine Bailleux889ca032016-06-14 17:01:00 +010054 *
55 * The flash needs to be mapped as writable in order to erase the FIP's Table of
56 * Contents in case of unrecoverable error (see plat_error_handler()).
Jon Medhurstb1eb0932014-02-26 16:27:53 +000057 */
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090058#ifdef IMAGE_BL1
Dan Handley2b6b5742015-03-19 19:17:53 +000059const mmap_region_t plat_arm_mmap[] = {
60 ARM_MAP_SHARED_RAM,
Juan Castillob6132f12015-10-06 14:01:35 +010061 V2M_MAP_FLASH0_RW,
Dan Handley2b6b5742015-03-19 19:17:53 +000062 V2M_MAP_IOFPGA,
Soby Mathewb08bc042014-09-03 17:48:44 +010063 MAP_DEVICE0,
64 MAP_DEVICE1,
Yatharth Kochar736a3bf2015-10-11 14:14:55 +010065#if TRUSTED_BOARD_BOOT
Sandrine Bailleuxd9160a52017-05-26 15:48:10 +010066 /* To access the Root of Trust Public Key registers. */
67 MAP_DEVICE2,
68 /* Map DRAM to authenticate NS_BL2U image. */
Yatharth Kochar736a3bf2015-10-11 14:14:55 +010069 ARM_MAP_NS_DRAM1,
70#endif
Soby Mathewb08bc042014-09-03 17:48:44 +010071 {0}
72};
73#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090074#ifdef IMAGE_BL2
Dan Handley2b6b5742015-03-19 19:17:53 +000075const mmap_region_t plat_arm_mmap[] = {
76 ARM_MAP_SHARED_RAM,
Juan Castillob6132f12015-10-06 14:01:35 +010077 V2M_MAP_FLASH0_RW,
Dan Handley2b6b5742015-03-19 19:17:53 +000078 V2M_MAP_IOFPGA,
Soby Mathewb08bc042014-09-03 17:48:44 +010079 MAP_DEVICE0,
80 MAP_DEVICE1,
Dan Handley2b6b5742015-03-19 19:17:53 +000081 ARM_MAP_NS_DRAM1,
82 ARM_MAP_TSP_SEC_MEM,
Sandrine Bailleuxd9160a52017-05-26 15:48:10 +010083#if TRUSTED_BOARD_BOOT
84 /* To access the Root of Trust Public Key registers. */
85 MAP_DEVICE2,
86#endif
David Wang0ba499f2016-03-07 11:02:57 +080087#if ARM_BL31_IN_DRAM
88 ARM_MAP_BL31_SEC_DRAM,
89#endif
Jens Wiklander0814c6a2017-08-25 10:07:20 +020090#ifdef SPD_opteed
91 ARM_OPTEE_PAGEABLE_LOAD_MEM,
92#endif
Soby Mathewb08bc042014-09-03 17:48:44 +010093 {0}
94};
95#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090096#ifdef IMAGE_BL2U
Yatharth Kochar3a11eda2015-10-14 15:28:11 +010097const mmap_region_t plat_arm_mmap[] = {
98 MAP_DEVICE0,
99 V2M_MAP_IOFPGA,
100 {0}
101};
102#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900103#ifdef IMAGE_BL31
Dan Handley2b6b5742015-03-19 19:17:53 +0000104const mmap_region_t plat_arm_mmap[] = {
105 ARM_MAP_SHARED_RAM,
106 V2M_MAP_IOFPGA,
Soby Mathewb08bc042014-09-03 17:48:44 +0100107 MAP_DEVICE0,
108 MAP_DEVICE1,
109 {0}
110};
111#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900112#ifdef IMAGE_BL32
Dan Handley2b6b5742015-03-19 19:17:53 +0000113const mmap_region_t plat_arm_mmap[] = {
Soby Mathew0d268dc2016-07-11 14:13:56 +0100114#ifdef AARCH32
115 ARM_MAP_SHARED_RAM,
116#endif
Dan Handley2b6b5742015-03-19 19:17:53 +0000117 V2M_MAP_IOFPGA,
Soby Mathewb08bc042014-09-03 17:48:44 +0100118 MAP_DEVICE0,
119 MAP_DEVICE1,
Jon Medhurstb1eb0932014-02-26 16:27:53 +0000120 {0}
121};
Soby Mathewb08bc042014-09-03 17:48:44 +0100122#endif
Jon Medhurstb1eb0932014-02-26 16:27:53 +0000123
Dan Handley2b6b5742015-03-19 19:17:53 +0000124ARM_CASSERT_MMAP
Soby Mathew13ee9682015-01-22 11:22:22 +0000125
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100126#if FVP_INTERCONNECT_DRIVER != FVP_CCN
127static const int fvp_cci400_map[] = {
128 PLAT_FVP_CCI400_CLUS0_SL_PORT,
129 PLAT_FVP_CCI400_CLUS1_SL_PORT,
130};
131
132static const int fvp_cci5xx_map[] = {
133 PLAT_FVP_CCI5XX_CLUS0_SL_PORT,
134 PLAT_FVP_CCI5XX_CLUS1_SL_PORT,
135};
136
137static unsigned int get_interconnect_master(void)
138{
139 unsigned int master;
140 u_register_t mpidr;
141
142 mpidr = read_mpidr_el1();
143 master = (arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) ?
144 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr);
145
146 assert(master < FVP_CLUSTER_COUNT);
147 return master;
148}
149#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100150
Achin Gupta4f6ad662013-10-25 09:08:21 +0100151/*******************************************************************************
152 * A single boot loader stack is expected to work on both the Foundation FVP
153 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
154 * SYS_ID register provides a mechanism for detecting the differences between
155 * these platforms. This information is stored in a per-BL array to allow the
156 * code to take the correct path.Per BL platform configuration.
157 ******************************************************************************/
Dan Handley2b6b5742015-03-19 19:17:53 +0000158void fvp_config_setup(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100159{
Soby Mathew8e2f2872014-08-14 12:49:05 +0100160 unsigned int rev, hbi, bld, arch, sys_id;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100161
Dan Handley2b6b5742015-03-19 19:17:53 +0000162 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
163 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK;
164 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK;
165 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK;
166 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100167
Andrew Thoelke960347d2014-06-26 14:27:26 +0100168 if (arch != ARCH_MODEL) {
169 ERROR("This firmware is for FVP models\n");
James Morrissey40a6f642014-02-10 14:24:36 +0000170 panic();
Andrew Thoelke960347d2014-06-26 14:27:26 +0100171 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100172
173 /*
174 * The build field in the SYS_ID tells which variant of the GIC
175 * memory is implemented by the model.
176 */
177 switch (bld) {
178 case BLD_GIC_VE_MMAP:
Soby Mathewcf022c52016-01-13 17:06:00 +0000179 ERROR("Legacy Versatile Express memory map for GIC peripheral"
180 " is not supported\n");
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000181 panic();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100182 break;
183 case BLD_GIC_A53A57_MMAP:
Achin Gupta4f6ad662013-10-25 09:08:21 +0100184 break;
185 default:
Andrew Thoelke960347d2014-06-26 14:27:26 +0100186 ERROR("Unsupported board build %x\n", bld);
187 panic();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100188 }
189
190 /*
191 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010
192 * for the Foundation FVP.
193 */
194 switch (hbi) {
Dan Handley2b6b5742015-03-19 19:17:53 +0000195 case HBI_FOUNDATION_FVP:
Dan Handley2b6b5742015-03-19 19:17:53 +0000196 arm_config.flags = 0;
Andrew Thoelke960347d2014-06-26 14:27:26 +0100197
198 /*
199 * Check for supported revisions of Foundation FVP
200 * Allow future revisions to run but emit warning diagnostic
201 */
202 switch (rev) {
Dan Handley2b6b5742015-03-19 19:17:53 +0000203 case REV_FOUNDATION_FVP_V2_0:
204 case REV_FOUNDATION_FVP_V2_1:
205 case REV_FOUNDATION_FVP_v9_1:
Sandrine Bailleux8b33d702016-09-22 09:46:50 +0100206 case REV_FOUNDATION_FVP_v9_6:
Andrew Thoelke960347d2014-06-26 14:27:26 +0100207 break;
208 default:
209 WARN("Unrecognized Foundation FVP revision %x\n", rev);
210 break;
211 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100212 break;
Dan Handley2b6b5742015-03-19 19:17:53 +0000213 case HBI_BASE_FVP:
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100214 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC);
Andrew Thoelke960347d2014-06-26 14:27:26 +0100215
216 /*
217 * Check for supported revisions
218 * Allow future revisions to run but emit warning diagnostic
219 */
220 switch (rev) {
Dan Handley2b6b5742015-03-19 19:17:53 +0000221 case REV_BASE_FVP_V0:
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100222 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400;
223 break;
224 case REV_BASE_FVP_REVC:
Isla Mitchellc7860cf2017-08-17 12:25:34 +0100225 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 |
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100226 ARM_CONFIG_FVP_HAS_CCI5XX);
Andrew Thoelke960347d2014-06-26 14:27:26 +0100227 break;
228 default:
229 WARN("Unrecognized Base FVP revision %x\n", rev);
230 break;
231 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100232 break;
233 default:
Andrew Thoelke960347d2014-06-26 14:27:26 +0100234 ERROR("Unsupported board HBI number 0x%x\n", hbi);
235 panic();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100236 }
Isla Mitchellc7860cf2017-08-17 12:25:34 +0100237
238 /*
239 * We assume that the presence of MT bit, and therefore shifted
240 * affinities, is uniform across the platform: either all CPUs, or no
241 * CPUs implement it.
242 */
243 if (read_mpidr_el1() & MPIDR_MT_MASK)
244 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF;
Sandrine Bailleux3fa98472014-03-31 11:25:18 +0100245}
Vikram Kanigiri96377452014-04-24 11:02:16 +0100246
Vikram Kanigiri4e97e542015-02-26 15:25:58 +0000247
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000248void fvp_interconnect_init(void)
Vikram Kanigiri96377452014-04-24 11:02:16 +0100249{
Soby Mathew7356b1e2016-03-24 10:12:42 +0000250#if FVP_INTERCONNECT_DRIVER == FVP_CCN
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100251 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) {
252 ERROR("Unrecognized CCN variant detected. Only CCN-502"
253 " is supported");
254 panic();
255 }
256
257 plat_arm_interconnect_init();
258#else
259 uintptr_t cci_base = 0;
260 const int *cci_map = 0;
261 unsigned int map_size = 0;
262
263 if (!(arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
264 ARM_CONFIG_FVP_HAS_CCI5XX))) {
265 return;
266 }
267
268 /* Initialize the right interconnect */
269 if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) {
270 cci_base = PLAT_FVP_CCI5XX_BASE;
271 cci_map = fvp_cci5xx_map;
272 map_size = ARRAY_SIZE(fvp_cci5xx_map);
273 } else if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) {
274 cci_base = PLAT_FVP_CCI400_BASE;
275 cci_map = fvp_cci400_map;
276 map_size = ARRAY_SIZE(fvp_cci400_map);
Soby Mathew7356b1e2016-03-24 10:12:42 +0000277 }
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100278
279 assert(cci_base);
280 assert(cci_map);
281 cci_init(cci_base, cci_map, map_size);
282#endif
Dan Handleybe234f92014-08-04 16:11:15 +0100283}
284
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000285void fvp_interconnect_enable(void)
Dan Handleybe234f92014-08-04 16:11:15 +0100286{
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100287#if FVP_INTERCONNECT_DRIVER == FVP_CCN
288 plat_arm_interconnect_enter_coherency();
289#else
290 unsigned int master;
291
292 if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
293 ARM_CONFIG_FVP_HAS_CCI5XX)) {
294 master = get_interconnect_master();
295 cci_enable_snoop_dvm_reqs(master);
296 }
297#endif
Vikram Kanigiri4e97e542015-02-26 15:25:58 +0000298}
299
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000300void fvp_interconnect_disable(void)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +0000301{
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100302#if FVP_INTERCONNECT_DRIVER == FVP_CCN
303 plat_arm_interconnect_exit_coherency();
304#else
305 unsigned int master;
306
307 if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
308 ARM_CONFIG_FVP_HAS_CCI5XX)) {
309 master = get_interconnect_master();
310 cci_disable_snoop_dvm_reqs(master);
311 }
312#endif
Vikram Kanigiri96377452014-04-24 11:02:16 +0100313}