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Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +00001/*
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +00002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +00003 *
David Cunadodedfde52017-05-11 17:30:06 +01004 * SPDX-License-Identifier: BSD-3-Clause
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +00005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <stdbool.h>
8#include <string.h>
9
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +000010#include <arch_helpers.h>
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +000011#include <context.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012#include <lib/el3_runtime/context_mgmt.h>
13#include <lib/psci/psci.h>
14#include <lib/utils.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000015#include <plat/arm/common/arm_sip_svc.h>
16#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +000017#include <smccc_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000018
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +000019/*
20 * Handle SMC from a lower exception level to switch its execution state
21 * (either from AArch64 to AArch32, or vice versa).
22 *
23 * smc_fid:
24 * SMC function ID - either ARM_SIP_SVC_STATE_SWITCH_64 or
25 * ARM_SIP_SVC_STATE_SWITCH_32.
26 * pc_hi, pc_lo:
27 * PC upon re-entry to the calling exception level; width dependent on the
28 * calling exception level.
29 * cookie_hi, cookie_lo:
30 * Opaque pointer pairs received from the caller to pass it back, upon
31 * re-entry.
32 * handle:
33 * Handle to saved context.
34 */
35int arm_execution_state_switch(unsigned int smc_fid,
36 uint32_t pc_hi,
37 uint32_t pc_lo,
38 uint32_t cookie_hi,
39 uint32_t cookie_lo,
40 void *handle)
41{
42 /* Execution state can be switched only if EL3 is AArch64 */
43#ifdef AARCH64
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +010044 bool caller_64, thumb = false, from_el2;
45 unsigned int el, endianness;
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +000046 u_register_t spsr, pc, scr, sctlr;
47 entry_point_info_t ep;
48 cpu_context_t *ctx = (cpu_context_t *) handle;
49 el3_state_t *el3_ctx = get_el3state_ctx(ctx);
50
51 /* That the SMC originated from NS is already validated by the caller */
52
53 /*
54 * Disallow state switch if any of the secondaries have been brought up.
55 */
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +010056 if (psci_secondaries_brought_up() != 0)
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +000057 goto exec_denied;
58
59 spsr = read_ctx_reg(el3_ctx, CTX_SPSR_EL3);
60 caller_64 = (GET_RW(spsr) == MODE_RW_64);
61
62 if (caller_64) {
63 /*
64 * If the call originated from AArch64, expect 32-bit pointers when
65 * switching to AArch32.
66 */
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +010067 if ((pc_hi != 0U) || (cookie_hi != 0U))
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +000068 goto invalid_param;
69
70 pc = pc_lo;
71
72 /* Instruction state when entering AArch32 */
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +010073 thumb = (pc & 1U) != 0U;
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +000074 } else {
75 /* Construct AArch64 PC */
76 pc = (((u_register_t) pc_hi) << 32) | pc_lo;
77 }
78
79 /* Make sure PC is 4-byte aligned, except for Thumb */
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +010080 if (((pc & 0x3U) != 0U) && !thumb)
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +000081 goto invalid_param;
82
83 /*
84 * EL3 controls register width of the immediate lower EL only. Expect
85 * this request from EL2/Hyp unless:
86 *
87 * - EL2 is not implemented;
88 * - EL2 is implemented, but was disabled. This can be inferred from
89 * SCR_EL3.HCE.
90 */
91 from_el2 = caller_64 ? (GET_EL(spsr) == MODE_EL2) :
92 (GET_M32(spsr) == MODE32_hyp);
93 scr = read_ctx_reg(el3_ctx, CTX_SCR_EL3);
94 if (!from_el2) {
95 /* The call is from NS privilege level other than HYP */
96
97 /*
98 * Disallow switching state if there's a Hypervisor in place;
99 * this request must be taken up with the Hypervisor instead.
100 */
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +0100101 if ((scr & SCR_HCE_BIT) != 0U)
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000102 goto exec_denied;
103 }
104
105 /*
106 * Return to the caller using the same endianness. Extract
107 * endianness bit from the respective system control register
108 * directly.
109 */
110 sctlr = from_el2 ? read_sctlr_el2() : read_sctlr_el1();
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +0100111 endianness = ((sctlr & SCTLR_EE_BIT) != 0U) ? 1U : 0U;
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000112
113 /* Construct SPSR for the exception state we're about to switch to */
114 if (caller_64) {
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +0100115 unsigned long long impl;
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000116
117 /*
118 * Switching from AArch64 to AArch32. Ensure this CPU implements
119 * the target EL in AArch32.
120 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000121 impl = from_el2 ? el_implemented(2) : el_implemented(1);
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000122 if (impl != EL_IMPL_A64_A32)
123 goto exec_denied;
124
125 /* Return to the equivalent AArch32 privilege level */
126 el = from_el2 ? MODE32_hyp : MODE32_svc;
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +0100127 spsr = SPSR_MODE32((u_register_t) el,
128 thumb ? SPSR_T_THUMB : SPSR_T_ARM,
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000129 endianness, DISABLE_ALL_EXCEPTIONS);
130 } else {
131 /*
132 * Switching from AArch32 to AArch64. Since it's not possible to
133 * implement an EL as AArch32-only (from which this call was
134 * raised), it's safe to assume AArch64 is also implemented.
135 */
136 el = from_el2 ? MODE_EL2 : MODE_EL1;
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +0100137 spsr = SPSR_64((u_register_t) el, MODE_SP_ELX,
138 DISABLE_ALL_EXCEPTIONS);
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000139 }
140
141 /*
142 * Use the context management library to re-initialize the existing
143 * context with the execution state flipped. Since the library takes
144 * entry_point_info_t pointer as the argument, construct a dummy one
145 * with PC, state width, endianness, security etc. appropriately set.
146 * Other entries in the entry point structure are irrelevant for
147 * purpose.
148 */
149 zeromem(&ep, sizeof(ep));
150 ep.pc = pc;
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +0100151 ep.spsr = (uint32_t) spsr;
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000152 SET_PARAM_HEAD(&ep, PARAM_EP, VERSION_1,
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +0100153 ((unsigned int) ((endianness != 0U) ? EP_EE_BIG :
154 EP_EE_LITTLE)
155 | NON_SECURE | EP_ST_DISABLE));
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000156
157 /*
158 * Re-initialize the system register context, and exit EL3 as if for the
159 * first time. State switch is effectively a soft reset of the
160 * calling EL.
161 */
162 cm_init_my_context(&ep);
163 cm_prepare_el3_exit(NON_SECURE);
164
165 /*
166 * State switch success. The caller of SMC wouldn't see the SMC
167 * returning. Instead, execution starts at the supplied entry point,
168 * with context pointers populated in registers 0 and 1.
169 */
170 SMC_RET2(handle, cookie_hi, cookie_lo);
171
172invalid_param:
173 SMC_RET1(handle, STATE_SW_E_PARAM);
174
175exec_denied:
176#endif
177 /* State switch denied */
178 SMC_RET1(handle, STATE_SW_E_DENIED);
179}