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Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +00001/*
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +00002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +00003 *
David Cunadodedfde52017-05-11 17:30:06 +01004 * SPDX-License-Identifier: BSD-3-Clause
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +00005 */
6
7#include <arch_helpers.h>
8#include <arm_sip_svc.h>
9#include <context.h>
10#include <context_mgmt.h>
11#include <plat_arm.h>
12#include <psci.h>
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +000013#include <smccc_helpers.h>
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +010014#include <stdbool.h>
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +000015#include <string.h>
16#include <utils.h>
17
18/*
19 * Handle SMC from a lower exception level to switch its execution state
20 * (either from AArch64 to AArch32, or vice versa).
21 *
22 * smc_fid:
23 * SMC function ID - either ARM_SIP_SVC_STATE_SWITCH_64 or
24 * ARM_SIP_SVC_STATE_SWITCH_32.
25 * pc_hi, pc_lo:
26 * PC upon re-entry to the calling exception level; width dependent on the
27 * calling exception level.
28 * cookie_hi, cookie_lo:
29 * Opaque pointer pairs received from the caller to pass it back, upon
30 * re-entry.
31 * handle:
32 * Handle to saved context.
33 */
34int arm_execution_state_switch(unsigned int smc_fid,
35 uint32_t pc_hi,
36 uint32_t pc_lo,
37 uint32_t cookie_hi,
38 uint32_t cookie_lo,
39 void *handle)
40{
41 /* Execution state can be switched only if EL3 is AArch64 */
42#ifdef AARCH64
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +010043 bool caller_64, thumb = false, from_el2;
44 unsigned int el, endianness;
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +000045 u_register_t spsr, pc, scr, sctlr;
46 entry_point_info_t ep;
47 cpu_context_t *ctx = (cpu_context_t *) handle;
48 el3_state_t *el3_ctx = get_el3state_ctx(ctx);
49
50 /* That the SMC originated from NS is already validated by the caller */
51
52 /*
53 * Disallow state switch if any of the secondaries have been brought up.
54 */
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +010055 if (psci_secondaries_brought_up() != 0)
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +000056 goto exec_denied;
57
58 spsr = read_ctx_reg(el3_ctx, CTX_SPSR_EL3);
59 caller_64 = (GET_RW(spsr) == MODE_RW_64);
60
61 if (caller_64) {
62 /*
63 * If the call originated from AArch64, expect 32-bit pointers when
64 * switching to AArch32.
65 */
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +010066 if ((pc_hi != 0U) || (cookie_hi != 0U))
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +000067 goto invalid_param;
68
69 pc = pc_lo;
70
71 /* Instruction state when entering AArch32 */
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +010072 thumb = (pc & 1U) != 0U;
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +000073 } else {
74 /* Construct AArch64 PC */
75 pc = (((u_register_t) pc_hi) << 32) | pc_lo;
76 }
77
78 /* Make sure PC is 4-byte aligned, except for Thumb */
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +010079 if (((pc & 0x3U) != 0U) && !thumb)
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +000080 goto invalid_param;
81
82 /*
83 * EL3 controls register width of the immediate lower EL only. Expect
84 * this request from EL2/Hyp unless:
85 *
86 * - EL2 is not implemented;
87 * - EL2 is implemented, but was disabled. This can be inferred from
88 * SCR_EL3.HCE.
89 */
90 from_el2 = caller_64 ? (GET_EL(spsr) == MODE_EL2) :
91 (GET_M32(spsr) == MODE32_hyp);
92 scr = read_ctx_reg(el3_ctx, CTX_SCR_EL3);
93 if (!from_el2) {
94 /* The call is from NS privilege level other than HYP */
95
96 /*
97 * Disallow switching state if there's a Hypervisor in place;
98 * this request must be taken up with the Hypervisor instead.
99 */
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +0100100 if ((scr & SCR_HCE_BIT) != 0U)
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000101 goto exec_denied;
102 }
103
104 /*
105 * Return to the caller using the same endianness. Extract
106 * endianness bit from the respective system control register
107 * directly.
108 */
109 sctlr = from_el2 ? read_sctlr_el2() : read_sctlr_el1();
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +0100110 endianness = ((sctlr & SCTLR_EE_BIT) != 0U) ? 1U : 0U;
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000111
112 /* Construct SPSR for the exception state we're about to switch to */
113 if (caller_64) {
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +0100114 unsigned long long impl;
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000115
116 /*
117 * Switching from AArch64 to AArch32. Ensure this CPU implements
118 * the target EL in AArch32.
119 */
120 impl = from_el2 ? EL_IMPLEMENTED(2) : EL_IMPLEMENTED(1);
121 if (impl != EL_IMPL_A64_A32)
122 goto exec_denied;
123
124 /* Return to the equivalent AArch32 privilege level */
125 el = from_el2 ? MODE32_hyp : MODE32_svc;
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +0100126 spsr = SPSR_MODE32((u_register_t) el,
127 thumb ? SPSR_T_THUMB : SPSR_T_ARM,
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000128 endianness, DISABLE_ALL_EXCEPTIONS);
129 } else {
130 /*
131 * Switching from AArch32 to AArch64. Since it's not possible to
132 * implement an EL as AArch32-only (from which this call was
133 * raised), it's safe to assume AArch64 is also implemented.
134 */
135 el = from_el2 ? MODE_EL2 : MODE_EL1;
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +0100136 spsr = SPSR_64((u_register_t) el, MODE_SP_ELX,
137 DISABLE_ALL_EXCEPTIONS);
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000138 }
139
140 /*
141 * Use the context management library to re-initialize the existing
142 * context with the execution state flipped. Since the library takes
143 * entry_point_info_t pointer as the argument, construct a dummy one
144 * with PC, state width, endianness, security etc. appropriately set.
145 * Other entries in the entry point structure are irrelevant for
146 * purpose.
147 */
148 zeromem(&ep, sizeof(ep));
149 ep.pc = pc;
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +0100150 ep.spsr = (uint32_t) spsr;
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000151 SET_PARAM_HEAD(&ep, PARAM_EP, VERSION_1,
Jeenu Viswambharan210f0a82018-08-02 10:14:12 +0100152 ((unsigned int) ((endianness != 0U) ? EP_EE_BIG :
153 EP_EE_LITTLE)
154 | NON_SECURE | EP_ST_DISABLE));
Jeenu Viswambharanbc1a9292017-02-16 14:55:15 +0000155
156 /*
157 * Re-initialize the system register context, and exit EL3 as if for the
158 * first time. State switch is effectively a soft reset of the
159 * calling EL.
160 */
161 cm_init_my_context(&ep);
162 cm_prepare_el3_exit(NON_SECURE);
163
164 /*
165 * State switch success. The caller of SMC wouldn't see the SMC
166 * returning. Instead, execution starts at the supplied entry point,
167 * with context pointers populated in registers 0 and 1.
168 */
169 SMC_RET2(handle, cookie_hi, cookie_lo);
170
171invalid_param:
172 SMC_RET1(handle, STATE_SW_E_PARAM);
173
174exec_denied:
175#endif
176 /* State switch denied */
177 SMC_RET1(handle, STATE_SW_E_DENIED);
178}