blob: d20d8cdd7cf955e5081537113efde7c38bb4f48e [file] [log] [blame]
Dan Handley9df48042015-03-19 18:58:55 +00001/*
Vikram Kanigirifbb13012016-02-15 11:54:14 +00002 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <arch_helpers.h>
33#include <arm_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000034#include <assert.h>
35#include <bl_common.h>
Dan Handley9df48042015-03-19 18:58:55 +000036#include <console.h>
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010037#include <debug.h>
Dan Handley9df48042015-03-19 18:58:55 +000038#include <mmio.h>
39#include <plat_arm.h>
40#include <platform.h>
41
Soby Mathewa0fedc42016-06-16 14:52:04 +010042#define BL31_END (uintptr_t)(&__BL31_END__)
Dan Handley9df48042015-03-19 18:58:55 +000043
Dan Handley9df48042015-03-19 18:58:55 +000044/*
45 * Placeholder variables for copying the arguments that have been passed to
Juan Castillo7d199412015-12-14 09:35:25 +000046 * BL31 from BL2.
Dan Handley9df48042015-03-19 18:58:55 +000047 */
48static entry_point_info_t bl32_image_ep_info;
49static entry_point_info_t bl33_image_ep_info;
50
51
52/* Weak definitions may be overridden in specific ARM standard platform */
53#pragma weak bl31_early_platform_setup
54#pragma weak bl31_platform_setup
55#pragma weak bl31_plat_arch_setup
56#pragma weak bl31_plat_get_next_image_ep_info
Dan Handley9df48042015-03-19 18:58:55 +000057
58
59/*******************************************************************************
60 * Return a pointer to the 'entry_point_info' structure of the next image for the
Juan Castillo7d199412015-12-14 09:35:25 +000061 * security state specified. BL33 corresponds to the non-secure image type
62 * while BL32 corresponds to the secure image type. A NULL pointer is returned
Dan Handley9df48042015-03-19 18:58:55 +000063 * if the image does not exist.
64 ******************************************************************************/
65entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
66{
67 entry_point_info_t *next_image_info;
68
69 assert(sec_state_is_valid(type));
70 next_image_info = (type == NON_SECURE)
71 ? &bl33_image_ep_info : &bl32_image_ep_info;
72 /*
73 * None of the images on the ARM development platforms can have 0x0
74 * as the entrypoint
75 */
76 if (next_image_info->pc)
77 return next_image_info;
78 else
79 return NULL;
80}
81
82/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +000083 * Perform any BL31 early platform setup common to ARM standard platforms.
Dan Handley9df48042015-03-19 18:58:55 +000084 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1
85 * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be
86 * done before the MMU is initialized so that the memory layout can be used
87 * while creating page tables. BL2 has flushed this information to memory, so
88 * we are guaranteed to pick up good data.
89 ******************************************************************************/
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010090#if LOAD_IMAGE_V2
91void arm_bl31_early_platform_setup(void *from_bl2,
92 void *plat_params_from_bl2)
93#else
Dan Handley9df48042015-03-19 18:58:55 +000094void arm_bl31_early_platform_setup(bl31_params_t *from_bl2,
95 void *plat_params_from_bl2)
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010096#endif
Dan Handley9df48042015-03-19 18:58:55 +000097{
98 /* Initialize the console to provide early debug support */
99 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ,
100 ARM_CONSOLE_BAUDRATE);
101
102#if RESET_TO_BL31
Juan Castillo7d199412015-12-14 09:35:25 +0000103 /* There are no parameters from BL2 if BL31 is a reset vector */
Dan Handley9df48042015-03-19 18:58:55 +0000104 assert(from_bl2 == NULL);
105 assert(plat_params_from_bl2 == NULL);
106
Juan Castillo456deef2015-11-06 10:01:37 +0000107#ifdef BL32_BASE
Juan Castillo7d199412015-12-14 09:35:25 +0000108 /* Populate entry point information for BL32 */
Dan Handley9df48042015-03-19 18:58:55 +0000109 SET_PARAM_HEAD(&bl32_image_ep_info,
110 PARAM_EP,
111 VERSION_1,
112 0);
113 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
114 bl32_image_ep_info.pc = BL32_BASE;
115 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
Juan Castillo456deef2015-11-06 10:01:37 +0000116#endif /* BL32_BASE */
Dan Handley9df48042015-03-19 18:58:55 +0000117
Juan Castillo7d199412015-12-14 09:35:25 +0000118 /* Populate entry point information for BL33 */
Dan Handley9df48042015-03-19 18:58:55 +0000119 SET_PARAM_HEAD(&bl33_image_ep_info,
120 PARAM_EP,
121 VERSION_1,
122 0);
123 /*
Juan Castillo7d199412015-12-14 09:35:25 +0000124 * Tell BL31 where the non-trusted software image
Dan Handley9df48042015-03-19 18:58:55 +0000125 * is located and the entry state information
126 */
127 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
Soby Mathew4876ae32016-05-09 17:20:10 +0100128
Dan Handley9df48042015-03-19 18:58:55 +0000129 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
130 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
131
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100132#else /* RESET_TO_BL31 */
133
Dan Handley9df48042015-03-19 18:58:55 +0000134 /*
135 * In debug builds, we pass a special value in 'plat_params_from_bl2'
Juan Castillo7d199412015-12-14 09:35:25 +0000136 * to verify platform parameters from BL2 to BL31.
Dan Handley9df48042015-03-19 18:58:55 +0000137 * In release builds, it's not used.
138 */
139 assert(((unsigned long long)plat_params_from_bl2) ==
140 ARM_BL31_PLAT_PARAM_VAL);
141
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100142# if LOAD_IMAGE_V2
143 /*
144 * Check params passed from BL2 should not be NULL,
145 */
146 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
147 assert(params_from_bl2 != NULL);
148 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
149 assert(params_from_bl2->h.version >= VERSION_2);
150
151 bl_params_node_t *bl_params = params_from_bl2->head;
152
153 /*
154 * Copy BL33 and BL32 (if present), entry point information.
155 * They are stored in Secure RAM, in BL2's address space.
156 */
157 while (bl_params) {
158 if (bl_params->image_id == BL32_IMAGE_ID)
159 bl32_image_ep_info = *bl_params->ep_info;
160
161 if (bl_params->image_id == BL33_IMAGE_ID)
162 bl33_image_ep_info = *bl_params->ep_info;
163
164 bl_params = bl_params->next_params_info;
165 }
166
167 if (bl33_image_ep_info.pc == 0)
168 panic();
169
170# else /* LOAD_IMAGE_V2 */
171
172 /*
173 * Check params passed from BL2 should not be NULL,
174 */
175 assert(from_bl2 != NULL);
176 assert(from_bl2->h.type == PARAM_BL31);
177 assert(from_bl2->h.version >= VERSION_1);
178
Dan Handley9df48042015-03-19 18:58:55 +0000179 /*
Juan Castillo7d199412015-12-14 09:35:25 +0000180 * Copy BL32 (if populated by BL2) and BL33 entry point information.
Dan Handley9df48042015-03-19 18:58:55 +0000181 * They are stored in Secure RAM, in BL2's address space.
182 */
Juan Castillo456deef2015-11-06 10:01:37 +0000183 if (from_bl2->bl32_ep_info)
184 bl32_image_ep_info = *from_bl2->bl32_ep_info;
Dan Handley9df48042015-03-19 18:58:55 +0000185 bl33_image_ep_info = *from_bl2->bl33_ep_info;
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100186
187# endif /* LOAD_IMAGE_V2 */
188#endif /* RESET_TO_BL31 */
Dan Handley9df48042015-03-19 18:58:55 +0000189}
190
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100191#if LOAD_IMAGE_V2
192void bl31_early_platform_setup(void *from_bl2,
193 void *plat_params_from_bl2)
194#else
Dan Handley9df48042015-03-19 18:58:55 +0000195void bl31_early_platform_setup(bl31_params_t *from_bl2,
196 void *plat_params_from_bl2)
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100197#endif
Dan Handley9df48042015-03-19 18:58:55 +0000198{
199 arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2);
200
201 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000202 * Initialize Interconnect for this cluster during cold boot.
Dan Handley9df48042015-03-19 18:58:55 +0000203 * No need for locks as no other CPU is active.
204 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000205 plat_arm_interconnect_init();
Sandrine Bailleuxda797f62015-05-14 14:13:05 +0100206
Dan Handley9df48042015-03-19 18:58:55 +0000207 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000208 * Enable Interconnect coherency for the primary CPU's cluster.
Sandrine Bailleuxda797f62015-05-14 14:13:05 +0100209 * Earlier bootloader stages might already do this (e.g. Trusted
210 * Firmware's BL1 does it) but we can't assume so. There is no harm in
211 * executing this code twice anyway.
Dan Handley9df48042015-03-19 18:58:55 +0000212 * Platform specific PSCI code will enable coherency for other
213 * clusters.
214 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000215 plat_arm_interconnect_enter_coherency();
Dan Handley9df48042015-03-19 18:58:55 +0000216}
217
218/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000219 * Perform any BL31 platform setup common to ARM standard platforms
Dan Handley9df48042015-03-19 18:58:55 +0000220 ******************************************************************************/
221void arm_bl31_platform_setup(void)
222{
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000223 /* Initialize the GIC driver, cpu and distributor interfaces */
224 plat_arm_gic_driver_init();
Dan Handley9df48042015-03-19 18:58:55 +0000225 plat_arm_gic_init();
Dan Handley9df48042015-03-19 18:58:55 +0000226
227#if RESET_TO_BL31
228 /*
229 * Do initial security configuration to allow DRAM/device access
230 * (if earlier BL has not already done so).
231 */
232 plat_arm_security_setup();
233
234#endif /* RESET_TO_BL31 */
235
236 /* Enable and initialize the System level generic timer */
237 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
238 CNTCR_FCREQ(0) | CNTCR_EN);
239
240 /* Allow access to the System counter timer module */
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100241 arm_configure_sys_timer();
Dan Handley9df48042015-03-19 18:58:55 +0000242
243 /* Initialize power controller before setting up topology */
244 plat_arm_pwrc_setup();
Dan Handley9df48042015-03-19 18:58:55 +0000245}
246
Soby Mathew2fd66be2015-12-09 11:38:43 +0000247/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000248 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM
Soby Mathew2fd66be2015-12-09 11:38:43 +0000249 * standard platforms
250 ******************************************************************************/
251void arm_bl31_plat_runtime_setup(void)
252{
253 /* Initialize the runtime console */
254 console_init(PLAT_ARM_BL31_RUN_UART_BASE, PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ,
255 ARM_CONSOLE_BAUDRATE);
256}
257
Dan Handley9df48042015-03-19 18:58:55 +0000258void bl31_platform_setup(void)
259{
260 arm_bl31_platform_setup();
261}
262
Soby Mathew2fd66be2015-12-09 11:38:43 +0000263void bl31_plat_runtime_setup(void)
264{
265 arm_bl31_plat_runtime_setup();
266}
267
Dan Handley9df48042015-03-19 18:58:55 +0000268/*******************************************************************************
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100269 * Perform the very early platform specific architectural setup shared between
270 * ARM standard platforms. This only does basic initialization. Later
271 * architectural setup (bl31_arch_setup()) does not do anything platform
272 * specific.
Dan Handley9df48042015-03-19 18:58:55 +0000273 ******************************************************************************/
274void arm_bl31_plat_arch_setup(void)
275{
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +0100276 arm_setup_page_tables(BL31_BASE,
277 BL31_END - BL31_BASE,
278 BL_CODE_BASE,
Masahiro Yamada51bef612017-01-18 02:10:08 +0900279 BL_CODE_END,
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +0100280 BL_RO_DATA_BASE,
Masahiro Yamada51bef612017-01-18 02:10:08 +0900281 BL_RO_DATA_END
Dan Handley9df48042015-03-19 18:58:55 +0000282#if USE_COHERENT_MEM
Masahiro Yamada0fac5af2016-12-28 16:11:41 +0900283 , BL_COHERENT_RAM_BASE,
284 BL_COHERENT_RAM_END
Dan Handley9df48042015-03-19 18:58:55 +0000285#endif
286 );
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100287 enable_mmu_el3(0);
Dan Handley9df48042015-03-19 18:58:55 +0000288}
289
290void bl31_plat_arch_setup(void)
291{
292 arm_bl31_plat_arch_setup();
293}