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Sandrine Bailleux798140d2014-07-17 16:06:39 +01001/*
2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __PLATFORM_DEF_H__
32#define __PLATFORM_DEF_H__
33
34#include <arch.h>
Sandrine Bailleux1fe43362014-07-17 09:56:29 +010035#include "../juno_def.h"
Sandrine Bailleux798140d2014-07-17 16:06:39 +010036
37/*******************************************************************************
38 * Platform binary types for linking
39 ******************************************************************************/
40#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
41#define PLATFORM_LINKER_ARCH aarch64
42
43/*******************************************************************************
44 * Generic platform constants
45 ******************************************************************************/
46
47/* Size of cacheable stacks */
Juan Castillo9c25a402015-01-13 12:21:04 +000048#if TRUSTED_BOARD_BOOT && (IMAGE_BL1 || IMAGE_BL2)
49#define PLATFORM_STACK_SIZE 0x1000
50#else
51#define PLATFORM_STACK_SIZE 0x800
52#endif
Sandrine Bailleux798140d2014-07-17 16:06:39 +010053
54#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
55
56/* Trusted Boot Firmware BL2 */
57#define BL2_IMAGE_NAME "bl2.bin"
58
59/* EL3 Runtime Firmware BL3-1 */
60#define BL31_IMAGE_NAME "bl31.bin"
61
62/* SCP Firmware BL3-0 */
63#define BL30_IMAGE_NAME "bl30.bin"
64
65/* Secure Payload BL3-2 (Trusted OS) */
66#define BL32_IMAGE_NAME "bl32.bin"
67
68/* Non-Trusted Firmware BL3-3 */
69#define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */
70
71/* Firmware Image Package */
72#define FIP_IMAGE_NAME "fip.bin"
73
Juan Castillod227d8b2015-01-07 13:49:59 +000074#if TRUSTED_BOARD_BOOT
75/* Certificates */
76# define BL2_CERT_NAME "bl2.crt"
Juan Castillo9246ab82015-01-28 16:46:57 +000077# define TRUSTED_KEY_CERT_NAME "trusted_key.crt"
78
79# define BL30_KEY_CERT_NAME "bl30_key.crt"
80# define BL31_KEY_CERT_NAME "bl31_key.crt"
81# define BL32_KEY_CERT_NAME "bl32_key.crt"
82# define BL33_KEY_CERT_NAME "bl33_key.crt"
83
84# define BL30_CERT_NAME "bl30.crt"
85# define BL31_CERT_NAME "bl31.crt"
86# define BL32_CERT_NAME "bl32.crt"
87# define BL33_CERT_NAME "bl33.crt"
Juan Castillod227d8b2015-01-07 13:49:59 +000088#endif /* TRUSTED_BOARD_BOOT */
89
Sandrine Bailleux798140d2014-07-17 16:06:39 +010090#define PLATFORM_CACHE_LINE_SIZE 64
91#define PLATFORM_CLUSTER_COUNT 2
92#define PLATFORM_CORE_COUNT 6
93#define PLATFORM_NUM_AFFS (PLATFORM_CLUSTER_COUNT + \
94 PLATFORM_CORE_COUNT)
Soby Mathew2b7de2b2015-02-12 14:45:02 +000095#define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL1
Sandrine Bailleux798140d2014-07-17 16:06:39 +010096#define MAX_IO_DEVICES 3
97#define MAX_IO_HANDLES 4
98
99/*******************************************************************************
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100100 * BL1 specific defines.
101 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 base
102 * addresses.
103 ******************************************************************************/
104#define BL1_RO_BASE TZROM_BASE
105#define BL1_RO_LIMIT (TZROM_BASE + TZROM_SIZE)
Juan Castillo6ba59eb2014-11-07 09:44:58 +0000106
107/*
108 * Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using
109 * the current BL1 RW debug size plus a little space for growth.
110 */
Juan Castillo9c25a402015-01-13 12:21:04 +0000111#if TRUSTED_BOARD_BOOT
112#define BL1_RW_BASE (TZRAM_BASE + TZRAM_SIZE - 0x8000)
113#else
Juan Castillo6ba59eb2014-11-07 09:44:58 +0000114#define BL1_RW_BASE (TZRAM_BASE + TZRAM_SIZE - 0x6000)
Juan Castillo9c25a402015-01-13 12:21:04 +0000115#endif
Juan Castillo6ba59eb2014-11-07 09:44:58 +0000116#define BL1_RW_LIMIT (TZRAM_BASE + TZRAM_SIZE)
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100117
118/*******************************************************************************
119 * BL2 specific defines.
120 ******************************************************************************/
Juan Castillo6ba59eb2014-11-07 09:44:58 +0000121/*
122 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
123 * size plus a little space for growth.
124 */
Juan Castillo9c25a402015-01-13 12:21:04 +0000125#if TRUSTED_BOARD_BOOT
126#define BL2_BASE (BL31_BASE - 0x1D000)
127#else
Juan Castillo6ba59eb2014-11-07 09:44:58 +0000128#define BL2_BASE (BL31_BASE - 0xC000)
Juan Castillo9c25a402015-01-13 12:21:04 +0000129#endif
Juan Castillo6ba59eb2014-11-07 09:44:58 +0000130#define BL2_LIMIT BL31_BASE
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100131
132/*******************************************************************************
133 * Load address of BL3-0 in the Juno port
134 * BL3-0 is loaded to the same place as BL3-1. Once BL3-0 is transferred to the
135 * SCP, it is discarded and BL3-1 is loaded over the top.
136 ******************************************************************************/
137#define BL30_BASE BL31_BASE
138
139/*******************************************************************************
140 * BL3-1 specific defines.
141 ******************************************************************************/
Juan Castillo6ba59eb2014-11-07 09:44:58 +0000142/*
143 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the
144 * current BL3-1 debug size plus a little space for growth.
145 */
146#define BL31_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1D000)
147#define BL31_PROGBITS_LIMIT BL1_RW_BASE
148#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100149
150/*******************************************************************************
151 * BL3-2 specific defines.
152 ******************************************************************************/
Juan Castillo921b8772014-09-05 17:29:38 +0100153#if (PLAT_TSP_LOCATION_ID == PLAT_TRUSTED_SRAM_ID)
154# define TSP_SEC_MEM_BASE TZRAM_BASE
155# define TSP_SEC_MEM_SIZE TZRAM_SIZE
Juan Castillo6ba59eb2014-11-07 09:44:58 +0000156# define BL32_BASE TZRAM_BASE
157# define BL32_LIMIT BL31_BASE
158# define BL32_PROGBITS_LIMIT BL2_BASE
Juan Castillo921b8772014-09-05 17:29:38 +0100159#elif (PLAT_TSP_LOCATION_ID == PLAT_DRAM_ID)
160# define TSP_SEC_MEM_BASE DRAM_SEC_BASE
161# define TSP_SEC_MEM_SIZE (DRAM_SEC_SIZE - DRAM_SCP_SIZE)
162# define BL32_BASE DRAM_SEC_BASE
163# define BL32_LIMIT (DRAM_SEC_BASE + DRAM_SEC_SIZE - \
164 DRAM_SCP_SIZE)
165#else
166# error "Unsupported PLAT_TSP_LOCATION_ID value"
167#endif
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100168
169/*******************************************************************************
170 * Load address of BL3-3 in the Juno port
171 ******************************************************************************/
172#define NS_IMAGE_OFFSET 0xE0000000
173
174/*******************************************************************************
175 * Platform specific page table and MMU setup constants
176 ******************************************************************************/
177#define ADDR_SPACE_SIZE (1ull << 32)
Juan Castillo921b8772014-09-05 17:29:38 +0100178
179#if IMAGE_BL1 || IMAGE_BL31
180# define MAX_XLAT_TABLES 2
181#endif
182
183#if IMAGE_BL2 || IMAGE_BL32
184# define MAX_XLAT_TABLES 3
185#endif
186
Soby Mathew13ee9682015-01-22 11:22:22 +0000187#define MAX_MMAP_REGIONS (JUNO_MMAP_ENTRIES + JUNO_BL_REGIONS)
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100188
189/*******************************************************************************
Sandrine Bailleux1fe43362014-07-17 09:56:29 +0100190 * ID of the secure physical generic timer interrupt used by the TSP
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100191 ******************************************************************************/
Sandrine Bailleux1fe43362014-07-17 09:56:29 +0100192#define TSP_IRQ_SEC_PHY_TIMER IRQ_SEC_PHY_TIMER
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100193
194/*******************************************************************************
195 * Declarations and constants to access the mailboxes safely. Each mailbox is
196 * aligned on the biggest cache line size in the platform. This is known only
197 * to the platform as it might have a combination of integrated and external
198 * caches. Such alignment ensures that two maiboxes do not sit on the same cache
199 * line at any cache level. They could belong to different cpus/clusters &
200 * get written while being protected by different locks causing corruption of
201 * a valid mailbox address.
202 ******************************************************************************/
203#define CACHE_WRITEBACK_SHIFT 6
204#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
205
Soby Mathew523d6332015-01-08 18:02:19 +0000206#if !USE_COHERENT_MEM
207/*******************************************************************************
208 * Size of the per-cpu data in bytes that should be reserved in the generic
209 * per-cpu data structure for the Juno port.
210 ******************************************************************************/
211#define PLAT_PCPU_DATA_SIZE 2
212#endif
213
Sandrine Bailleux798140d2014-07-17 16:06:39 +0100214#endif /* __PLATFORM_DEF_H__ */