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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Soby Mathew981487a2015-07-13 14:10:57 +01002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handley2bd4ef22014-04-09 13:14:54 +010031#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <assert.h>
Soby Mathew96168382014-12-17 14:47:57 +000034#include <debug.h>
35#include <platform.h>
Jeenu Viswambharancaa84932014-02-06 10:36:15 +000036#include <runtime_svc.h>
Soby Mathew6cdddaf2015-01-07 11:10:22 +000037#include <std_svc.h>
Soby Mathew981487a2015-07-13 14:10:57 +010038#include <string.h>
Dan Handley714a0d22014-04-09 13:13:04 +010039#include "psci_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010040
41/*******************************************************************************
42 * PSCI frontend api for servicing SMCs. Described in the PSCI spec.
43 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +010044int psci_cpu_on(u_register_t target_cpu,
45 uintptr_t entrypoint,
46 u_register_t context_id)
Achin Gupta4f6ad662013-10-25 09:08:21 +010047
48{
49 int rc;
Soby Mathew981487a2015-07-13 14:10:57 +010050 unsigned int end_pwrlvl;
Soby Mathew8595b872015-01-06 15:36:38 +000051 entry_point_info_t ep;
Achin Gupta4f6ad662013-10-25 09:08:21 +010052
53 /* Determine if the cpu exists of not */
Soby Mathew981487a2015-07-13 14:10:57 +010054 rc = psci_validate_mpidr(target_cpu);
55 if (rc != PSCI_E_SUCCESS)
Soby Mathew74e52a72014-10-02 16:56:51 +010056 return PSCI_E_INVALID_PARAMS;
Soby Mathew74e52a72014-10-02 16:56:51 +010057
Soby Mathewf1f97a12015-07-15 12:13:26 +010058 /* Validate the entry point and get the entry_point_info */
59 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew8595b872015-01-06 15:36:38 +000060 if (rc != PSCI_E_SUCCESS)
61 return rc;
62
Soby Mathew8595b872015-01-06 15:36:38 +000063 /*
Soby Mathew981487a2015-07-13 14:10:57 +010064 * To turn this cpu on, specify which power
Achin Gupta0959db52013-12-02 17:33:04 +000065 * levels need to be turned on
66 */
Soby Mathew981487a2015-07-13 14:10:57 +010067 end_pwrlvl = PLAT_MAX_PWR_LVL;
68 rc = psci_cpu_on_start(target_cpu,
Soby Mathew8595b872015-01-06 15:36:38 +000069 &ep,
Soby Mathew981487a2015-07-13 14:10:57 +010070 end_pwrlvl);
Achin Gupta4f6ad662013-10-25 09:08:21 +010071 return rc;
72}
73
74unsigned int psci_version(void)
75{
76 return PSCI_MAJOR_VER | PSCI_MINOR_VER;
77}
78
79int psci_cpu_suspend(unsigned int power_state,
Soby Mathew011ca182015-07-29 17:05:03 +010080 uintptr_t entrypoint,
81 u_register_t context_id)
Achin Gupta4f6ad662013-10-25 09:08:21 +010082{
83 int rc;
Soby Mathew981487a2015-07-13 14:10:57 +010084 unsigned int target_pwrlvl, is_power_down_state;
Soby Mathew8595b872015-01-06 15:36:38 +000085 entry_point_info_t ep;
Soby Mathew981487a2015-07-13 14:10:57 +010086 psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
87 plat_local_state_t cpu_pd_state;
Achin Gupta4f6ad662013-10-25 09:08:21 +010088
Soby Mathew981487a2015-07-13 14:10:57 +010089 /* Validate the power_state parameter */
90 rc = psci_validate_power_state(power_state, &state_info);
91 if (rc != PSCI_E_SUCCESS) {
92 assert(rc == PSCI_E_INVALID_PARAMS);
93 return rc;
94 }
Vikram Kanigirif100f412014-04-01 19:26:26 +010095
Soby Mathew981487a2015-07-13 14:10:57 +010096 /*
97 * Get the value of the state type bit from the power state parameter.
98 */
99 is_power_down_state = psci_get_pstate_type(power_state);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100100
Soby Mathew981487a2015-07-13 14:10:57 +0100101 /* Sanity check the requested suspend levels */
102 assert (psci_validate_suspend_req(&state_info, is_power_down_state)
103 == PSCI_E_SUCCESS);
Soby Mathew74e52a72014-10-02 16:56:51 +0100104
Soby Mathew981487a2015-07-13 14:10:57 +0100105 target_pwrlvl = psci_find_target_suspend_lvl(&state_info);
106
107 /* Fast path for CPU standby.*/
108 if (is_cpu_standby_req(is_power_down_state, target_pwrlvl)) {
109 if (!psci_plat_pm_ops->cpu_standby)
Soby Mathew74e52a72014-10-02 16:56:51 +0100110 return PSCI_E_INVALID_PARAMS;
Soby Mathew74e52a72014-10-02 16:56:51 +0100111
Soby Mathew981487a2015-07-13 14:10:57 +0100112 /*
113 * Set the state of the CPU power domain to the platform
114 * specific retention state and enter the standby state.
115 */
116 cpu_pd_state = state_info.pwr_domain_state[PSCI_CPU_PWR_LVL];
117 psci_set_cpu_local_state(cpu_pd_state);
118 psci_plat_pm_ops->cpu_standby(cpu_pd_state);
Achin Gupta42c52802014-05-09 19:32:25 +0100119
Soby Mathew981487a2015-07-13 14:10:57 +0100120 /* Upon exit from standby, set the state back to RUN. */
121 psci_set_cpu_local_state(PSCI_LOCAL_STATE_RUN);
Achin Gupta42c52802014-05-09 19:32:25 +0100122
Soby Mathew74e52a72014-10-02 16:56:51 +0100123 return PSCI_E_SUCCESS;
Vikram Kanigiri3b7c59b2014-03-21 11:57:10 +0000124 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100125
Achin Gupta42c52802014-05-09 19:32:25 +0100126 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100127 * If a power down state has been requested, we need to verify entry
128 * point and program entry information.
Soby Mathew8595b872015-01-06 15:36:38 +0000129 */
Soby Mathew981487a2015-07-13 14:10:57 +0100130 if (is_power_down_state) {
Soby Mathewf1f97a12015-07-15 12:13:26 +0100131 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew981487a2015-07-13 14:10:57 +0100132 if (rc != PSCI_E_SUCCESS)
133 return rc;
134 }
Soby Mathewf5121572014-09-30 11:19:51 +0100135
Soby Mathew8595b872015-01-06 15:36:38 +0000136 /*
Achin Gupta42c52802014-05-09 19:32:25 +0100137 * Do what is needed to enter the power down state. Upon success,
Soby Mathew981487a2015-07-13 14:10:57 +0100138 * enter the final wfi which will power down this CPU. This function
139 * might return if the power down was abandoned for any reason, e.g.
140 * arrival of an interrupt
Achin Gupta42c52802014-05-09 19:32:25 +0100141 */
Soby Mathew981487a2015-07-13 14:10:57 +0100142 psci_cpu_suspend_start(&ep,
143 target_pwrlvl,
144 &state_info,
145 is_power_down_state);
Soby Mathew74e52a72014-10-02 16:56:51 +0100146
Soby Mathew74e52a72014-10-02 16:56:51 +0100147 return PSCI_E_SUCCESS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100148}
149
Soby Mathew011ca182015-07-29 17:05:03 +0100150
151int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id)
Soby Mathew96168382014-12-17 14:47:57 +0000152{
153 int rc;
Soby Mathew981487a2015-07-13 14:10:57 +0100154 psci_power_state_t state_info;
Soby Mathew96168382014-12-17 14:47:57 +0000155 entry_point_info_t ep;
156
Soby Mathew96168382014-12-17 14:47:57 +0000157 /* Check if the current CPU is the last ON CPU in the system */
158 if (!psci_is_last_on_cpu())
159 return PSCI_E_DENIED;
160
Soby Mathewf1f97a12015-07-15 12:13:26 +0100161 /* Validate the entry point and get the entry_point_info */
162 rc = psci_validate_entry_point(&ep, entrypoint, context_id);
Soby Mathew96168382014-12-17 14:47:57 +0000163 if (rc != PSCI_E_SUCCESS)
164 return rc;
165
Soby Mathew981487a2015-07-13 14:10:57 +0100166 /* Query the psci_power_state for system suspend */
167 psci_query_sys_suspend_pwrstate(&state_info);
Soby Mathew96168382014-12-17 14:47:57 +0000168
Soby Mathew981487a2015-07-13 14:10:57 +0100169 /* Ensure that the psci_power_state makes sense */
170 assert(psci_find_target_suspend_lvl(&state_info) == PLAT_MAX_PWR_LVL);
171 assert(psci_validate_suspend_req(&state_info, PSTATE_TYPE_POWERDOWN)
172 == PSCI_E_SUCCESS);
173 assert(is_local_state_off(state_info.pwr_domain_state[PLAT_MAX_PWR_LVL]));
Soby Mathew96168382014-12-17 14:47:57 +0000174
175 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100176 * Do what is needed to enter the system suspend state. This function
177 * might return if the power down was abandoned for any reason, e.g.
178 * arrival of an interrupt
Soby Mathew96168382014-12-17 14:47:57 +0000179 */
Soby Mathew981487a2015-07-13 14:10:57 +0100180 psci_cpu_suspend_start(&ep,
181 PLAT_MAX_PWR_LVL,
182 &state_info,
183 PSTATE_TYPE_POWERDOWN);
Soby Mathew96168382014-12-17 14:47:57 +0000184
Soby Mathew96168382014-12-17 14:47:57 +0000185 return PSCI_E_SUCCESS;
186}
187
Achin Gupta4f6ad662013-10-25 09:08:21 +0100188int psci_cpu_off(void)
189{
190 int rc;
Soby Mathew011ca182015-07-29 17:05:03 +0100191 unsigned int target_pwrlvl = PLAT_MAX_PWR_LVL;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100192
Achin Gupta4f6ad662013-10-25 09:08:21 +0100193 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100194 * Do what is needed to power off this CPU and possible higher power
195 * levels if it able to do so. Upon success, enter the final wfi
196 * which will power down this CPU.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100197 */
Soby Mathew981487a2015-07-13 14:10:57 +0100198 rc = psci_do_cpu_off(target_pwrlvl);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100199
Achin Gupta3140a9e2013-12-02 16:23:12 +0000200 /*
201 * The only error cpu_off can return is E_DENIED. So check if that's
202 * indeed the case.
203 */
Achin Gupta42c52802014-05-09 19:32:25 +0100204 assert (rc == PSCI_E_DENIED);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100205
206 return rc;
207}
208
Soby Mathew011ca182015-07-29 17:05:03 +0100209int psci_affinity_info(u_register_t target_affinity,
Achin Gupta4f6ad662013-10-25 09:08:21 +0100210 unsigned int lowest_affinity_level)
211{
Soby Mathew981487a2015-07-13 14:10:57 +0100212 unsigned int target_idx;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100213
Soby Mathew981487a2015-07-13 14:10:57 +0100214 /* We dont support level higher than PSCI_CPU_PWR_LVL */
215 if (lowest_affinity_level > PSCI_CPU_PWR_LVL)
216 return PSCI_E_INVALID_PARAMS;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100217
Soby Mathew981487a2015-07-13 14:10:57 +0100218 /* Calculate the cpu index of the target */
219 target_idx = plat_core_pos_by_mpidr(target_affinity);
220 if (target_idx == -1)
221 return PSCI_E_INVALID_PARAMS;
Achin Gupta75f73672013-12-05 16:33:10 +0000222
Soby Mathew981487a2015-07-13 14:10:57 +0100223 return psci_get_aff_info_state_by_idx(target_idx);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100224}
225
Soby Mathew011ca182015-07-29 17:05:03 +0100226int psci_migrate(u_register_t target_cpu)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100227{
Soby Mathew110fe362014-10-23 10:35:34 +0100228 int rc;
Soby Mathew011ca182015-07-29 17:05:03 +0100229 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100230
231 rc = psci_spd_migrate_info(&resident_cpu_mpidr);
232 if (rc != PSCI_TOS_UP_MIG_CAP)
233 return (rc == PSCI_TOS_NOT_UP_MIG_CAP) ?
234 PSCI_E_DENIED : PSCI_E_NOT_SUPPORTED;
235
236 /*
237 * Migrate should only be invoked on the CPU where
238 * the Secure OS is resident.
239 */
240 if (resident_cpu_mpidr != read_mpidr_el1())
241 return PSCI_E_NOT_PRESENT;
242
243 /* Check the validity of the specified target cpu */
Soby Mathew981487a2015-07-13 14:10:57 +0100244 rc = psci_validate_mpidr(target_cpu);
Soby Mathew110fe362014-10-23 10:35:34 +0100245 if (rc != PSCI_E_SUCCESS)
246 return PSCI_E_INVALID_PARAMS;
247
248 assert(psci_spd_pm && psci_spd_pm->svc_migrate);
249
250 rc = psci_spd_pm->svc_migrate(read_mpidr_el1(), target_cpu);
251 assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL);
252
253 return rc;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100254}
255
Soby Mathew110fe362014-10-23 10:35:34 +0100256int psci_migrate_info_type(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100257{
Soby Mathew011ca182015-07-29 17:05:03 +0100258 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100259
260 return psci_spd_migrate_info(&resident_cpu_mpidr);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100261}
262
Soby Mathew110fe362014-10-23 10:35:34 +0100263long psci_migrate_info_up_cpu(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100264{
Soby Mathew011ca182015-07-29 17:05:03 +0100265 u_register_t resident_cpu_mpidr;
Soby Mathew110fe362014-10-23 10:35:34 +0100266 int rc;
267
Achin Gupta4f6ad662013-10-25 09:08:21 +0100268 /*
Soby Mathew110fe362014-10-23 10:35:34 +0100269 * Return value of this depends upon what
270 * psci_spd_migrate_info() returns.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100271 */
Soby Mathew110fe362014-10-23 10:35:34 +0100272 rc = psci_spd_migrate_info(&resident_cpu_mpidr);
273 if (rc != PSCI_TOS_NOT_UP_MIG_CAP && rc != PSCI_TOS_UP_MIG_CAP)
274 return PSCI_E_INVALID_PARAMS;
275
276 return resident_cpu_mpidr;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100277}
278
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000279int psci_features(unsigned int psci_fid)
280{
Soby Mathew011ca182015-07-29 17:05:03 +0100281 unsigned int local_caps = psci_caps;
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000282
283 /* Check if it is a 64 bit function */
284 if (((psci_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_64)
285 local_caps &= PSCI_CAP_64BIT_MASK;
286
287 /* Check for invalid fid */
288 if (!(is_std_svc_call(psci_fid) && is_valid_fast_smc(psci_fid)
289 && is_psci_fid(psci_fid)))
290 return PSCI_E_NOT_SUPPORTED;
291
292
293 /* Check if the psci fid is supported or not */
294 if (!(local_caps & define_psci_cap(psci_fid)))
295 return PSCI_E_NOT_SUPPORTED;
296
297 /* Format the feature flags */
298 if (psci_fid == PSCI_CPU_SUSPEND_AARCH32 ||
299 psci_fid == PSCI_CPU_SUSPEND_AARCH64) {
300 /*
Soby Mathew981487a2015-07-13 14:10:57 +0100301 * The trusted firmware does not support OS Initiated Mode.
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000302 */
Soby Mathew981487a2015-07-13 14:10:57 +0100303 return (FF_PSTATE << FF_PSTATE_SHIFT) |
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000304 ((!FF_SUPPORTS_OS_INIT_MODE) << FF_MODE_SUPPORT_SHIFT);
305 }
306
307 /* Return 0 for all other fid's */
308 return PSCI_E_SUCCESS;
309}
310
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000311/*******************************************************************************
312 * PSCI top level handler for servicing SMCs.
313 ******************************************************************************/
314uint64_t psci_smc_handler(uint32_t smc_fid,
315 uint64_t x1,
316 uint64_t x2,
317 uint64_t x3,
318 uint64_t x4,
319 void *cookie,
320 void *handle,
321 uint64_t flags)
322{
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100323 if (is_caller_secure(flags))
324 SMC_RET1(handle, SMC_UNK);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000325
Soby Mathew61e615b2015-01-15 11:49:49 +0000326 /* Check the fid against the capabilities */
327 if (!(psci_caps & define_psci_cap(smc_fid)))
328 SMC_RET1(handle, SMC_UNK);
329
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100330 if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) {
331 /* 32-bit PSCI function, clear top parameter bits */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000332
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100333 x1 = (uint32_t)x1;
334 x2 = (uint32_t)x2;
335 x3 = (uint32_t)x3;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000336
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100337 switch (smc_fid) {
338 case PSCI_VERSION:
339 SMC_RET1(handle, psci_version());
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000340
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100341 case PSCI_CPU_OFF:
Achin Guptae1aa5162014-06-26 09:58:52 +0100342 SMC_RET1(handle, psci_cpu_off());
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000343
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100344 case PSCI_CPU_SUSPEND_AARCH32:
Achin Guptae1aa5162014-06-26 09:58:52 +0100345 SMC_RET1(handle, psci_cpu_suspend(x1, x2, x3));
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000346
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100347 case PSCI_CPU_ON_AARCH32:
348 SMC_RET1(handle, psci_cpu_on(x1, x2, x3));
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000349
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100350 case PSCI_AFFINITY_INFO_AARCH32:
351 SMC_RET1(handle, psci_affinity_info(x1, x2));
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000352
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100353 case PSCI_MIG_AARCH32:
354 SMC_RET1(handle, psci_migrate(x1));
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000355
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100356 case PSCI_MIG_INFO_TYPE:
357 SMC_RET1(handle, psci_migrate_info_type());
358
359 case PSCI_MIG_INFO_UP_CPU_AARCH32:
360 SMC_RET1(handle, psci_migrate_info_up_cpu());
361
Soby Mathew96168382014-12-17 14:47:57 +0000362 case PSCI_SYSTEM_SUSPEND_AARCH32:
363 SMC_RET1(handle, psci_system_suspend(x1, x2));
364
Juan Castillo4dc4a472014-08-12 11:17:06 +0100365 case PSCI_SYSTEM_OFF:
366 psci_system_off();
367 /* We should never return from psci_system_off() */
368
369 case PSCI_SYSTEM_RESET:
370 psci_system_reset();
371 /* We should never return from psci_system_reset() */
372
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000373 case PSCI_FEATURES:
374 SMC_RET1(handle, psci_features(x1));
375
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100376 default:
377 break;
378 }
379 } else {
380 /* 64-bit PSCI function */
381
382 switch (smc_fid) {
383 case PSCI_CPU_SUSPEND_AARCH64:
Achin Guptae1aa5162014-06-26 09:58:52 +0100384 SMC_RET1(handle, psci_cpu_suspend(x1, x2, x3));
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100385
386 case PSCI_CPU_ON_AARCH64:
387 SMC_RET1(handle, psci_cpu_on(x1, x2, x3));
388
389 case PSCI_AFFINITY_INFO_AARCH64:
390 SMC_RET1(handle, psci_affinity_info(x1, x2));
391
392 case PSCI_MIG_AARCH64:
393 SMC_RET1(handle, psci_migrate(x1));
394
395 case PSCI_MIG_INFO_UP_CPU_AARCH64:
396 SMC_RET1(handle, psci_migrate_info_up_cpu());
397
Soby Mathew96168382014-12-17 14:47:57 +0000398 case PSCI_SYSTEM_SUSPEND_AARCH64:
399 SMC_RET1(handle, psci_system_suspend(x1, x2));
400
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100401 default:
402 break;
403 }
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000404 }
405
Andrew Thoelke89a3c842014-06-10 16:37:37 +0100406 WARN("Unimplemented PSCI Call: 0x%x \n", smc_fid);
407 SMC_RET1(handle, SMC_UNK);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000408}