johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 1 | /* |
Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 2 | * Copyright (c) 2021-2022, Arm Limited. All rights reserved. |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
| 10 | #include <cortex_a710.h> |
| 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 13 | #include "wa_cve_2022_23960_bhb_vector.S" |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 14 | |
| 15 | /* Hardware handled coherency */ |
| 16 | #if HW_ASSISTED_COHERENCY == 0 |
| 17 | #error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 18 | #endif |
| 19 | |
| 20 | /* 64-bit only core */ |
| 21 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
| 22 | #error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
| 23 | #endif |
| 24 | |
Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 25 | #if WORKAROUND_CVE_2022_23960 |
| 26 | wa_cve_2022_23960_bhb_vector_table CORTEX_A710_BHB_LOOP_COUNT, cortex_a710 |
| 27 | #endif /* WORKAROUND_CVE_2022_23960 */ |
| 28 | |
nayanpatel-arm | e55d325 | 2021-08-06 16:39:48 -0700 | [diff] [blame] | 29 | /* -------------------------------------------------- |
| 30 | * Errata Workaround for Cortex-A710 Erratum 1987031. |
| 31 | * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. It is still |
| 32 | * open. |
| 33 | * Inputs: |
| 34 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 35 | * Shall clobber: x0-x17 |
| 36 | * -------------------------------------------------- |
| 37 | */ |
| 38 | func errata_a710_1987031_wa |
| 39 | /* Check revision. */ |
| 40 | mov x17, x30 |
| 41 | bl check_errata_1987031 |
| 42 | cbz x0, 1f |
| 43 | |
| 44 | /* Apply instruction patching sequence */ |
| 45 | ldr x0,=0x6 |
| 46 | msr S3_6_c15_c8_0,x0 |
| 47 | ldr x0,=0xF3A08002 |
| 48 | msr S3_6_c15_c8_2,x0 |
| 49 | ldr x0,=0xFFF0F7FE |
| 50 | msr S3_6_c15_c8_3,x0 |
| 51 | ldr x0,=0x40000001003ff |
| 52 | msr S3_6_c15_c8_1,x0 |
| 53 | ldr x0,=0x7 |
| 54 | msr S3_6_c15_c8_0,x0 |
| 55 | ldr x0,=0xBF200000 |
| 56 | msr S3_6_c15_c8_2,x0 |
| 57 | ldr x0,=0xFFEF0000 |
| 58 | msr S3_6_c15_c8_3,x0 |
| 59 | ldr x0,=0x40000001003f3 |
| 60 | msr S3_6_c15_c8_1,x0 |
| 61 | isb |
| 62 | 1: |
| 63 | ret x17 |
| 64 | endfunc errata_a710_1987031_wa |
| 65 | |
| 66 | func check_errata_1987031 |
| 67 | /* Applies to r0p0, r1p0 and r2p0 */ |
| 68 | mov x1, #0x20 |
| 69 | b cpu_rev_var_ls |
| 70 | endfunc check_errata_1987031 |
| 71 | |
nayanpatel-arm | 7597d08 | 2021-08-25 17:35:15 -0700 | [diff] [blame] | 72 | /* -------------------------------------------------- |
| 73 | * Errata Workaround for Cortex-A710 Erratum 2081180. |
| 74 | * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. |
| 75 | * It is still open. |
| 76 | * Inputs: |
| 77 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 78 | * Shall clobber: x0-x17 |
| 79 | * -------------------------------------------------- |
| 80 | */ |
| 81 | func errata_a710_2081180_wa |
| 82 | /* Check revision. */ |
| 83 | mov x17, x30 |
| 84 | bl check_errata_2081180 |
| 85 | cbz x0, 1f |
| 86 | |
| 87 | /* Apply instruction patching sequence */ |
| 88 | ldr x0,=0x3 |
| 89 | msr S3_6_c15_c8_0,x0 |
| 90 | ldr x0,=0xF3A08002 |
| 91 | msr S3_6_c15_c8_2,x0 |
| 92 | ldr x0,=0xFFF0F7FE |
| 93 | msr S3_6_c15_c8_3,x0 |
| 94 | ldr x0,=0x10002001003FF |
| 95 | msr S3_6_c15_c8_1,x0 |
| 96 | ldr x0,=0x4 |
| 97 | msr S3_6_c15_c8_0,x0 |
| 98 | ldr x0,=0xBF200000 |
| 99 | msr S3_6_c15_c8_2,x0 |
| 100 | ldr x0,=0xFFEF0000 |
| 101 | msr S3_6_c15_c8_3,x0 |
| 102 | ldr x0,=0x10002001003F3 |
| 103 | msr S3_6_c15_c8_1,x0 |
| 104 | isb |
| 105 | 1: |
| 106 | ret x17 |
| 107 | endfunc errata_a710_2081180_wa |
| 108 | |
| 109 | func check_errata_2081180 |
| 110 | /* Applies to r0p0, r1p0 and r2p0 */ |
| 111 | mov x1, #0x20 |
| 112 | b cpu_rev_var_ls |
| 113 | endfunc check_errata_2081180 |
| 114 | |
Bipin Ravi | cd39b14 | 2021-03-31 16:45:40 -0500 | [diff] [blame] | 115 | /* --------------------------------------------------------------------- |
| 116 | * Errata Workaround for Cortex-A710 Erratum 2055002. |
| 117 | * This applies to revision r1p0, r2p0 of Cortex-A710 and is still open. |
| 118 | * Inputs: |
| 119 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 120 | * Shall clobber: x0-x17 |
| 121 | * --------------------------------------------------------------------- |
| 122 | */ |
| 123 | func errata_a710_2055002_wa |
| 124 | /* Compare x0 against revision r2p0 */ |
| 125 | mov x17, x30 |
| 126 | bl check_errata_2055002 |
| 127 | cbz x0, 1f |
| 128 | mrs x1, CORTEX_A710_CPUACTLR_EL1 |
| 129 | orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_46 |
| 130 | msr CORTEX_A710_CPUACTLR_EL1, x1 |
| 131 | 1: |
| 132 | ret x17 |
| 133 | endfunc errata_a710_2055002_wa |
| 134 | |
| 135 | func check_errata_2055002 |
| 136 | /* Applies to r1p0, r2p0 */ |
| 137 | mov x1, #0x20 |
| 138 | b cpu_rev_var_ls |
| 139 | endfunc check_errata_2055002 |
| 140 | |
Bipin Ravi | 87e1d28 | 2021-03-31 18:45:55 -0500 | [diff] [blame] | 141 | /* ------------------------------------------------------------- |
| 142 | * Errata Workaround for Cortex-A710 Erratum 2017096. |
| 143 | * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710. |
| 144 | * Inputs: |
| 145 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 146 | * Shall clobber: x0-x17 |
| 147 | * ------------------------------------------------------------- |
| 148 | */ |
| 149 | func errata_a710_2017096_wa |
| 150 | /* Compare x0 against revision r0p0 to r2p0 */ |
| 151 | mov x17, x30 |
| 152 | bl check_errata_2017096 |
| 153 | cbz x0, 1f |
| 154 | mrs x1, CORTEX_A710_CPUECTLR_EL1 |
| 155 | orr x1, x1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT |
| 156 | msr CORTEX_A710_CPUECTLR_EL1, x1 |
| 157 | |
| 158 | 1: |
| 159 | ret x17 |
| 160 | endfunc errata_a710_2017096_wa |
| 161 | |
| 162 | func check_errata_2017096 |
| 163 | /* Applies to r0p0, r1p0, r2p0 */ |
| 164 | mov x1, #0x20 |
| 165 | b cpu_rev_var_ls |
| 166 | endfunc check_errata_2017096 |
| 167 | |
nayanpatel-arm | 0b338b4 | 2021-09-16 15:27:53 -0700 | [diff] [blame] | 168 | |
| 169 | /* --------------------------------------------------------------------- |
| 170 | * Errata Workaround for Cortex-A710 Erratum 2083908. |
| 171 | * This applies to revision r2p0 of Cortex-A710 and is still open. |
| 172 | * Inputs: |
| 173 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 174 | * Shall clobber: x0-x17 |
| 175 | * --------------------------------------------------------------------- |
| 176 | */ |
| 177 | func errata_a710_2083908_wa |
| 178 | /* Compare x0 against revision r2p0 */ |
| 179 | mov x17, x30 |
| 180 | bl check_errata_2083908 |
| 181 | cbz x0, 1f |
| 182 | mrs x1, CORTEX_A710_CPUACTLR5_EL1 |
| 183 | orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 |
| 184 | msr CORTEX_A710_CPUACTLR5_EL1, x1 |
| 185 | 1: |
| 186 | ret x17 |
| 187 | endfunc errata_a710_2083908_wa |
| 188 | |
| 189 | func check_errata_2083908 |
| 190 | /* Applies to r2p0 */ |
| 191 | mov x1, #CPU_REV(2, 0) |
| 192 | mov x2, #CPU_REV(2, 0) |
| 193 | b cpu_rev_var_range |
| 194 | endfunc check_errata_2083908 |
| 195 | |
nayanpatel-arm | f2dce0e | 2021-09-22 12:35:03 -0700 | [diff] [blame] | 196 | /* --------------------------------------------------------------------- |
| 197 | * Errata Workaround for Cortex-A710 Erratum 2058056. |
| 198 | * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710 and is still |
| 199 | * open. |
| 200 | * Inputs: |
| 201 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 202 | * Shall clobber: x0-x17 |
| 203 | * --------------------------------------------------------------------- |
| 204 | */ |
| 205 | func errata_a710_2058056_wa |
| 206 | /* Compare x0 against revision r2p0 */ |
| 207 | mov x17, x30 |
| 208 | bl check_errata_2058056 |
| 209 | cbz x0, 1f |
| 210 | mrs x1, CORTEX_A710_CPUECTLR2_EL1 |
| 211 | mov x0, #CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV |
| 212 | bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH |
| 213 | msr CORTEX_A710_CPUECTLR2_EL1, x1 |
| 214 | 1: |
| 215 | ret x17 |
| 216 | endfunc errata_a710_2058056_wa |
| 217 | |
| 218 | func check_errata_2058056 |
| 219 | /* Applies to r0p0, r1p0 and r2p0 */ |
| 220 | mov x1, #0x20 |
| 221 | b cpu_rev_var_ls |
| 222 | endfunc check_errata_2058056 |
| 223 | |
Bipin Ravi | 32705b1 | 2022-02-06 02:32:54 -0600 | [diff] [blame] | 224 | /* -------------------------------------------------- |
| 225 | * Errata Workaround for Cortex-A710 Erratum 2267065. |
| 226 | * This applies to revisions r0p0, r1p0 and r2p0. |
| 227 | * It is fixed in r2p1. |
| 228 | * Inputs: |
| 229 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 230 | * Shall clobber: x0-x1, x17 |
| 231 | * -------------------------------------------------- |
| 232 | */ |
| 233 | func errata_a710_2267065_wa |
| 234 | /* Compare x0 against revision r2p0 */ |
| 235 | mov x17, x30 |
| 236 | bl check_errata_2267065 |
| 237 | cbz x0, 1f |
| 238 | |
| 239 | /* Apply instruction patching sequence */ |
| 240 | mrs x1, CORTEX_A710_CPUACTLR_EL1 |
| 241 | orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_22 |
| 242 | msr CORTEX_A710_CPUACTLR_EL1, x1 |
| 243 | 1: |
| 244 | ret x17 |
| 245 | endfunc errata_a710_2267065_wa |
| 246 | |
| 247 | func check_errata_2267065 |
| 248 | /* Applies to r0p0, r1p0 and r2p0 */ |
| 249 | mov x1, #0x20 |
| 250 | b cpu_rev_var_ls |
| 251 | endfunc check_errata_2267065 |
| 252 | |
Bipin Ravi | d53069b | 2022-02-06 03:11:44 -0600 | [diff] [blame] | 253 | /* --------------------------------------------------------------- |
| 254 | * Errata Workaround for Cortex-A710 Erratum 2136059. |
| 255 | * This applies to revision r0p0, r1p0 and r2p0. |
| 256 | * It is fixed in r2p1. |
| 257 | * Inputs: |
| 258 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 259 | * Shall clobber: x0-x17 |
| 260 | * --------------------------------------------------------------- |
| 261 | */ |
| 262 | func errata_a710_2136059_wa |
| 263 | /* Compare x0 against revision r2p0 */ |
| 264 | mov x17, x30 |
| 265 | bl check_errata_2136059 |
| 266 | cbz x0, 1f |
| 267 | |
| 268 | /* Apply the workaround */ |
| 269 | mrs x1, CORTEX_A710_CPUACTLR5_EL1 |
| 270 | orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_44 |
| 271 | msr CORTEX_A710_CPUACTLR5_EL1, x1 |
| 272 | |
| 273 | 1: |
| 274 | ret x17 |
| 275 | endfunc errata_a710_2136059_wa |
| 276 | |
| 277 | func check_errata_2136059 |
| 278 | /* Applies to r0p0, r1p0 and r2p0 */ |
| 279 | mov x1, #0x20 |
| 280 | b cpu_rev_var_ls |
| 281 | endfunc check_errata_2136059 |
| 282 | |
johpow01 | 7249fd0 | 2022-02-28 18:34:04 -0600 | [diff] [blame] | 283 | /* --------------------------------------------------------------- |
| 284 | * Errata Workaround for Cortex-A710 Erratum 2282622. |
| 285 | * This applies to revision r0p0, r1p0 and r2p0. |
| 286 | * It is fixed in r2p1. |
| 287 | * Inputs: |
| 288 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 289 | * Shall clobber: x0, x1, x17 |
| 290 | * --------------------------------------------------------------- |
| 291 | */ |
| 292 | func errata_a710_2282622_wa |
| 293 | /* Compare x0 against revision r2p0 */ |
| 294 | mov x17, x30 |
| 295 | bl check_errata_2282622 |
| 296 | cbz x0, 1f |
| 297 | |
| 298 | /* Apply the workaround */ |
| 299 | mrs x1, CORTEX_A710_CPUACTLR2_EL1 |
| 300 | orr x1, x1, BIT(0) |
| 301 | msr CORTEX_A710_CPUACTLR2_EL1, x1 |
| 302 | |
| 303 | 1: |
| 304 | ret x17 |
| 305 | endfunc errata_a710_2282622_wa |
| 306 | |
| 307 | func check_errata_2282622 |
| 308 | /* Applies to r0p0, r1p0 and r2p0 */ |
| 309 | mov x1, #0x20 |
| 310 | b cpu_rev_var_ls |
| 311 | endfunc check_errata_2282622 |
| 312 | |
johpow01 | 7d52a8f | 2022-03-09 16:23:04 -0600 | [diff] [blame] | 313 | /* --------------------------------------------------------------- |
| 314 | * Errata Workaround for Cortex-A710 Erratum 2008768. |
| 315 | * This applies to revision r0p0, r1p0 and r2p0. |
| 316 | * It is fixed in r2p1. |
| 317 | * Inputs: |
| 318 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 319 | * Shall clobber: x0, x1, x2, x17 |
| 320 | * --------------------------------------------------------------- |
| 321 | */ |
| 322 | func errata_a710_2008768_wa |
| 323 | mov x17, x30 |
| 324 | bl check_errata_2008768 |
| 325 | cbz x0, 1f |
| 326 | |
| 327 | /* Stash ERRSELR_EL1 in x2 */ |
| 328 | mrs x2, ERRSELR_EL1 |
| 329 | |
| 330 | /* Select error record 0 and clear ED bit */ |
| 331 | msr ERRSELR_EL1, xzr |
| 332 | mrs x1, ERXCTLR_EL1 |
| 333 | bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 |
| 334 | msr ERXCTLR_EL1, x1 |
| 335 | |
| 336 | /* Select error record 1 and clear ED bit */ |
| 337 | mov x0, #1 |
| 338 | msr ERRSELR_EL1, x0 |
| 339 | mrs x1, ERXCTLR_EL1 |
| 340 | bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1 |
| 341 | msr ERXCTLR_EL1, x1 |
| 342 | |
| 343 | /* Restore ERRSELR_EL1 from x2 */ |
| 344 | msr ERRSELR_EL1, x2 |
| 345 | |
| 346 | 1: |
| 347 | ret x17 |
| 348 | endfunc errata_a710_2008768_wa |
| 349 | |
| 350 | func check_errata_2008768 |
| 351 | /* Applies to r0p0, r1p0 and r2p0 */ |
| 352 | mov x1, #0x20 |
| 353 | b cpu_rev_var_ls |
| 354 | endfunc check_errata_2008768 |
| 355 | |
Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 356 | func check_errata_cve_2022_23960 |
| 357 | #if WORKAROUND_CVE_2022_23960 |
| 358 | mov x0, #ERRATA_APPLIES |
| 359 | #else |
| 360 | mov x0, #ERRATA_MISSING |
| 361 | #endif |
| 362 | ret |
| 363 | endfunc check_errata_cve_2022_23960 |
| 364 | |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 365 | /* ---------------------------------------------------- |
| 366 | * HW will do the cache maintenance while powering down |
| 367 | * ---------------------------------------------------- |
| 368 | */ |
| 369 | func cortex_a710_core_pwr_dwn |
johpow01 | 7d52a8f | 2022-03-09 16:23:04 -0600 | [diff] [blame] | 370 | |
| 371 | #if ERRATA_A710_2008768 |
| 372 | mov x4, x30 |
| 373 | bl cpu_get_rev_var |
| 374 | bl errata_a710_2008768_wa |
| 375 | mov x30, x4 |
| 376 | #endif |
| 377 | |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 378 | /* --------------------------------------------------- |
| 379 | * Enable CPU power down bit in power control register |
| 380 | * --------------------------------------------------- |
| 381 | */ |
| 382 | mrs x0, CORTEX_A710_CPUPWRCTLR_EL1 |
| 383 | orr x0, x0, #CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT |
| 384 | msr CORTEX_A710_CPUPWRCTLR_EL1, x0 |
| 385 | isb |
| 386 | ret |
| 387 | endfunc cortex_a710_core_pwr_dwn |
| 388 | |
Bipin Ravi | cd39b14 | 2021-03-31 16:45:40 -0500 | [diff] [blame] | 389 | #if REPORT_ERRATA |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 390 | /* |
Bipin Ravi | cd39b14 | 2021-03-31 16:45:40 -0500 | [diff] [blame] | 391 | * Errata printing function for Cortex-A710. Must follow AAPCS. |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 392 | */ |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 393 | func cortex_a710_errata_report |
nayanpatel-arm | e55d325 | 2021-08-06 16:39:48 -0700 | [diff] [blame] | 394 | stp x8, x30, [sp, #-16]! |
| 395 | |
| 396 | bl cpu_get_rev_var |
| 397 | mov x8, x0 |
| 398 | |
| 399 | /* |
| 400 | * Report all errata. The revision-variant information is passed to |
| 401 | * checking functions of each errata. |
| 402 | */ |
| 403 | report_errata ERRATA_A710_1987031, cortex_a710, 1987031 |
nayanpatel-arm | 7597d08 | 2021-08-25 17:35:15 -0700 | [diff] [blame] | 404 | report_errata ERRATA_A710_2081180, cortex_a710, 2081180 |
Bipin Ravi | cd39b14 | 2021-03-31 16:45:40 -0500 | [diff] [blame] | 405 | report_errata ERRATA_A710_2055002, cortex_a710, 2055002 |
Bipin Ravi | 87e1d28 | 2021-03-31 18:45:55 -0500 | [diff] [blame] | 406 | report_errata ERRATA_A710_2017096, cortex_a710, 2017096 |
nayanpatel-arm | 0b338b4 | 2021-09-16 15:27:53 -0700 | [diff] [blame] | 407 | report_errata ERRATA_A710_2083908, cortex_a710, 2083908 |
nayanpatel-arm | f2dce0e | 2021-09-22 12:35:03 -0700 | [diff] [blame] | 408 | report_errata ERRATA_A710_2058056, cortex_a710, 2058056 |
Bipin Ravi | 32705b1 | 2022-02-06 02:32:54 -0600 | [diff] [blame] | 409 | report_errata ERRATA_A710_2267065, cortex_a710, 2267065 |
Bipin Ravi | d53069b | 2022-02-06 03:11:44 -0600 | [diff] [blame] | 410 | report_errata ERRATA_A710_2136059, cortex_a710, 2136059 |
johpow01 | 7249fd0 | 2022-02-28 18:34:04 -0600 | [diff] [blame] | 411 | report_errata ERRATA_A710_2282622, cortex_a710, 2282622 |
johpow01 | 7d52a8f | 2022-03-09 16:23:04 -0600 | [diff] [blame] | 412 | report_errata ERRATA_A710_2008768, cortex_a710, 2008768 |
Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 413 | report_errata WORKAROUND_CVE_2022_23960, cortex_a710, cve_2022_23960 |
Bipin Ravi | af40d69 | 2021-12-22 14:35:21 -0600 | [diff] [blame] | 414 | report_errata ERRATA_DSU_2313941, cortex_a710, dsu_2313941 |
nayanpatel-arm | e55d325 | 2021-08-06 16:39:48 -0700 | [diff] [blame] | 415 | |
| 416 | ldp x8, x30, [sp], #16 |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 417 | ret |
| 418 | endfunc cortex_a710_errata_report |
| 419 | #endif |
| 420 | |
| 421 | func cortex_a710_reset_func |
nayanpatel-arm | e55d325 | 2021-08-06 16:39:48 -0700 | [diff] [blame] | 422 | mov x19, x30 |
| 423 | |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 424 | /* Disable speculative loads */ |
| 425 | msr SSBS, xzr |
nayanpatel-arm | e55d325 | 2021-08-06 16:39:48 -0700 | [diff] [blame] | 426 | |
| 427 | bl cpu_get_rev_var |
| 428 | mov x18, x0 |
| 429 | |
Bipin Ravi | af40d69 | 2021-12-22 14:35:21 -0600 | [diff] [blame] | 430 | #if ERRATA_DSU_2313941 |
| 431 | bl errata_dsu_2313941_wa |
| 432 | #endif |
| 433 | |
nayanpatel-arm | e55d325 | 2021-08-06 16:39:48 -0700 | [diff] [blame] | 434 | #if ERRATA_A710_1987031 |
| 435 | mov x0, x18 |
| 436 | bl errata_a710_1987031_wa |
| 437 | #endif |
| 438 | |
nayanpatel-arm | 7597d08 | 2021-08-25 17:35:15 -0700 | [diff] [blame] | 439 | #if ERRATA_A710_2081180 |
| 440 | mov x0, x18 |
| 441 | bl errata_a710_2081180_wa |
| 442 | #endif |
| 443 | |
Bipin Ravi | cd39b14 | 2021-03-31 16:45:40 -0500 | [diff] [blame] | 444 | #if ERRATA_A710_2055002 |
| 445 | mov x0, x18 |
| 446 | bl errata_a710_2055002_wa |
| 447 | #endif |
| 448 | |
Bipin Ravi | 87e1d28 | 2021-03-31 18:45:55 -0500 | [diff] [blame] | 449 | #if ERRATA_A710_2017096 |
nayanpatel-arm | 0b338b4 | 2021-09-16 15:27:53 -0700 | [diff] [blame] | 450 | mov x0, x18 |
| 451 | bl errata_a710_2017096_wa |
| 452 | #endif |
| 453 | |
| 454 | #if ERRATA_A710_2083908 |
| 455 | mov x0, x18 |
| 456 | bl errata_a710_2083908_wa |
Bipin Ravi | 87e1d28 | 2021-03-31 18:45:55 -0500 | [diff] [blame] | 457 | #endif |
nayanpatel-arm | f2dce0e | 2021-09-22 12:35:03 -0700 | [diff] [blame] | 458 | |
| 459 | #if ERRATA_A710_2058056 |
| 460 | mov x0, x18 |
| 461 | bl errata_a710_2058056_wa |
| 462 | #endif |
Bipin Ravi | 32705b1 | 2022-02-06 02:32:54 -0600 | [diff] [blame] | 463 | |
| 464 | #if ERRATA_A710_2267065 |
| 465 | mov x0, x18 |
| 466 | bl errata_a710_2267065_wa |
| 467 | #endif |
| 468 | |
Bipin Ravi | d53069b | 2022-02-06 03:11:44 -0600 | [diff] [blame] | 469 | #if ERRATA_A710_2136059 |
| 470 | mov x0, x18 |
| 471 | bl errata_a710_2136059_wa |
| 472 | #endif |
| 473 | |
johpow01 | 7249fd0 | 2022-02-28 18:34:04 -0600 | [diff] [blame] | 474 | #if ERRATA_A710_2282622 |
| 475 | mov x0, x18 |
| 476 | bl errata_a710_2282622_wa |
| 477 | #endif |
| 478 | |
Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 479 | #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 |
| 480 | /* |
| 481 | * The Cortex-A710 generic vectors are overridden to apply errata |
| 482 | * mitigation on exception entry from lower ELs. |
| 483 | */ |
| 484 | adr x0, wa_cve_vbar_cortex_a710 |
| 485 | msr vbar_el3, x0 |
| 486 | #endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ |
| 487 | |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 488 | isb |
Bipin Ravi | cd39b14 | 2021-03-31 16:45:40 -0500 | [diff] [blame] | 489 | ret x19 |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 490 | endfunc cortex_a710_reset_func |
| 491 | |
| 492 | /* --------------------------------------------- |
| 493 | * This function provides Cortex-A710 specific |
| 494 | * register information for crash reporting. |
| 495 | * It needs to return with x6 pointing to |
| 496 | * a list of register names in ascii and |
| 497 | * x8 - x15 having values of registers to be |
| 498 | * reported. |
| 499 | * --------------------------------------------- |
| 500 | */ |
| 501 | .section .rodata.cortex_a710_regs, "aS" |
| 502 | cortex_a710_regs: /* The ascii list of register names to be reported */ |
| 503 | .asciz "cpuectlr_el1", "" |
| 504 | |
| 505 | func cortex_a710_cpu_reg_dump |
| 506 | adr x6, cortex_a710_regs |
| 507 | mrs x8, CORTEX_A710_CPUECTLR_EL1 |
| 508 | ret |
| 509 | endfunc cortex_a710_cpu_reg_dump |
| 510 | |
| 511 | declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ |
| 512 | cortex_a710_reset_func, \ |
| 513 | cortex_a710_core_pwr_dwn |