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Hadi Asyrafiab1132f2019-10-22 10:31:45 +08001/*
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +08002 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
Hadi Asyrafiab1132f2019-10-22 10:31:45 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef SOCFPGA_SIP_SVC_H
8#define SOCFPGA_SIP_SVC_H
9
10
11/* SiP status response */
12#define INTEL_SIP_SMC_STATUS_OK 0
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080013#define INTEL_SIP_SMC_STATUS_BUSY 0x1
14#define INTEL_SIP_SMC_STATUS_REJECTED 0x2
Abdul Halim, Muhammad Hadi Asyrafi25f623e2020-02-27 10:23:48 +080015#define INTEL_SIP_SMC_STATUS_ERROR 0x4
16#define INTEL_SIP_SMC_RSU_ERROR 0x7
17
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +080018/* SiP mailbox error code */
19#define GENERIC_RESPONSE_ERROR 0x3FF
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080020
21/* SMC SiP service function identifier */
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080022
23/* FPGA Reconfig */
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080024#define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001
25#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002
26#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003
27#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004
28#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080029
30/* Secure Register Access */
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080031#define INTEL_SIP_SMC_REG_READ 0xC2000007
32#define INTEL_SIP_SMC_REG_WRITE 0xC2000008
33#define INTEL_SIP_SMC_REG_UPDATE 0xC2000009
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080034
35/* Remote System Update */
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080036#define INTEL_SIP_SMC_RSU_STATUS 0xC200000B
37#define INTEL_SIP_SMC_RSU_UPDATE 0xC200000C
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080038#define INTEL_SIP_SMC_RSU_NOTIFY 0xC200000E
39#define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +080040#define INTEL_SIP_SMC_RSU_DCMF_VERSION 0xC2000010
41#define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION 0xC2000011
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080042
Sieu Mun Tangdbcc2cf2022-03-07 12:13:04 +080043
44/* ECC */
45#define INTEL_SIP_SMC_ECC_DBE 0xC200000D
46
Sieu Mun Tanga34b8812022-03-17 03:11:55 +080047/* Generic Command */
48#define INTEL_SIP_SMC_GET_ROM_PATCH_SHA384 0xC2000040
49
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080050/* Send Mailbox Command */
Hadi Asyrafia33e8102019-12-17 19:30:41 +080051#define INTEL_SIP_SMC_MBOX_SEND_CMD 0xC200001E
Abdul Halim, Muhammad Hadi Asyrafib30ce3f2020-06-18 16:21:29 +080052#define INTEL_SIP_SMC_HPS_SET_BRIDGES 0xC2000032
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080053
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +080054
55/* SiP Definitions */
56
Sieu Mun Tangdbcc2cf2022-03-07 12:13:04 +080057/* ECC DBE */
58#define WARM_RESET_WFI_FLAG BIT(31)
59#define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\
60 SYSMGR_ECC_DDR0_MASK |\
61 SYSMGR_ECC_DDR1_MASK)
62
Sieu Mun Tangf9cb6572022-04-27 18:24:06 +080063/* Non-mailbox SMC Call */
64#define INTEL_SIP_SMC_SVC_VERSION 0xC2000200
65
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080066/* SMC function IDs for SiP Service queries */
67#define SIP_SVC_CALL_COUNT 0x8200ff00
68#define SIP_SVC_UID 0x8200ff01
69#define SIP_SVC_VERSION 0x8200ff03
70
71/* SiP Service Calls version numbers */
Sieu Mun Tangf9cb6572022-04-27 18:24:06 +080072#define SIP_SVC_VERSION_MAJOR 1
73#define SIP_SVC_VERSION_MINOR 0
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080074
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +080075
76/* Structure Definitions */
77struct fpga_config_info {
78 uint32_t addr;
79 int size;
80 int size_written;
81 uint32_t write_requested;
82 int subblocks_sent;
83 int block_number;
84};
85
Abdul Halim, Muhammad Hadi Asyrafib251c332020-05-29 12:13:17 +080086typedef enum {
87 FULL_CONFIG = 0,
88 PARTIAL_CONFIG,
89} config_type;
90
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +080091/* Function Definitions */
92
93bool is_address_in_ddr_range(uint64_t addr, uint64_t size);
94
Sieu Mun Tangdbcc2cf2022-03-07 12:13:04 +080095/* ECC DBE */
96bool cold_reset_for_ecc_dbe(void);
97uint32_t intel_ecc_dbe_notification(uint64_t dbe_value);
98
Hadi Asyrafiab1132f2019-10-22 10:31:45 +080099#endif /* SOCFPGA_SIP_SVC_H */