Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | ab2d31e | 2013-12-02 19:25:12 +0000 | [diff] [blame^] | 2 | * Copyright (c) 2013, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <string.h> |
| 32 | #include <assert.h> |
| 33 | #include <arch_helpers.h> |
| 34 | #include <platform.h> |
| 35 | #include <bl1.h> |
| 36 | #include <console.h> |
Harry Liebel | 30affd5 | 2013-10-30 17:41:48 +0000 | [diff] [blame] | 37 | #include <cci400.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 38 | |
| 39 | /******************************************************************************* |
| 40 | * Declarations of linker defined symbols which will help us find the layout |
| 41 | * of trusted SRAM |
| 42 | ******************************************************************************/ |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 43 | extern unsigned long __COHERENT_RAM_START__; |
| 44 | extern unsigned long __COHERENT_RAM_END__; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 45 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 46 | extern unsigned long __BL1_RAM_START__; |
| 47 | extern unsigned long __BL1_RAM_END__; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 48 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 49 | /* |
| 50 | * The next 2 constants identify the extents of the coherent memory region. |
| 51 | * These addresses are used by the MMU setup code and therefore they must be |
| 52 | * page-aligned. It is the responsibility of the linker script to ensure that |
| 53 | * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to |
| 54 | * page-aligned addresses. |
| 55 | */ |
| 56 | #define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) |
| 57 | #define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 58 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 59 | #define BL1_RAM_BASE (unsigned long)(&__BL1_RAM_START__) |
| 60 | #define BL1_RAM_LIMIT (unsigned long)(&__BL1_RAM_END__) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 61 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 62 | |
| 63 | /* Data structure which holds the extents of the trusted SRAM for BL1*/ |
Sandrine Bailleux | 204aa03 | 2013-10-28 15:14:00 +0000 | [diff] [blame] | 64 | static meminfo bl1_tzram_layout; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 65 | |
| 66 | meminfo bl1_get_sec_mem_layout(void) |
| 67 | { |
| 68 | return bl1_tzram_layout; |
| 69 | } |
| 70 | |
| 71 | /******************************************************************************* |
| 72 | * Perform any BL1 specific platform actions. |
| 73 | ******************************************************************************/ |
| 74 | void bl1_early_platform_setup(void) |
| 75 | { |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 76 | const unsigned long bl1_ram_base = BL1_RAM_BASE; |
| 77 | const unsigned long bl1_ram_limit = BL1_RAM_LIMIT; |
| 78 | const unsigned long tzram_limit = TZRAM_BASE + TZRAM_SIZE; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 79 | |
| 80 | /* |
| 81 | * Calculate how much ram is BL1 using & how much remains free. |
| 82 | * This also includes a rudimentary mechanism to detect whether |
| 83 | * the BL1 data is loaded at the top or bottom of memory. |
| 84 | * TODO: add support for discontigous chunks of free ram if |
| 85 | * needed. Might need dynamic memory allocation support |
| 86 | * et al. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 87 | */ |
| 88 | bl1_tzram_layout.total_base = TZRAM_BASE; |
| 89 | bl1_tzram_layout.total_size = TZRAM_SIZE; |
| 90 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 91 | if (bl1_ram_limit == tzram_limit) { |
| 92 | /* BL1 has been loaded at the top of memory. */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 93 | bl1_tzram_layout.free_base = TZRAM_BASE; |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 94 | bl1_tzram_layout.free_size = bl1_ram_base - TZRAM_BASE; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 95 | } else { |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 96 | /* BL1 has been loaded at the bottom of memory. */ |
| 97 | bl1_tzram_layout.free_base = bl1_ram_limit; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 98 | bl1_tzram_layout.free_size = |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 99 | tzram_limit - bl1_ram_limit; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 100 | } |
Harry Liebel | 30affd5 | 2013-10-30 17:41:48 +0000 | [diff] [blame] | 101 | |
| 102 | /* Initialize the platform config for future decision making */ |
| 103 | platform_config_setup(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 104 | } |
| 105 | |
| 106 | /******************************************************************************* |
| 107 | * Function which will evaluate how much of the trusted ram has been gobbled |
| 108 | * up by BL1 and return the base and size of whats available for loading BL2. |
| 109 | * Its called after coherency and the MMU have been turned on. |
| 110 | ******************************************************************************/ |
| 111 | void bl1_platform_setup(void) |
| 112 | { |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 113 | /* Enable and initialize the System level generic timer */ |
| 114 | mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_EN); |
| 115 | |
| 116 | /* Initialize the console */ |
| 117 | console_init(); |
| 118 | |
| 119 | return; |
| 120 | } |
| 121 | |
| 122 | /******************************************************************************* |
| 123 | * Perform the very early platform specific architecture setup here. At the |
Harry Liebel | 30affd5 | 2013-10-30 17:41:48 +0000 | [diff] [blame] | 124 | * moment this only does basic initialization. Later architectural setup |
| 125 | * (bl1_arch_setup()) does not do anything platform specific. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 126 | ******************************************************************************/ |
| 127 | void bl1_plat_arch_setup(void) |
| 128 | { |
Harry Liebel | 30affd5 | 2013-10-30 17:41:48 +0000 | [diff] [blame] | 129 | unsigned long cci_setup; |
| 130 | |
| 131 | /* |
| 132 | * Enable CCI-400 for this cluster. No need |
| 133 | * for locks as no other cpu is active at the |
| 134 | * moment |
| 135 | */ |
| 136 | cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI); |
| 137 | if (cci_setup) { |
| 138 | cci_enable_coherency(read_mpidr()); |
| 139 | } |
| 140 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 141 | configure_mmu(&bl1_tzram_layout, |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 142 | TZROM_BASE, |
| 143 | TZROM_BASE + TZROM_SIZE, |
| 144 | BL1_COHERENT_RAM_BASE, |
| 145 | BL1_COHERENT_RAM_LIMIT); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 146 | } |