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johpow019baade32021-07-08 14:14:00 -05001/*
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +00002 * Copyright (c) 2021-2023, Arm Limited and Contributors. All rights reserved.
johpow019baade32021-07-08 14:14:00 -05003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <stdbool.h>
8
9#include <arch.h>
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +000010#include <arch_features.h>
johpow019baade32021-07-08 14:14:00 -050011#include <arch_helpers.h>
12#include <common/debug.h>
13#include <lib/el3_runtime/context_mgmt.h>
14#include <lib/extensions/sme.h>
15#include <lib/extensions/sve.h>
16
johpow019baade32021-07-08 14:14:00 -050017void sme_enable(cpu_context_t *context)
18{
19 u_register_t reg;
20 u_register_t cptr_el3;
21 el3_state_t *state;
22
johpow019baade32021-07-08 14:14:00 -050023 /* Get the context state. */
24 state = get_el3state_ctx(context);
25
26 /* Enable SME in CPTR_EL3. */
27 reg = read_ctx_reg(state, CTX_CPTR_EL3);
28 reg |= ESM_BIT;
29 write_ctx_reg(state, CTX_CPTR_EL3, reg);
30
31 /* Set the ENTP2 bit in SCR_EL3 to enable access to TPIDR2_EL0. */
32 reg = read_ctx_reg(state, CTX_SCR_EL3);
33 reg |= SCR_ENTP2_BIT;
34 write_ctx_reg(state, CTX_SCR_EL3, reg);
35
36 /* Set CPTR_EL3.ESM bit so we can write SMCR_EL3 without trapping. */
37 cptr_el3 = read_cptr_el3();
38 write_cptr_el3(cptr_el3 | ESM_BIT);
Boyan Karatotevbe028b42022-10-13 13:51:05 +010039 isb();
johpow019baade32021-07-08 14:14:00 -050040
41 /*
42 * Set the max LEN value and FA64 bit. This register is set up globally
43 * to be the least restrictive, then lower ELs can restrict as needed
44 * using SMCR_EL2 and SMCR_EL1.
45 */
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +000046 reg = SMCR_ELX_LEN_MAX;
47
Jayanth Dodderi Chidanand605419a2023-03-06 23:56:14 +000048 if (read_feat_sme_fa64_id_field() != 0U) {
johpow019baade32021-07-08 14:14:00 -050049 VERBOSE("[SME] FA64 enabled\n");
50 reg |= SMCR_ELX_FA64_BIT;
51 }
Jayanth Dodderi Chidanandcfe053a2022-11-08 10:31:07 +000052
53 /*
54 * Enable access to ZT0 register.
55 * Make sure FEAT_SME2 is supported by the hardware before continuing.
56 * If supported, Set the EZT0 bit in SMCR_EL3 to allow instructions to
57 * access ZT0 register without trapping.
58 */
59 if (is_feat_sme2_supported()) {
60 VERBOSE("SME2 enabled\n");
61 reg |= SMCR_ELX_EZT0_BIT;
62 }
johpow019baade32021-07-08 14:14:00 -050063 write_smcr_el3(reg);
64
65 /* Reset CPTR_EL3 value. */
66 write_cptr_el3(cptr_el3);
Boyan Karatotevbe028b42022-10-13 13:51:05 +010067 isb();
johpow019baade32021-07-08 14:14:00 -050068
69 /* Enable SVE/FPU in addition to SME. */
70 sve_enable(context);
71}
72
73void sme_disable(cpu_context_t *context)
74{
75 u_register_t reg;
76 el3_state_t *state;
77
johpow019baade32021-07-08 14:14:00 -050078 /* Get the context state. */
79 state = get_el3state_ctx(context);
80
81 /* Disable SME, SVE, and FPU since they all share registers. */
82 reg = read_ctx_reg(state, CTX_CPTR_EL3);
83 reg &= ~ESM_BIT; /* Trap SME */
84 reg &= ~CPTR_EZ_BIT; /* Trap SVE */
85 reg |= TFP_BIT; /* Trap FPU/SIMD */
86 write_ctx_reg(state, CTX_CPTR_EL3, reg);
87
88 /* Disable access to TPIDR2_EL0. */
89 reg = read_ctx_reg(state, CTX_SCR_EL3);
90 reg &= ~SCR_ENTP2_BIT;
91 write_ctx_reg(state, CTX_SCR_EL3, reg);
92}