feat(sme): enable SME2 functionality for NS world
FEAT_SME2 is an extension of FEAT_SME and an optional feature
from v9.2. Its an extension of SME, wherein it not only
processes matrix operations efficiently, but also provides
outer-product instructions to accelerate matrix operations.
It affords instructions for multi-vector operations.
Further, it adds an 512 bit architectural register ZT0.
This patch implements all the changes introduced with FEAT_SME2
to ensure that the instructions are allowed to access ZT0
register from Non-secure lower exception levels.
Additionally, it adds support to ensure FEAT_SME2 is aligned
with the existing FEATURE DETECTION mechanism, and documented.
Change-Id: Iee0f61943304a9cfc3db8f986047b1321d0a6463
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
diff --git a/lib/extensions/sme/sme.c b/lib/extensions/sme/sme.c
index 29034fd..f888d12 100644
--- a/lib/extensions/sme/sme.c
+++ b/lib/extensions/sme/sme.c
@@ -43,11 +43,23 @@
* to be the least restrictive, then lower ELs can restrict as needed
* using SMCR_EL2 and SMCR_EL1.
*/
- reg = SMCR_ELX_LEN_MASK;
+ reg = SMCR_ELX_LEN_MAX;
+
if (read_feat_sme_fa64_id_field() != 0U) {
VERBOSE("[SME] FA64 enabled\n");
reg |= SMCR_ELX_FA64_BIT;
}
+
+ /*
+ * Enable access to ZT0 register.
+ * Make sure FEAT_SME2 is supported by the hardware before continuing.
+ * If supported, Set the EZT0 bit in SMCR_EL3 to allow instructions to
+ * access ZT0 register without trapping.
+ */
+ if (is_feat_sme2_supported()) {
+ VERBOSE("SME2 enabled\n");
+ reg |= SMCR_ELX_EZT0_BIT;
+ }
write_smcr_el3(reg);
/* Reset CPTR_EL3 value. */