Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Madhukar Pappireddy | f4e6ea6 | 2020-01-27 15:32:15 -0600 | [diff] [blame] | 2 | * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
Dan Handley | ed6ff95 | 2014-05-14 17:44:19 +0100 | [diff] [blame] | 7 | #include <platform_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | |
| 9 | #include <lib/xlat_tables/xlat_tables_defs.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 10 | |
| 11 | OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) |
| 12 | OUTPUT_ARCH(PLATFORM_LINKER_ARCH) |
Jeenu Viswambharan | 2a30a75 | 2014-03-11 11:06:45 +0000 | [diff] [blame] | 13 | ENTRY(bl31_entrypoint) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 14 | |
| 15 | |
| 16 | MEMORY { |
Juan Castillo | fd8c077 | 2014-09-16 10:40:35 +0100 | [diff] [blame] | 17 | RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE |
Samuel Holland | 31a14e1 | 2018-10-17 21:40:18 -0500 | [diff] [blame] | 18 | #if SEPARATE_NOBITS_REGION |
| 19 | NOBITS (rw!a): ORIGIN = BL31_NOBITS_BASE, LENGTH = BL31_NOBITS_LIMIT - BL31_NOBITS_BASE |
| 20 | #else |
| 21 | #define NOBITS RAM |
| 22 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 23 | } |
| 24 | |
Caesar Wang | d90f43e | 2016-10-11 09:36:00 +0800 | [diff] [blame] | 25 | #ifdef PLAT_EXTRA_LD_SCRIPT |
| 26 | #include <plat.ld.S> |
| 27 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 28 | |
| 29 | SECTIONS |
| 30 | { |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 31 | . = BL31_BASE; |
Antonio Nino Diaz | 2ce2b09 | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 32 | ASSERT(. == ALIGN(PAGE_SIZE), |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 33 | "BL31_BASE address is not aligned on a page boundary.") |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 34 | |
Soby Mathew | 4e28c20 | 2018-10-14 08:09:22 +0100 | [diff] [blame] | 35 | __BL31_START__ = .; |
| 36 | |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 37 | #if SEPARATE_CODE_AND_RODATA |
| 38 | .text . : { |
| 39 | __TEXT_START__ = .; |
| 40 | *bl31_entrypoint.o(.text*) |
Samuel Holland | 23f5e54 | 2019-10-20 16:11:25 -0500 | [diff] [blame] | 41 | *(SORT_BY_ALIGNMENT(.text*)) |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 42 | *(.vectors) |
Roberto Vargas | d93fde3 | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 43 | . = ALIGN(PAGE_SIZE); |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 44 | __TEXT_END__ = .; |
| 45 | } >RAM |
| 46 | |
| 47 | .rodata . : { |
| 48 | __RODATA_START__ = .; |
Samuel Holland | 23f5e54 | 2019-10-20 16:11:25 -0500 | [diff] [blame] | 49 | *(SORT_BY_ALIGNMENT(.rodata*)) |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 50 | |
| 51 | /* Ensure 8-byte alignment for descriptors and ensure inclusion */ |
| 52 | . = ALIGN(8); |
| 53 | __RT_SVC_DESCS_START__ = .; |
| 54 | KEEP(*(rt_svc_descs)) |
| 55 | __RT_SVC_DESCS_END__ = .; |
| 56 | |
Madhukar Pappireddy | ae9677b | 2020-01-27 13:37:51 -0600 | [diff] [blame] | 57 | . = ALIGN(8); |
| 58 | __FCONF_POPULATOR_START__ = .; |
| 59 | KEEP(*(.fconf_populator)) |
| 60 | __FCONF_POPULATOR_END__ = .; |
| 61 | |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 62 | #if ENABLE_PMF |
| 63 | /* Ensure 8-byte alignment for descriptors and ensure inclusion */ |
| 64 | . = ALIGN(8); |
| 65 | __PMF_SVC_DESCS_START__ = .; |
| 66 | KEEP(*(pmf_svc_descs)) |
| 67 | __PMF_SVC_DESCS_END__ = .; |
| 68 | #endif /* ENABLE_PMF */ |
| 69 | |
| 70 | /* |
| 71 | * Ensure 8-byte alignment for cpu_ops so that its fields are also |
| 72 | * aligned. Also ensure cpu_ops inclusion. |
| 73 | */ |
| 74 | . = ALIGN(8); |
| 75 | __CPU_OPS_START__ = .; |
| 76 | KEEP(*(cpu_ops)) |
| 77 | __CPU_OPS_END__ = .; |
| 78 | |
Soby Mathew | 4e28c20 | 2018-10-14 08:09:22 +0100 | [diff] [blame] | 79 | /* |
Soby Mathew | 2b3fc1d | 2018-12-12 14:33:11 +0000 | [diff] [blame] | 80 | * Keep the .got section in the RO section as it is patched |
Soby Mathew | 4e28c20 | 2018-10-14 08:09:22 +0100 | [diff] [blame] | 81 | * prior to enabling the MMU and having the .got in RO is better for |
Soby Mathew | 2b3fc1d | 2018-12-12 14:33:11 +0000 | [diff] [blame] | 82 | * security. GOT is a table of addresses so ensure 8-byte alignment. |
Soby Mathew | 4e28c20 | 2018-10-14 08:09:22 +0100 | [diff] [blame] | 83 | */ |
Soby Mathew | 2b3fc1d | 2018-12-12 14:33:11 +0000 | [diff] [blame] | 84 | . = ALIGN(8); |
Soby Mathew | 4e28c20 | 2018-10-14 08:09:22 +0100 | [diff] [blame] | 85 | __GOT_START__ = .; |
| 86 | *(.got) |
| 87 | __GOT_END__ = .; |
| 88 | |
Jeenu Viswambharan | e3f2200 | 2017-09-22 08:32:10 +0100 | [diff] [blame] | 89 | /* Place pubsub sections for events */ |
| 90 | . = ALIGN(8); |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 91 | #include <lib/el3_runtime/pubsub_events.h> |
Jeenu Viswambharan | e3f2200 | 2017-09-22 08:32:10 +0100 | [diff] [blame] | 92 | |
Roberto Vargas | d93fde3 | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 93 | . = ALIGN(PAGE_SIZE); |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 94 | __RODATA_END__ = .; |
| 95 | } >RAM |
| 96 | #else |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 97 | ro . : { |
| 98 | __RO_START__ = .; |
Andrew Thoelke | e01ea34 | 2014-03-18 07:13:52 +0000 | [diff] [blame] | 99 | *bl31_entrypoint.o(.text*) |
Samuel Holland | 23f5e54 | 2019-10-20 16:11:25 -0500 | [diff] [blame] | 100 | *(SORT_BY_ALIGNMENT(.text*)) |
| 101 | *(SORT_BY_ALIGNMENT(.rodata*)) |
Achin Gupta | 7421b46 | 2014-02-01 18:53:26 +0000 | [diff] [blame] | 102 | |
Andrew Thoelke | e01ea34 | 2014-03-18 07:13:52 +0000 | [diff] [blame] | 103 | /* Ensure 8-byte alignment for descriptors and ensure inclusion */ |
Achin Gupta | 7421b46 | 2014-02-01 18:53:26 +0000 | [diff] [blame] | 104 | . = ALIGN(8); |
| 105 | __RT_SVC_DESCS_START__ = .; |
Andrew Thoelke | e01ea34 | 2014-03-18 07:13:52 +0000 | [diff] [blame] | 106 | KEEP(*(rt_svc_descs)) |
Achin Gupta | 7421b46 | 2014-02-01 18:53:26 +0000 | [diff] [blame] | 107 | __RT_SVC_DESCS_END__ = .; |
| 108 | |
Madhukar Pappireddy | ae9677b | 2020-01-27 13:37:51 -0600 | [diff] [blame] | 109 | . = ALIGN(8); |
| 110 | __FCONF_POPULATOR_START__ = .; |
| 111 | KEEP(*(.fconf_populator)) |
| 112 | __FCONF_POPULATOR_END__ = .; |
| 113 | |
Yatharth Kochar | 9518d02 | 2016-03-11 14:20:19 +0000 | [diff] [blame] | 114 | #if ENABLE_PMF |
| 115 | /* Ensure 8-byte alignment for descriptors and ensure inclusion */ |
| 116 | . = ALIGN(8); |
| 117 | __PMF_SVC_DESCS_START__ = .; |
| 118 | KEEP(*(pmf_svc_descs)) |
| 119 | __PMF_SVC_DESCS_END__ = .; |
| 120 | #endif /* ENABLE_PMF */ |
| 121 | |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 122 | /* |
| 123 | * Ensure 8-byte alignment for cpu_ops so that its fields are also |
| 124 | * aligned. Also ensure cpu_ops inclusion. |
| 125 | */ |
| 126 | . = ALIGN(8); |
| 127 | __CPU_OPS_START__ = .; |
| 128 | KEEP(*(cpu_ops)) |
| 129 | __CPU_OPS_END__ = .; |
| 130 | |
Soby Mathew | 2b3fc1d | 2018-12-12 14:33:11 +0000 | [diff] [blame] | 131 | /* |
| 132 | * Keep the .got section in the RO section as it is patched |
| 133 | * prior to enabling the MMU and having the .got in RO is better for |
| 134 | * security. GOT is a table of addresses so ensure 8-byte alignment. |
| 135 | */ |
| 136 | . = ALIGN(8); |
| 137 | __GOT_START__ = .; |
| 138 | *(.got) |
| 139 | __GOT_END__ = .; |
| 140 | |
Jeenu Viswambharan | e3f2200 | 2017-09-22 08:32:10 +0100 | [diff] [blame] | 141 | /* Place pubsub sections for events */ |
| 142 | . = ALIGN(8); |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 143 | #include <lib/el3_runtime/pubsub_events.h> |
Jeenu Viswambharan | e3f2200 | 2017-09-22 08:32:10 +0100 | [diff] [blame] | 144 | |
Achin Gupta | b739f22 | 2014-01-18 16:50:09 +0000 | [diff] [blame] | 145 | *(.vectors) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 146 | __RO_END_UNALIGNED__ = .; |
| 147 | /* |
| 148 | * Memory page(s) mapped to this section will be marked as read-only, |
| 149 | * executable. No RW data from the next section must creep in. |
| 150 | * Ensure the rest of the current memory page is unused. |
| 151 | */ |
Roberto Vargas | d93fde3 | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 152 | . = ALIGN(PAGE_SIZE); |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 153 | __RO_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 154 | } >RAM |
Sandrine Bailleux | f91f144 | 2016-07-08 14:37:40 +0100 | [diff] [blame] | 155 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 156 | |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 157 | ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, |
| 158 | "cpu_ops not defined for this platform.") |
| 159 | |
Paul Beesley | db4e25a | 2019-10-14 15:27:12 +0000 | [diff] [blame] | 160 | #if SPM_MM |
Ard Biesheuvel | 447d56f | 2019-01-06 10:07:24 +0100 | [diff] [blame] | 161 | #ifndef SPM_SHIM_EXCEPTIONS_VMA |
| 162 | #define SPM_SHIM_EXCEPTIONS_VMA RAM |
| 163 | #endif |
| 164 | |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 165 | /* |
| 166 | * Exception vectors of the SPM shim layer. They must be aligned to a 2K |
| 167 | * address, but we need to place them in a separate page so that we can set |
| 168 | * individual permissions to them, so the actual alignment needed is 4K. |
| 169 | * |
| 170 | * There's no need to include this into the RO section of BL31 because it |
| 171 | * doesn't need to be accessed by BL31. |
| 172 | */ |
Antonio Nino Diaz | 2ce2b09 | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 173 | spm_shim_exceptions : ALIGN(PAGE_SIZE) { |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 174 | __SPM_SHIM_EXCEPTIONS_START__ = .; |
| 175 | *(.spm_shim_exceptions) |
Roberto Vargas | d93fde3 | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 176 | . = ALIGN(PAGE_SIZE); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 177 | __SPM_SHIM_EXCEPTIONS_END__ = .; |
Ard Biesheuvel | 447d56f | 2019-01-06 10:07:24 +0100 | [diff] [blame] | 178 | } >SPM_SHIM_EXCEPTIONS_VMA AT>RAM |
| 179 | |
| 180 | PROVIDE(__SPM_SHIM_EXCEPTIONS_LMA__ = LOADADDR(spm_shim_exceptions)); |
| 181 | . = LOADADDR(spm_shim_exceptions) + SIZEOF(spm_shim_exceptions); |
Antonio Nino Diaz | c41f206 | 2017-10-24 10:07:35 +0100 | [diff] [blame] | 182 | #endif |
| 183 | |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 184 | /* |
| 185 | * Define a linker symbol to mark start of the RW memory area for this |
| 186 | * image. |
| 187 | */ |
| 188 | __RW_START__ = . ; |
| 189 | |
Douglas Raillard | 306593d | 2017-02-24 18:14:15 +0000 | [diff] [blame] | 190 | /* |
| 191 | * .data must be placed at a lower address than the stacks if the stack |
| 192 | * protector is enabled. Alternatively, the .data.stack_protector_canary |
| 193 | * section can be placed independently of the main .data section. |
| 194 | */ |
| 195 | .data . : { |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 196 | __DATA_START__ = .; |
Samuel Holland | 23f5e54 | 2019-10-20 16:11:25 -0500 | [diff] [blame] | 197 | *(SORT_BY_ALIGNMENT(.data*)) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 198 | __DATA_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 199 | } >RAM |
| 200 | |
Soby Mathew | 4e28c20 | 2018-10-14 08:09:22 +0100 | [diff] [blame] | 201 | /* |
| 202 | * .rela.dyn needs to come after .data for the read-elf utility to parse |
Soby Mathew | 2b3fc1d | 2018-12-12 14:33:11 +0000 | [diff] [blame] | 203 | * this section correctly. Ensure 8-byte alignment so that the fields of |
| 204 | * RELA data structure are aligned. |
Soby Mathew | 4e28c20 | 2018-10-14 08:09:22 +0100 | [diff] [blame] | 205 | */ |
Soby Mathew | 2b3fc1d | 2018-12-12 14:33:11 +0000 | [diff] [blame] | 206 | . = ALIGN(8); |
Soby Mathew | 4e28c20 | 2018-10-14 08:09:22 +0100 | [diff] [blame] | 207 | __RELA_START__ = .; |
| 208 | .rela.dyn . : { |
| 209 | } >RAM |
| 210 | __RELA_END__ = .; |
| 211 | |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 212 | #ifdef BL31_PROGBITS_LIMIT |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 213 | ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.") |
Sandrine Bailleux | e2e0c65 | 2014-06-16 16:12:27 +0100 | [diff] [blame] | 214 | #endif |
| 215 | |
Samuel Holland | 31a14e1 | 2018-10-17 21:40:18 -0500 | [diff] [blame] | 216 | #if SEPARATE_NOBITS_REGION |
| 217 | /* |
| 218 | * Define a linker symbol to mark end of the RW memory area for this |
| 219 | * image. |
| 220 | */ |
Madhukar Pappireddy | f4e6ea6 | 2020-01-27 15:32:15 -0600 | [diff] [blame] | 221 | . = ALIGN(PAGE_SIZE); |
Samuel Holland | 31a14e1 | 2018-10-17 21:40:18 -0500 | [diff] [blame] | 222 | __RW_END__ = .; |
| 223 | __BL31_END__ = .; |
| 224 | |
| 225 | ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") |
| 226 | |
| 227 | . = BL31_NOBITS_BASE; |
| 228 | ASSERT(. == ALIGN(PAGE_SIZE), |
| 229 | "BL31 NOBITS base address is not aligned on a page boundary.") |
| 230 | |
| 231 | __NOBITS_START__ = .; |
| 232 | #endif |
| 233 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 234 | stacks (NOLOAD) : { |
| 235 | __STACKS_START__ = .; |
| 236 | *(tzfw_normal_stacks) |
| 237 | __STACKS_END__ = .; |
Samuel Holland | 31a14e1 | 2018-10-17 21:40:18 -0500 | [diff] [blame] | 238 | } >NOBITS |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 239 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 240 | /* |
| 241 | * The .bss section gets initialised to 0 at runtime. |
Douglas Raillard | 21362a9 | 2016-12-02 13:51:54 +0000 | [diff] [blame] | 242 | * Its base address should be 16-byte aligned for better performance of the |
| 243 | * zero-initialization code. |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 244 | */ |
Andrew Thoelke | e466c9f | 2015-09-10 11:39:36 +0100 | [diff] [blame] | 245 | .bss (NOLOAD) : ALIGN(16) { |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 246 | __BSS_START__ = .; |
Samuel Holland | 23f5e54 | 2019-10-20 16:11:25 -0500 | [diff] [blame] | 247 | *(SORT_BY_ALIGNMENT(.bss*)) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 248 | *(COMMON) |
Andrew Thoelke | e466c9f | 2015-09-10 11:39:36 +0100 | [diff] [blame] | 249 | #if !USE_COHERENT_MEM |
| 250 | /* |
| 251 | * Bakery locks are stored in normal .bss memory |
| 252 | * |
| 253 | * Each lock's data is spread across multiple cache lines, one per CPU, |
| 254 | * but multiple locks can share the same cache line. |
| 255 | * The compiler will allocate enough memory for one CPU's bakery locks, |
| 256 | * the remaining cache lines are allocated by the linker script |
| 257 | */ |
| 258 | . = ALIGN(CACHE_WRITEBACK_GRANULE); |
| 259 | __BAKERY_LOCK_START__ = .; |
Varun Wadekar | 77c382c | 2019-01-30 08:26:20 -0800 | [diff] [blame] | 260 | __PERCPU_BAKERY_LOCK_START__ = .; |
Andrew Thoelke | e466c9f | 2015-09-10 11:39:36 +0100 | [diff] [blame] | 261 | *(bakery_lock) |
| 262 | . = ALIGN(CACHE_WRITEBACK_GRANULE); |
Varun Wadekar | 77c382c | 2019-01-30 08:26:20 -0800 | [diff] [blame] | 263 | __PERCPU_BAKERY_LOCK_END__ = .; |
| 264 | __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__); |
Andrew Thoelke | e466c9f | 2015-09-10 11:39:36 +0100 | [diff] [blame] | 265 | . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); |
| 266 | __BAKERY_LOCK_END__ = .; |
Roberto Vargas | 0099694 | 2017-11-13 13:41:58 +0000 | [diff] [blame] | 267 | |
| 268 | /* |
| 269 | * If BL31 doesn't use any bakery lock then __PERCPU_BAKERY_LOCK_SIZE__ |
| 270 | * will be zero. For this reason, the only two valid values for |
| 271 | * __PERCPU_BAKERY_LOCK_SIZE__ are 0 or the platform defined value |
| 272 | * PLAT_PERCPU_BAKERY_LOCK_SIZE. |
| 273 | */ |
Andrew Thoelke | e466c9f | 2015-09-10 11:39:36 +0100 | [diff] [blame] | 274 | #ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE |
Roberto Vargas | 0099694 | 2017-11-13 13:41:58 +0000 | [diff] [blame] | 275 | ASSERT((__PERCPU_BAKERY_LOCK_SIZE__ == 0) || (__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE), |
Andrew Thoelke | e466c9f | 2015-09-10 11:39:36 +0100 | [diff] [blame] | 276 | "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); |
| 277 | #endif |
| 278 | #endif |
Yatharth Kochar | 9518d02 | 2016-03-11 14:20:19 +0000 | [diff] [blame] | 279 | |
| 280 | #if ENABLE_PMF |
| 281 | /* |
| 282 | * Time-stamps are stored in normal .bss memory |
| 283 | * |
| 284 | * The compiler will allocate enough memory for one CPU's time-stamps, |
Paul Beesley | 1fbc97b | 2019-01-11 18:26:51 +0000 | [diff] [blame] | 285 | * the remaining memory for other CPUs is allocated by the |
Yatharth Kochar | 9518d02 | 2016-03-11 14:20:19 +0000 | [diff] [blame] | 286 | * linker script |
| 287 | */ |
| 288 | . = ALIGN(CACHE_WRITEBACK_GRANULE); |
| 289 | __PMF_TIMESTAMP_START__ = .; |
| 290 | KEEP(*(pmf_timestamp_array)) |
| 291 | . = ALIGN(CACHE_WRITEBACK_GRANULE); |
| 292 | __PMF_PERCPU_TIMESTAMP_END__ = .; |
| 293 | __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); |
| 294 | . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); |
| 295 | __PMF_TIMESTAMP_END__ = .; |
| 296 | #endif /* ENABLE_PMF */ |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 297 | __BSS_END__ = .; |
Samuel Holland | 31a14e1 | 2018-10-17 21:40:18 -0500 | [diff] [blame] | 298 | } >NOBITS |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 299 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 300 | /* |
Jeenu Viswambharan | 97cc9ee | 2014-02-24 15:20:28 +0000 | [diff] [blame] | 301 | * The xlat_table section is for full, aligned page tables (4K). |
Achin Gupta | a0cd989 | 2014-02-09 13:30:38 +0000 | [diff] [blame] | 302 | * Removing them from .bss avoids forcing 4K alignment on |
Antonio Nino Diaz | 7c2a3ca | 2018-02-23 15:07:54 +0000 | [diff] [blame] | 303 | * the .bss section. The tables are initialized to zero by the translation |
| 304 | * tables library. |
Achin Gupta | a0cd989 | 2014-02-09 13:30:38 +0000 | [diff] [blame] | 305 | */ |
| 306 | xlat_table (NOLOAD) : { |
| 307 | *(xlat_table) |
Samuel Holland | 31a14e1 | 2018-10-17 21:40:18 -0500 | [diff] [blame] | 308 | } >NOBITS |
Achin Gupta | a0cd989 | 2014-02-09 13:30:38 +0000 | [diff] [blame] | 309 | |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 310 | #if USE_COHERENT_MEM |
Achin Gupta | a0cd989 | 2014-02-09 13:30:38 +0000 | [diff] [blame] | 311 | /* |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 312 | * The base address of the coherent memory section must be page-aligned (4K) |
| 313 | * to guarantee that the coherent data are stored on their own pages and |
| 314 | * are not mixed with normal data. This is required to set up the correct |
| 315 | * memory attributes for the coherent data page tables. |
| 316 | */ |
Antonio Nino Diaz | 2ce2b09 | 2017-11-15 11:45:35 +0000 | [diff] [blame] | 317 | coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 318 | __COHERENT_RAM_START__ = .; |
Andrew Thoelke | e466c9f | 2015-09-10 11:39:36 +0100 | [diff] [blame] | 319 | /* |
| 320 | * Bakery locks are stored in coherent memory |
| 321 | * |
| 322 | * Each lock's data is contiguous and fully allocated by the compiler |
| 323 | */ |
| 324 | *(bakery_lock) |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 325 | *(tzfw_coherent_mem) |
| 326 | __COHERENT_RAM_END_UNALIGNED__ = .; |
| 327 | /* |
| 328 | * Memory page(s) mapped to this section will be marked |
| 329 | * as device memory. No other unexpected data must creep in. |
| 330 | * Ensure the rest of the current memory page is unused. |
| 331 | */ |
Roberto Vargas | d93fde3 | 2018-04-11 11:53:31 +0100 | [diff] [blame] | 332 | . = ALIGN(PAGE_SIZE); |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 333 | __COHERENT_RAM_END__ = .; |
Samuel Holland | 31a14e1 | 2018-10-17 21:40:18 -0500 | [diff] [blame] | 334 | } >NOBITS |
Soby Mathew | 2ae2043 | 2015-01-08 18:02:44 +0000 | [diff] [blame] | 335 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 336 | |
Samuel Holland | 31a14e1 | 2018-10-17 21:40:18 -0500 | [diff] [blame] | 337 | #if SEPARATE_NOBITS_REGION |
| 338 | /* |
| 339 | * Define a linker symbol to mark end of the NOBITS memory area for this |
| 340 | * image. |
| 341 | */ |
| 342 | __NOBITS_END__ = .; |
| 343 | |
| 344 | ASSERT(. <= BL31_NOBITS_LIMIT, "BL31 NOBITS region has exceeded its limit.") |
| 345 | #else |
Achin Gupta | e9c4a64 | 2015-09-11 16:03:13 +0100 | [diff] [blame] | 346 | /* |
| 347 | * Define a linker symbol to mark end of the RW memory area for this |
| 348 | * image. |
| 349 | */ |
| 350 | __RW_END__ = .; |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 351 | __BL31_END__ = .; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 352 | |
Masahiro Yamada | d3e7baa | 2020-01-17 13:44:50 +0900 | [diff] [blame] | 353 | /DISCARD/ : { |
| 354 | *(.dynsym .dynstr .hash .gnu.hash) |
| 355 | } |
| 356 | |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 357 | ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") |
Samuel Holland | 31a14e1 | 2018-10-17 21:40:18 -0500 | [diff] [blame] | 358 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 359 | } |