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Juan Castillo0c70c572014-08-12 13:04:43 +01001/*
Alexei Fedorovaad60c82020-01-10 14:24:17 +00002 * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved.
Dan Handleyed6ff952014-05-14 17:44:19 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handleyed6ff952014-05-14 17:44:19 +01005 */
6
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01007#ifndef FVP_DEF_H
8#define FVP_DEF_H
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils_def.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010011
Soby Mathew47e43f22016-02-01 14:04:34 +000012#ifndef FVP_CLUSTER_COUNT
Alexei Fedorovaad60c82020-01-10 14:24:17 +000013#error "FVP_CLUSTER_COUNT is not set in makefile"
Soby Mathew47e43f22016-02-01 14:04:34 +000014#endif
Jeenu Viswambharan75421132018-01-31 14:52:08 +000015
16#ifndef FVP_MAX_CPUS_PER_CLUSTER
Alexei Fedorovaad60c82020-01-10 14:24:17 +000017#error "FVP_MAX_CPUS_PER_CLUSTER is not set in makefile"
Jeenu Viswambharan75421132018-01-31 14:52:08 +000018#endif
Dan Handley2b6b5742015-03-19 19:17:53 +000019
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000020#ifndef FVP_MAX_PE_PER_CPU
Alexei Fedorovaad60c82020-01-10 14:24:17 +000021#error "FVP_MAX_PE_PER_CPU is not set in makefile"
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000022#endif
23
Dan Handley2b6b5742015-03-19 19:17:53 +000024#define FVP_PRIMARY_CPU 0x0
Juan Castillo0c70c572014-08-12 13:04:43 +010025
Soby Mathew7356b1e2016-03-24 10:12:42 +000026/* Defines for the Interconnect build selection */
27#define FVP_CCI 1
28#define FVP_CCN 2
29
Manish V Badarkhea637c3f2020-08-04 17:09:10 +010030/******************************************************************************
31 * Definition of platform soc id
32 *****************************************************************************/
33#define FVP_SOC_ID 0
34
Dan Handleyed6ff952014-05-14 17:44:19 +010035/*******************************************************************************
36 * FVP memory map related constants
37 ******************************************************************************/
38
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +000039#define FLASH1_BASE UL(0x0c000000)
40#define FLASH1_SIZE UL(0x04000000)
Juan Castillo0c70c572014-08-12 13:04:43 +010041
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +000042#define PSRAM_BASE UL(0x14000000)
43#define PSRAM_SIZE UL(0x04000000)
Juan Castillo42a617d2014-09-24 10:00:06 +010044
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +000045#define VRAM_BASE UL(0x18000000)
46#define VRAM_SIZE UL(0x02000000)
Dan Handleyed6ff952014-05-14 17:44:19 +010047
48/* Aggregate of all devices in the first GB */
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +000049#define DEVICE0_BASE UL(0x20000000)
50#define DEVICE0_SIZE UL(0x0c200000)
Dan Handleyed6ff952014-05-14 17:44:19 +010051
Soby Mathew7356b1e2016-03-24 10:12:42 +000052/*
53 * In case of FVP models with CCN, the CCN register space overlaps into
54 * the NSRAM area.
55 */
56#if FVP_INTERCONNECT_DRIVER == FVP_CCN
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +000057#define DEVICE1_BASE UL(0x2e000000)
58#define DEVICE1_SIZE UL(0x1A00000)
Soby Mathew7356b1e2016-03-24 10:12:42 +000059#else
Alexei Fedorov4d6e7fb2020-02-24 10:39:31 +000060#define DEVICE1_BASE BASE_GICD_BASE
Alexei Fedorovfc4f80e2020-04-07 11:48:00 +010061
62#if GIC_ENABLE_V4_EXTN
63/* GICv4 mapping: GICD + CORE_COUNT * 256KB */
64#define DEVICE1_SIZE ((BASE_GICR_BASE - BASE_GICD_BASE) + \
65 (PLATFORM_CORE_COUNT * 0x40000))
66#else
67/* GICv2 and GICv3 mapping: GICD + CORE_COUNT * 128KB */
Alexei Fedorov4d6e7fb2020-02-24 10:39:31 +000068#define DEVICE1_SIZE ((BASE_GICR_BASE - BASE_GICD_BASE) + \
69 (PLATFORM_CORE_COUNT * 0x20000))
Alexei Fedorovfc4f80e2020-04-07 11:48:00 +010070#endif /* GIC_ENABLE_V4_EXTN */
71
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +000072#define NSRAM_BASE UL(0x2e000000)
73#define NSRAM_SIZE UL(0x10000)
Soby Mathew7356b1e2016-03-24 10:12:42 +000074#endif
Juan Castillo31a68f02015-04-14 12:49:03 +010075/* Devices in the second GB */
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +000076#define DEVICE2_BASE UL(0x7fe00000)
77#define DEVICE2_SIZE UL(0x00200000)
Juan Castillo31a68f02015-04-14 12:49:03 +010078
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +000079#define PCIE_EXP_BASE UL(0x40000000)
80#define TZRNG_BASE UL(0x7fe60000)
Juan Castillobfb7fa62016-01-22 11:05:57 +000081
82/* Non-volatile counters */
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +000083#define TRUSTED_NVCTR_BASE UL(0x7fe70000)
84#define TFW_NVCTR_BASE (TRUSTED_NVCTR_BASE + UL(0x0000))
85#define TFW_NVCTR_SIZE UL(4)
86#define NTFW_CTR_BASE (TRUSTED_NVCTR_BASE + UL(0x0004))
87#define NTFW_CTR_SIZE UL(4)
Juan Castillo31a68f02015-04-14 12:49:03 +010088
89/* Keys */
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +000090#define SOC_KEYS_BASE UL(0x7fe80000)
91#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + UL(0x0000))
92#define TZ_PUB_KEY_HASH_SIZE UL(32)
93#define HU_KEY_BASE (SOC_KEYS_BASE + UL(0x0020))
94#define HU_KEY_SIZE UL(16)
95#define END_KEY_BASE (SOC_KEYS_BASE + UL(0x0044))
96#define END_KEY_SIZE UL(32)
Juan Castillof3e02182014-12-19 09:28:30 +000097
Dan Handley2b6b5742015-03-19 19:17:53 +000098/* Constants to distinguish FVP type */
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +000099#define HBI_BASE_FVP U(0x020)
100#define REV_BASE_FVP_V0 U(0x0)
101#define REV_BASE_FVP_REVC U(0x2)
Juan Castillof3e02182014-12-19 09:28:30 +0000102
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +0000103#define HBI_FOUNDATION_FVP U(0x010)
104#define REV_FOUNDATION_FVP_V2_0 U(0x0)
105#define REV_FOUNDATION_FVP_V2_1 U(0x1)
106#define REV_FOUNDATION_FVP_v9_1 U(0x2)
107#define REV_FOUNDATION_FVP_v9_6 U(0x3)
Dan Handleyed6ff952014-05-14 17:44:19 +0100108
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +0000109#define BLD_GIC_VE_MMAP U(0x0)
110#define BLD_GIC_A53A57_MMAP U(0x1)
Dan Handleyed6ff952014-05-14 17:44:19 +0100111
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +0000112#define ARCH_MODEL U(0x1)
Dan Handleyed6ff952014-05-14 17:44:19 +0100113
114/* FVP Power controller base address*/
Sathees Balya50905c72018-10-05 13:30:59 +0100115#define PWRC_BASE UL(0x1c100000)
Dan Handleyed6ff952014-05-14 17:44:19 +0100116
Ryan Harkinf96fc8f2015-03-17 14:54:01 +0000117/* FVP SP804 timer frequency is 35 MHz*/
Juan Castillofd383b42015-12-01 16:10:15 +0000118#define SP804_TIMER_CLKMULT 1
119#define SP804_TIMER_CLKDIV 35
120
121/* SP810 controller. FVP specific flags */
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +0000122#define FVP_SP810_CTRL_TIM0_OV BIT_32(16)
123#define FVP_SP810_CTRL_TIM1_OV BIT_32(18)
124#define FVP_SP810_CTRL_TIM2_OV BIT_32(20)
125#define FVP_SP810_CTRL_TIM3_OV BIT_32(22)
Dan Handleyed6ff952014-05-14 17:44:19 +0100126
127/*******************************************************************************
Alexei Fedorov4d6e7fb2020-02-24 10:39:31 +0000128 * GIC & interrupt handling related constants
Dan Handleyed6ff952014-05-14 17:44:19 +0100129 ******************************************************************************/
130/* VE compatible GIC memory map */
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +0000131#define VE_GICD_BASE UL(0x2c001000)
132#define VE_GICC_BASE UL(0x2c002000)
133#define VE_GICH_BASE UL(0x2c004000)
134#define VE_GICV_BASE UL(0x2c006000)
Dan Handleyed6ff952014-05-14 17:44:19 +0100135
136/* Base FVP compatible GIC memory map */
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +0000137#define BASE_GICD_BASE UL(0x2f000000)
138#define BASE_GICR_BASE UL(0x2f100000)
139#define BASE_GICC_BASE UL(0x2c000000)
140#define BASE_GICH_BASE UL(0x2c010000)
141#define BASE_GICV_BASE UL(0x2c02f000)
Dan Handleyed6ff952014-05-14 17:44:19 +0100142
Vikram Kanigirif3bcea22015-06-24 17:51:09 +0100143#define FVP_IRQ_TZ_WDOG 56
144#define FVP_IRQ_SEC_SYS_TIMER 57
Soby Mathew69817f72014-07-14 15:43:21 +0100145
Dan Handleyed6ff952014-05-14 17:44:19 +0100146/*******************************************************************************
147 * TrustZone address space controller related constants
148 ******************************************************************************/
Dan Handleyed6ff952014-05-14 17:44:19 +0100149
Dan Handleyed6ff952014-05-14 17:44:19 +0100150/* NSAIDs used by devices in TZC filter 0 on FVP */
151#define FVP_NSAID_DEFAULT 0
152#define FVP_NSAID_PCI 1
153#define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */
154#define FVP_NSAID_AP 9 /* Application Processors */
155#define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */
156
157/* NSAIDs used by devices in TZC filter 2 on FVP */
158#define FVP_NSAID_HDLCD0 2
159#define FVP_NSAID_CLCD 7
160
Roberto Vargasbcca6c62018-06-11 16:15:35 +0100161/*******************************************************************************
162 * Memprotect definitions
163 ******************************************************************************/
164/* PSCI memory protect definitions:
165 * This variable is stored in a non-secure flash because some ARM reference
166 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT
167 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions.
168 */
169#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
170 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
171
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100172#endif /* FVP_DEF_H */