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Yann Gautier4b0c72a2018-07-16 10:54:09 +02001/*
Yann Gautiera45433b2019-01-16 18:31:00 +01002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Yann Gautier4b0c72a2018-07-16 10:54:09 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Yann Gautier4b0c72a2018-07-16 10:54:09 +02007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <string.h>
9
Yann Gautier4b0c72a2018-07-16 10:54:09 +020010#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011
12#include <arch_helpers.h>
13#include <common/bl_common.h>
14#include <common/debug.h>
15#include <common/desc_image_load.h>
16#include <drivers/delay_timer.h>
17#include <drivers/generic_delay_timer.h>
Yann Gautier3edc7c32019-05-20 19:17:08 +020018#include <drivers/st/bsec.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000019#include <drivers/st/stm32_console.h>
Yann Gautier091eab52019-06-04 18:06:34 +020020#include <drivers/st/stm32_iwdg.h>
Yann Gautiera45433b2019-01-16 18:31:00 +010021#include <drivers/st/stm32mp_pmic.h>
Yann Gautiera2e2a302019-02-14 11:13:39 +010022#include <drivers/st/stm32mp_reset.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000023#include <drivers/st/stm32mp1_clk.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000024#include <drivers/st/stm32mp1_pwr.h>
25#include <drivers/st/stm32mp1_ram.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000026#include <lib/mmio.h>
Yann Gautierb3386f72019-04-19 09:41:01 +020027#include <lib/optee_utils.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000028#include <lib/xlat_tables/xlat_tables_v2.h>
29#include <plat/common/platform.h>
30
Yann Gautier8593e442018-11-14 18:46:15 +010031#include <stm32mp1_context.h>
Yann Gautier091eab52019-06-04 18:06:34 +020032#include <stm32mp1_dbgmcu.h>
Yann Gautier4b0c72a2018-07-16 10:54:09 +020033
Andre Przywara678c6fa2020-01-25 00:58:35 +000034static console_t console;
Lionel Debieve7bd96f42019-09-03 12:22:23 +020035static struct stm32mp_auth_ops stm32mp1_auth_ops;
Yann Gautier8593e442018-11-14 18:46:15 +010036
Yann Gautierf9d40d52019-01-17 14:41:46 +010037static void print_reset_reason(void)
38{
Yann Gautier3d78a2e2019-02-14 11:01:20 +010039 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR);
Yann Gautierf9d40d52019-01-17 14:41:46 +010040
41 if (rstsr == 0U) {
42 WARN("Reset reason unknown\n");
43 return;
44 }
45
46 INFO("Reset reason (0x%x):\n", rstsr);
47
48 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) {
49 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) {
50 INFO("System exits from STANDBY\n");
51 return;
52 }
53
54 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) {
55 INFO("MPU exits from CSTANDBY\n");
56 return;
57 }
58 }
59
60 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) {
61 INFO(" Power-on Reset (rst_por)\n");
62 return;
63 }
64
65 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) {
66 INFO(" Brownout Reset (rst_bor)\n");
67 return;
68 }
69
70 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) {
71 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
72 INFO(" System reset generated by MCU (MCSYSRST)\n");
73 } else {
74 INFO(" Local reset generated by MCU (MCSYSRST)\n");
75 }
76 return;
77 }
78
79 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) {
80 INFO(" System reset generated by MPU (MPSYSRST)\n");
81 return;
82 }
83
84 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) {
85 INFO(" Reset due to a clock failure on HSE\n");
86 return;
87 }
88
89 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) {
90 INFO(" IWDG1 Reset (rst_iwdg1)\n");
91 return;
92 }
93
94 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) {
95 INFO(" IWDG2 Reset (rst_iwdg2)\n");
96 return;
97 }
98
99 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) {
100 INFO(" MPU Processor 0 Reset\n");
101 return;
102 }
103
104 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) {
105 INFO(" MPU Processor 1 Reset\n");
106 return;
107 }
108
109 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) {
110 INFO(" Pad Reset from NRST\n");
111 return;
112 }
113
114 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) {
115 INFO(" Reset due to a failure of VDD_CORE\n");
116 return;
117 }
118
119 ERROR(" Unidentified reset reason\n");
120}
121
122void bl2_el3_early_platform_setup(u_register_t arg0,
123 u_register_t arg1 __unused,
124 u_register_t arg2 __unused,
125 u_register_t arg3 __unused)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200126{
Yann Gautiera2e2a302019-02-14 11:13:39 +0100127 stm32mp_save_boot_ctx_address(arg0);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200128}
129
130void bl2_platform_setup(void)
131{
Yann Gautiercaf575b2018-07-24 17:18:19 +0200132 int ret;
133
Yann Gautierf3928f62019-02-14 11:15:03 +0100134 if (dt_pmic_status() > 0) {
Yann Gautierbb836ee2018-07-16 17:55:07 +0200135 initialize_pmic();
136 }
137
Yann Gautiercaf575b2018-07-24 17:18:19 +0200138 ret = stm32mp1_ddr_probe();
139 if (ret < 0) {
140 ERROR("Invalid DDR init: error %d\n", ret);
141 panic();
142 }
143
Yann Gautierb3386f72019-04-19 09:41:01 +0200144#ifdef AARCH32_SP_OPTEE
145 INFO("BL2 runs OP-TEE setup\n");
146 /* Initialize tzc400 after DDR initialization */
147 stm32mp1_security_setup();
148#else
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200149 INFO("BL2 runs SP_MIN setup\n");
Yann Gautierb3386f72019-04-19 09:41:01 +0200150#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200151}
152
153void bl2_el3_plat_arch_setup(void)
154{
Yann Gautier69035a82018-07-05 16:48:16 +0200155 int32_t result;
Yann Gautierf9d40d52019-01-17 14:41:46 +0100156 struct dt_node_info dt_uart_info;
Yann Gautier69035a82018-07-05 16:48:16 +0200157 const char *board_model;
Yann Gautier41934662018-07-20 11:36:05 +0200158 boot_api_context_t *boot_context =
Yann Gautiera2e2a302019-02-14 11:13:39 +0100159 (boot_api_context_t *)stm32mp_get_boot_ctx_address();
Yann Gautier69035a82018-07-05 16:48:16 +0200160 uint32_t clk_rate;
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100161 uintptr_t pwr_base;
162 uintptr_t rcc_base;
Yann Gautier41934662018-07-20 11:36:05 +0200163
Yann Gautierf9d40d52019-01-17 14:41:46 +0100164 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
165 BL_CODE_END - BL_CODE_BASE,
166 MT_CODE | MT_SECURE);
167
Yann Gautierb3386f72019-04-19 09:41:01 +0200168#ifdef AARCH32_SP_OPTEE
169 /* OP-TEE image needs post load processing: keep RAM read/write */
170 mmap_add_region(STM32MP_DDR_BASE + dt_get_ddr_size() -
171 STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE,
172 STM32MP_DDR_BASE + dt_get_ddr_size() -
173 STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE,
174 STM32MP_DDR_S_SIZE,
175 MT_MEMORY | MT_RW | MT_SECURE);
176
177 mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE,
178 STM32MP_OPTEE_SIZE,
179 MT_MEMORY | MT_RW | MT_SECURE);
180#else
Yann Gautierf9d40d52019-01-17 14:41:46 +0100181 /* Prevent corruption of preloaded BL32 */
182 mmap_add_region(BL32_BASE, BL32_BASE,
183 BL32_LIMIT - BL32_BASE,
184 MT_MEMORY | MT_RO | MT_SECURE);
185
Yann Gautierb3386f72019-04-19 09:41:01 +0200186#endif
Yann Gautierf9d40d52019-01-17 14:41:46 +0100187 /* Map non secure DDR for BL33 load and DDR training area restore */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100188 mmap_add_region(STM32MP_DDR_BASE,
189 STM32MP_DDR_BASE,
190 STM32MP_DDR_MAX_SIZE,
Yann Gautierf9d40d52019-01-17 14:41:46 +0100191 MT_MEMORY | MT_RW | MT_NS);
192
193 /* Prevent corruption of preloaded Device Tree */
194 mmap_add_region(DTB_BASE, DTB_BASE,
195 DTB_LIMIT - DTB_BASE,
196 MT_MEMORY | MT_RO | MT_SECURE);
197
198 configure_mmu();
199
200 if (dt_open_and_check() < 0) {
201 panic();
202 }
203
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100204 pwr_base = stm32mp_pwr_base();
205 rcc_base = stm32mp_rcc_base();
206
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200207 /*
208 * Disable the backup domain write protection.
209 * The protection is enable at each reset by hardware
210 * and must be disabled by software.
211 */
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100212 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200213
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100214 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) {
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200215 ;
216 }
217
Yann Gautier3edc7c32019-05-20 19:17:08 +0200218 if (bsec_probe() != 0) {
219 panic();
220 }
221
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200222 /* Reset backup domain on cold boot cases */
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100223 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) {
224 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200225
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100226 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) ==
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200227 0U) {
228 ;
229 }
230
Yann Gautier3d78a2e2019-02-14 11:01:20 +0100231 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200232 }
233
Yann Gautiered342322019-02-15 17:33:27 +0100234 /* Disable MCKPROT */
235 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT);
236
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200237 generic_delay_timer_init();
238
Yann Gautier9aea69e2018-07-24 17:13:36 +0200239 if (stm32mp1_clk_probe() < 0) {
240 panic();
241 }
242
243 if (stm32mp1_clk_init() < 0) {
244 panic();
245 }
246
Yann Gautier3edc7c32019-05-20 19:17:08 +0200247 stm32mp1_syscfg_init();
248
Yann Gautierf9d40d52019-01-17 14:41:46 +0100249 result = dt_get_stdout_uart_info(&dt_uart_info);
Yann Gautier69035a82018-07-05 16:48:16 +0200250
251 if ((result <= 0) ||
Yann Gautierf9d40d52019-01-17 14:41:46 +0100252 (dt_uart_info.status == 0U) ||
253 (dt_uart_info.clock < 0) ||
254 (dt_uart_info.reset < 0)) {
Yann Gautier69035a82018-07-05 16:48:16 +0200255 goto skip_console_init;
256 }
257
258 if (dt_set_stdout_pinctrl() != 0) {
259 goto skip_console_init;
260 }
261
Yann Gautiere4a3c352019-02-14 10:53:33 +0100262 stm32mp_clk_enable((unsigned long)dt_uart_info.clock);
Yann Gautier69035a82018-07-05 16:48:16 +0200263
Yann Gautiera2e2a302019-02-14 11:13:39 +0100264 stm32mp_reset_assert((uint32_t)dt_uart_info.reset);
Yann Gautier69035a82018-07-05 16:48:16 +0200265 udelay(2);
Yann Gautiera2e2a302019-02-14 11:13:39 +0100266 stm32mp_reset_deassert((uint32_t)dt_uart_info.reset);
Yann Gautier69035a82018-07-05 16:48:16 +0200267 mdelay(1);
268
Yann Gautiera2e2a302019-02-14 11:13:39 +0100269 clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock);
Yann Gautier69035a82018-07-05 16:48:16 +0200270
Yann Gautierf9d40d52019-01-17 14:41:46 +0100271 if (console_stm32_register(dt_uart_info.base, clk_rate,
Yann Gautiera2e2a302019-02-14 11:13:39 +0100272 STM32MP_UART_BAUDRATE, &console) == 0) {
Yann Gautier69035a82018-07-05 16:48:16 +0200273 panic();
274 }
275
Andre Przywara678c6fa2020-01-25 00:58:35 +0000276 console_set_scope(&console, CONSOLE_FLAG_BOOT |
Yann Gautiera30e5f72019-09-04 11:55:10 +0200277 CONSOLE_FLAG_CRASH | CONSOLE_FLAG_TRANSLATE_CRLF);
278
Yann Gautierc7374052019-06-04 18:02:37 +0200279 stm32mp_print_cpuinfo();
280
Yann Gautier69035a82018-07-05 16:48:16 +0200281 board_model = dt_get_board_model();
282 if (board_model != NULL) {
Yann Gautierf9d40d52019-01-17 14:41:46 +0100283 NOTICE("Model: %s\n", board_model);
Yann Gautier69035a82018-07-05 16:48:16 +0200284 }
285
Yann Gautier35dc0772019-05-13 18:34:48 +0200286 stm32mp_print_boardinfo();
287
Lionel Debieve7bd96f42019-09-03 12:22:23 +0200288 if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) {
289 NOTICE("Bootrom authentication %s\n",
290 (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ?
291 "failed" : "succeeded");
292 }
293
Yann Gautier69035a82018-07-05 16:48:16 +0200294skip_console_init:
Yann Gautier091eab52019-06-04 18:06:34 +0200295 if (stm32_iwdg_init() < 0) {
296 panic();
297 }
298
299 stm32_iwdg_refresh();
300
301 result = stm32mp1_dbgmcu_freeze_iwdg2();
302 if (result != 0) {
303 INFO("IWDG2 freeze error : %i\n", result);
304 }
Yann Gautier69035a82018-07-05 16:48:16 +0200305
Yann Gautier41934662018-07-20 11:36:05 +0200306 if (stm32_save_boot_interface(boot_context->boot_interface_selected,
307 boot_context->boot_interface_instance) !=
308 0) {
309 ERROR("Cannot save boot interface\n");
310 }
311
Lionel Debieve7bd96f42019-09-03 12:22:23 +0200312 stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key;
313 stm32mp1_auth_ops.verify_signature =
314 boot_context->bootrom_ecdsa_verify_signature;
315
316 stm32mp_init_auth(&stm32mp1_auth_ops);
317
Yann Gautiercaf575b2018-07-24 17:18:19 +0200318 stm32mp1_arch_security_setup();
319
Yann Gautierf9d40d52019-01-17 14:41:46 +0100320 print_reset_reason();
321
Yann Gautiera2e2a302019-02-14 11:13:39 +0100322 stm32mp_io_setup();
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200323}
Yann Gautierb3386f72019-04-19 09:41:01 +0200324
325#if defined(AARCH32_SP_OPTEE)
326/*******************************************************************************
327 * This function can be used by the platforms to update/use image
328 * information for given `image_id`.
329 ******************************************************************************/
330int bl2_plat_handle_post_image_load(unsigned int image_id)
331{
332 int err = 0;
333 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
334 bl_mem_params_node_t *bl32_mem_params;
335 bl_mem_params_node_t *pager_mem_params;
336 bl_mem_params_node_t *paged_mem_params;
337
338 assert(bl_mem_params != NULL);
339
340 switch (image_id) {
341 case BL32_IMAGE_ID:
342 bl_mem_params->ep_info.pc =
343 bl_mem_params->image_info.image_base;
344
345 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
346 assert(pager_mem_params != NULL);
347 pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE;
348 pager_mem_params->image_info.image_max_size =
349 STM32MP_OPTEE_SIZE;
350
351 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
352 assert(paged_mem_params != NULL);
353 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE +
354 (dt_get_ddr_size() - STM32MP_DDR_S_SIZE -
355 STM32MP_DDR_SHMEM_SIZE);
356 paged_mem_params->image_info.image_max_size =
357 STM32MP_DDR_S_SIZE;
358
359 err = parse_optee_header(&bl_mem_params->ep_info,
360 &pager_mem_params->image_info,
361 &paged_mem_params->image_info);
362 if (err) {
363 ERROR("OPTEE header parse error.\n");
364 panic();
365 }
366
367 /* Set optee boot info from parsed header data */
368 bl_mem_params->ep_info.pc =
369 pager_mem_params->image_info.image_base;
370 bl_mem_params->ep_info.args.arg0 =
371 paged_mem_params->image_info.image_base;
372 bl_mem_params->ep_info.args.arg1 = 0; /* Unused */
373 bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */
374 break;
375
376 case BL33_IMAGE_ID:
377 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
378 assert(bl32_mem_params != NULL);
379 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
380 break;
381
382 default:
383 /* Do nothing in default case */
384 break;
385 }
386
387 return err;
388}
389#endif