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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Vikram Kanigirifbb13012016-02-15 11:54:14 +00002 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handley2b6b5742015-03-19 19:17:53 +000031#include <arm_config.h>
32#include <arm_def.h>
Soby Mathew7356b1e2016-03-24 10:12:42 +000033#include <ccn.h>
Dan Handley714a0d22014-04-09 13:13:04 +010034#include <debug.h>
Achin Gupta1fa7eb62015-11-03 14:18:34 +000035#include <gicv2.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010036#include <mmio.h>
Dan Handley2b6b5742015-03-19 19:17:53 +000037#include <plat_arm.h>
38#include <v2m_def.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010039#include "../fvp_def.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010040
Achin Gupta1fa7eb62015-11-03 14:18:34 +000041/* Defines for GIC Driver build time selection */
42#define FVP_GICV2 1
43#define FVP_GICV3 2
44#define FVP_GICV3_LEGACY 3
45
Achin Gupta4f6ad662013-10-25 09:08:21 +010046/*******************************************************************************
Dan Handley2b6b5742015-03-19 19:17:53 +000047 * arm_config holds the characteristics of the differences between the three FVP
48 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
Vikram Kanigirifbb13012016-02-15 11:54:14 +000049 * at each boot stage by the primary before enabling the MMU (to allow
50 * interconnect configuration) & used thereafter. Each BL will have its own copy
51 * to allow independent operation.
Achin Gupta4f6ad662013-10-25 09:08:21 +010052 ******************************************************************************/
Dan Handley2b6b5742015-03-19 19:17:53 +000053arm_config_t arm_config;
Soby Mathewb08bc042014-09-03 17:48:44 +010054
55#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
56 DEVICE0_SIZE, \
57 MT_DEVICE | MT_RW | MT_SECURE)
58
59#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
60 DEVICE1_SIZE, \
61 MT_DEVICE | MT_RW | MT_SECURE)
62
Juan Castillo31a68f02015-04-14 12:49:03 +010063#define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \
64 DEVICE2_SIZE, \
Antonio Nino Diaz9d602fe2016-05-20 14:14:16 +010065 MT_DEVICE | MT_RW | MT_SECURE)
Juan Castillo31a68f02015-04-14 12:49:03 +010066
67
Jon Medhurstb1eb0932014-02-26 16:27:53 +000068/*
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010069 * Table of memory regions for various BL stages to map using the MMU.
70 * This doesn't include Trusted SRAM as arm_setup_page_tables() already
71 * takes care of mapping it.
Sandrine Bailleux889ca032016-06-14 17:01:00 +010072 *
73 * The flash needs to be mapped as writable in order to erase the FIP's Table of
74 * Contents in case of unrecoverable error (see plat_error_handler()).
Jon Medhurstb1eb0932014-02-26 16:27:53 +000075 */
Soby Mathewb08bc042014-09-03 17:48:44 +010076#if IMAGE_BL1
Dan Handley2b6b5742015-03-19 19:17:53 +000077const mmap_region_t plat_arm_mmap[] = {
78 ARM_MAP_SHARED_RAM,
Juan Castillob6132f12015-10-06 14:01:35 +010079 V2M_MAP_FLASH0_RW,
Dan Handley2b6b5742015-03-19 19:17:53 +000080 V2M_MAP_IOFPGA,
Soby Mathewb08bc042014-09-03 17:48:44 +010081 MAP_DEVICE0,
82 MAP_DEVICE1,
Juan Castillo31a68f02015-04-14 12:49:03 +010083 MAP_DEVICE2,
Yatharth Kochar736a3bf2015-10-11 14:14:55 +010084#if TRUSTED_BOARD_BOOT
85 ARM_MAP_NS_DRAM1,
86#endif
Soby Mathewb08bc042014-09-03 17:48:44 +010087 {0}
88};
89#endif
90#if IMAGE_BL2
Dan Handley2b6b5742015-03-19 19:17:53 +000091const mmap_region_t plat_arm_mmap[] = {
92 ARM_MAP_SHARED_RAM,
Juan Castillob6132f12015-10-06 14:01:35 +010093 V2M_MAP_FLASH0_RW,
Dan Handley2b6b5742015-03-19 19:17:53 +000094 V2M_MAP_IOFPGA,
Soby Mathewb08bc042014-09-03 17:48:44 +010095 MAP_DEVICE0,
96 MAP_DEVICE1,
Juan Castillo31a68f02015-04-14 12:49:03 +010097 MAP_DEVICE2,
Dan Handley2b6b5742015-03-19 19:17:53 +000098 ARM_MAP_NS_DRAM1,
99 ARM_MAP_TSP_SEC_MEM,
David Wang0ba499f2016-03-07 11:02:57 +0800100#if ARM_BL31_IN_DRAM
101 ARM_MAP_BL31_SEC_DRAM,
102#endif
Soby Mathewb08bc042014-09-03 17:48:44 +0100103 {0}
104};
105#endif
Yatharth Kochar3a11eda2015-10-14 15:28:11 +0100106#if IMAGE_BL2U
107const mmap_region_t plat_arm_mmap[] = {
108 MAP_DEVICE0,
109 V2M_MAP_IOFPGA,
110 {0}
111};
112#endif
Soby Mathewb08bc042014-09-03 17:48:44 +0100113#if IMAGE_BL31
Dan Handley2b6b5742015-03-19 19:17:53 +0000114const mmap_region_t plat_arm_mmap[] = {
115 ARM_MAP_SHARED_RAM,
116 V2M_MAP_IOFPGA,
Soby Mathewb08bc042014-09-03 17:48:44 +0100117 MAP_DEVICE0,
118 MAP_DEVICE1,
119 {0}
120};
121#endif
122#if IMAGE_BL32
Dan Handley2b6b5742015-03-19 19:17:53 +0000123const mmap_region_t plat_arm_mmap[] = {
Soby Mathew0d268dc2016-07-11 14:13:56 +0100124#ifdef AARCH32
125 ARM_MAP_SHARED_RAM,
126#endif
Dan Handley2b6b5742015-03-19 19:17:53 +0000127 V2M_MAP_IOFPGA,
Soby Mathewb08bc042014-09-03 17:48:44 +0100128 MAP_DEVICE0,
129 MAP_DEVICE1,
Jon Medhurstb1eb0932014-02-26 16:27:53 +0000130 {0}
131};
Soby Mathewb08bc042014-09-03 17:48:44 +0100132#endif
Jon Medhurstb1eb0932014-02-26 16:27:53 +0000133
Dan Handley2b6b5742015-03-19 19:17:53 +0000134ARM_CASSERT_MMAP
Soby Mathew13ee9682015-01-22 11:22:22 +0000135
Achin Gupta4f6ad662013-10-25 09:08:21 +0100136
Achin Gupta4f6ad662013-10-25 09:08:21 +0100137/*******************************************************************************
138 * A single boot loader stack is expected to work on both the Foundation FVP
139 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
140 * SYS_ID register provides a mechanism for detecting the differences between
141 * these platforms. This information is stored in a per-BL array to allow the
142 * code to take the correct path.Per BL platform configuration.
143 ******************************************************************************/
Dan Handley2b6b5742015-03-19 19:17:53 +0000144void fvp_config_setup(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100145{
Soby Mathew8e2f2872014-08-14 12:49:05 +0100146 unsigned int rev, hbi, bld, arch, sys_id;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100147
Dan Handley2b6b5742015-03-19 19:17:53 +0000148 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
149 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK;
150 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK;
151 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK;
152 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100153
Andrew Thoelke960347d2014-06-26 14:27:26 +0100154 if (arch != ARCH_MODEL) {
155 ERROR("This firmware is for FVP models\n");
James Morrissey40a6f642014-02-10 14:24:36 +0000156 panic();
Andrew Thoelke960347d2014-06-26 14:27:26 +0100157 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100158
159 /*
160 * The build field in the SYS_ID tells which variant of the GIC
161 * memory is implemented by the model.
162 */
163 switch (bld) {
164 case BLD_GIC_VE_MMAP:
Soby Mathewcf022c52016-01-13 17:06:00 +0000165 ERROR("Legacy Versatile Express memory map for GIC peripheral"
166 " is not supported\n");
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000167 panic();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100168 break;
169 case BLD_GIC_A53A57_MMAP:
Achin Gupta4f6ad662013-10-25 09:08:21 +0100170 break;
171 default:
Andrew Thoelke960347d2014-06-26 14:27:26 +0100172 ERROR("Unsupported board build %x\n", bld);
173 panic();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100174 }
175
176 /*
177 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010
178 * for the Foundation FVP.
179 */
180 switch (hbi) {
Dan Handley2b6b5742015-03-19 19:17:53 +0000181 case HBI_FOUNDATION_FVP:
Dan Handley2b6b5742015-03-19 19:17:53 +0000182 arm_config.flags = 0;
Andrew Thoelke960347d2014-06-26 14:27:26 +0100183
184 /*
185 * Check for supported revisions of Foundation FVP
186 * Allow future revisions to run but emit warning diagnostic
187 */
188 switch (rev) {
Dan Handley2b6b5742015-03-19 19:17:53 +0000189 case REV_FOUNDATION_FVP_V2_0:
190 case REV_FOUNDATION_FVP_V2_1:
191 case REV_FOUNDATION_FVP_v9_1:
Andrew Thoelke960347d2014-06-26 14:27:26 +0100192 break;
193 default:
194 WARN("Unrecognized Foundation FVP revision %x\n", rev);
195 break;
196 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100197 break;
Dan Handley2b6b5742015-03-19 19:17:53 +0000198 case HBI_BASE_FVP:
Dan Handley2b6b5742015-03-19 19:17:53 +0000199 arm_config.flags |= ARM_CONFIG_BASE_MMAP |
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000200 ARM_CONFIG_HAS_INTERCONNECT | ARM_CONFIG_HAS_TZC;
Andrew Thoelke960347d2014-06-26 14:27:26 +0100201
202 /*
203 * Check for supported revisions
204 * Allow future revisions to run but emit warning diagnostic
205 */
206 switch (rev) {
Dan Handley2b6b5742015-03-19 19:17:53 +0000207 case REV_BASE_FVP_V0:
Andrew Thoelke960347d2014-06-26 14:27:26 +0100208 break;
209 default:
210 WARN("Unrecognized Base FVP revision %x\n", rev);
211 break;
212 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100213 break;
214 default:
Andrew Thoelke960347d2014-06-26 14:27:26 +0100215 ERROR("Unsupported board HBI number 0x%x\n", hbi);
216 panic();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100217 }
Sandrine Bailleux3fa98472014-03-31 11:25:18 +0100218}
Vikram Kanigiri96377452014-04-24 11:02:16 +0100219
Vikram Kanigiri4e97e542015-02-26 15:25:58 +0000220
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000221void fvp_interconnect_init(void)
Vikram Kanigiri96377452014-04-24 11:02:16 +0100222{
Soby Mathew7356b1e2016-03-24 10:12:42 +0000223 if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) {
224#if FVP_INTERCONNECT_DRIVER == FVP_CCN
225 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) {
226 ERROR("Unrecognized CCN variant detected. Only CCN-502"
227 " is supported");
228 panic();
229 }
230#endif
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000231 plat_arm_interconnect_init();
Soby Mathew7356b1e2016-03-24 10:12:42 +0000232 }
Dan Handleybe234f92014-08-04 16:11:15 +0100233}
234
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000235void fvp_interconnect_enable(void)
Dan Handleybe234f92014-08-04 16:11:15 +0100236{
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000237 if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT)
238 plat_arm_interconnect_enter_coherency();
Vikram Kanigiri4e97e542015-02-26 15:25:58 +0000239}
240
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000241void fvp_interconnect_disable(void)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +0000242{
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000243 if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT)
244 plat_arm_interconnect_exit_coherency();
Vikram Kanigiri96377452014-04-24 11:02:16 +0100245}