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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Soby Mathew7d5a2e72018-01-10 15:59:31 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
7#include <arch_helpers.h>
8#include <arm_def.h>
Yatharth Kocharf9a0f162016-09-13 17:07:57 +01009#include <assert.h>
Dan Handley9df48042015-03-19 18:58:55 +000010#include <bl_common.h>
11#include <console.h>
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010012#include <debug.h>
13#include <desc_image_load.h>
Soby Mathew1ced6b82017-06-12 12:37:10 +010014#include <generic_delay_timer.h>
Summer Qin9db8f2e2017-04-24 16:49:28 +010015#ifdef SPD_opteed
16#include <optee_utils.h>
17#endif
Dan Handley9df48042015-03-19 18:58:55 +000018#include <plat_arm.h>
dp-arm7f297ca2017-05-02 11:49:33 +010019#include <platform.h>
Isla Mitchelld2548792017-07-14 10:48:25 +010020#include <platform_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000021#include <string.h>
Douglas Raillarda8954fc2017-01-26 15:54:44 +000022#include <utils.h>
Dan Handley9df48042015-03-19 18:58:55 +000023
Dan Handley9df48042015-03-19 18:58:55 +000024/* Data structure which holds the extents of the trusted SRAM for BL2 */
25static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
26
Soby Mathewc44110d2018-02-20 12:50:47 +000027/*
28 * Check that BL2_BASE is atleast a page over ARM_BL_RAM_BASE. The page is for
29 * `meminfo_t` data structure and TB_FW_CONFIG passed from BL1. Not needed
30 * when BL2 is compiled for BL_AT_EL3 as BL2 doesn't need any info from BL1 and
31 * BL2 is loaded at base of usable SRAM.
32 */
33#if BL2_AT_EL3
34#define BL1_MEMINFO_OFFSET 0x0
35#else
36#define BL1_MEMINFO_OFFSET PAGE_SIZE
37#endif
38
39CASSERT(BL2_BASE >= (ARM_BL_RAM_BASE + BL1_MEMINFO_OFFSET), assert_bl2_base_overflows);
40
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010041/* Weak definitions may be overridden in specific ARM standard platform */
Soby Mathew7d5a2e72018-01-10 15:59:31 +000042#pragma weak bl2_early_platform_setup2
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010043#pragma weak bl2_platform_setup
44#pragma weak bl2_plat_arch_setup
45#pragma weak bl2_plat_sec_mem_layout
46
47#if LOAD_IMAGE_V2
48
49#pragma weak bl2_plat_handle_post_image_load
50
51#else /* LOAD_IMAGE_V2 */
Dan Handley9df48042015-03-19 18:58:55 +000052
53/*******************************************************************************
54 * This structure represents the superset of information that is passed to
Juan Castillo7d199412015-12-14 09:35:25 +000055 * BL31, e.g. while passing control to it from BL2, bl31_params
Dan Handley9df48042015-03-19 18:58:55 +000056 * and other platform specific params
57 ******************************************************************************/
58typedef struct bl2_to_bl31_params_mem {
59 bl31_params_t bl31_params;
60 image_info_t bl31_image_info;
61 image_info_t bl32_image_info;
62 image_info_t bl33_image_info;
63 entry_point_info_t bl33_ep_info;
64 entry_point_info_t bl32_ep_info;
65 entry_point_info_t bl31_ep_info;
66} bl2_to_bl31_params_mem_t;
67
68
69static bl2_to_bl31_params_mem_t bl31_params_mem;
70
71
72/* Weak definitions may be overridden in specific ARM standard platform */
Dan Handley9df48042015-03-19 18:58:55 +000073#pragma weak bl2_plat_get_bl31_params
74#pragma weak bl2_plat_get_bl31_ep_info
75#pragma weak bl2_plat_flush_bl31_params
76#pragma weak bl2_plat_set_bl31_ep_info
Juan Castilloa72b6472015-12-10 15:49:17 +000077#pragma weak bl2_plat_get_scp_bl2_meminfo
Dan Handley9df48042015-03-19 18:58:55 +000078#pragma weak bl2_plat_get_bl32_meminfo
79#pragma weak bl2_plat_set_bl32_ep_info
80#pragma weak bl2_plat_get_bl33_meminfo
81#pragma weak bl2_plat_set_bl33_ep_info
82
David Wang0ba499f2016-03-07 11:02:57 +080083#if ARM_BL31_IN_DRAM
84meminfo_t *bl2_plat_sec_mem_layout(void)
85{
86 static meminfo_t bl2_dram_layout
87 __aligned(CACHE_WRITEBACK_GRANULE) = {
88 .total_base = BL31_BASE,
89 .total_size = (ARM_AP_TZC_DRAM1_BASE +
90 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE,
91 .free_base = BL31_BASE,
92 .free_size = (ARM_AP_TZC_DRAM1_BASE +
93 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE
94 };
Dan Handley9df48042015-03-19 18:58:55 +000095
David Wang0ba499f2016-03-07 11:02:57 +080096 return &bl2_dram_layout;
97}
98#else
Dan Handley9df48042015-03-19 18:58:55 +000099meminfo_t *bl2_plat_sec_mem_layout(void)
100{
101 return &bl2_tzram_layout;
102}
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100103#endif /* ARM_BL31_IN_DRAM */
Dan Handley9df48042015-03-19 18:58:55 +0000104
105/*******************************************************************************
106 * This function assigns a pointer to the memory that the platform has kept
107 * aside to pass platform specific and trusted firmware related information
108 * to BL31. This memory is allocated by allocating memory to
109 * bl2_to_bl31_params_mem_t structure which is a superset of all the
110 * structure whose information is passed to BL31
111 * NOTE: This function should be called only once and should be done
112 * before generating params to BL31
113 ******************************************************************************/
114bl31_params_t *bl2_plat_get_bl31_params(void)
115{
116 bl31_params_t *bl2_to_bl31_params;
117
118 /*
119 * Initialise the memory for all the arguments that needs to
Juan Castillo7d199412015-12-14 09:35:25 +0000120 * be passed to BL31
Dan Handley9df48042015-03-19 18:58:55 +0000121 */
Douglas Raillarda8954fc2017-01-26 15:54:44 +0000122 zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t));
Dan Handley9df48042015-03-19 18:58:55 +0000123
124 /* Assign memory for TF related information */
125 bl2_to_bl31_params = &bl31_params_mem.bl31_params;
126 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
127
Juan Castillo7d199412015-12-14 09:35:25 +0000128 /* Fill BL31 related information */
Dan Handley9df48042015-03-19 18:58:55 +0000129 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info;
130 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
131 VERSION_1, 0);
132
Juan Castillo7d199412015-12-14 09:35:25 +0000133 /* Fill BL32 related information if it exists */
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100134#ifdef BL32_BASE
Dan Handley9df48042015-03-19 18:58:55 +0000135 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
136 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
137 VERSION_1, 0);
138 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
139 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
140 VERSION_1, 0);
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100141#endif /* BL32_BASE */
Dan Handley9df48042015-03-19 18:58:55 +0000142
Juan Castillo7d199412015-12-14 09:35:25 +0000143 /* Fill BL33 related information */
Dan Handley9df48042015-03-19 18:58:55 +0000144 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
145 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
146 PARAM_EP, VERSION_1, 0);
147
Juan Castillo7d199412015-12-14 09:35:25 +0000148 /* BL33 expects to receive the primary CPU MPID (through x0) */
Dan Handley9df48042015-03-19 18:58:55 +0000149 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
150
151 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
152 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
153 VERSION_1, 0);
154
155 return bl2_to_bl31_params;
156}
157
158/* Flush the TF params and the TF plat params */
159void bl2_plat_flush_bl31_params(void)
160{
161 flush_dcache_range((unsigned long)&bl31_params_mem,
162 sizeof(bl2_to_bl31_params_mem_t));
163}
164
165/*******************************************************************************
166 * This function returns a pointer to the shared memory that the platform
167 * has kept to point to entry point information of BL31 to BL2
168 ******************************************************************************/
169struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
170{
171#if DEBUG
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000172 bl31_params_mem.bl31_ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL;
Dan Handley9df48042015-03-19 18:58:55 +0000173#endif
174
175 return &bl31_params_mem.bl31_ep_info;
176}
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100177#endif /* LOAD_IMAGE_V2 */
Dan Handley9df48042015-03-19 18:58:55 +0000178
179/*******************************************************************************
180 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
181 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
182 * Copy it to a safe location before its reclaimed by later BL2 functionality.
183 ******************************************************************************/
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000184void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, meminfo_t *mem_layout)
Dan Handley9df48042015-03-19 18:58:55 +0000185{
186 /* Initialize the console to provide early debug support */
187 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ,
188 ARM_CONSOLE_BAUDRATE);
189
190 /* Setup the BL2 memory layout */
191 bl2_tzram_layout = *mem_layout;
192
193 /* Initialise the IO layer and register platform IO devices */
194 plat_arm_io_setup();
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000195
196#if LOAD_IMAGE_V2
Soby Mathewcc364842018-02-21 01:16:39 +0000197 if (tb_fw_config != 0U)
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000198 arm_bl2_set_tb_cfg_addr((void *)tb_fw_config);
199#endif
Dan Handley9df48042015-03-19 18:58:55 +0000200}
201
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000202void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3)
Dan Handley9df48042015-03-19 18:58:55 +0000203{
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000204 arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1);
205
Soby Mathew1ced6b82017-06-12 12:37:10 +0100206 generic_delay_timer_init();
Dan Handley9df48042015-03-19 18:58:55 +0000207}
208
209/*
210 * Perform ARM standard platform setup.
211 */
212void arm_bl2_platform_setup(void)
213{
Soby Mathew96a1c6b2018-01-15 14:45:33 +0000214#if LOAD_IMAGE_V2
215 arm_bl2_dyn_cfg_init();
216#endif
217
Dan Handley9df48042015-03-19 18:58:55 +0000218 /* Initialize the secure environment */
219 plat_arm_security_setup();
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100220
221#if defined(PLAT_ARM_MEM_PROT_ADDR)
222 arm_nor_psci_do_mem_protect();
223#endif
Dan Handley9df48042015-03-19 18:58:55 +0000224}
225
226void bl2_platform_setup(void)
227{
228 arm_bl2_platform_setup();
229}
230
231/*******************************************************************************
232 * Perform the very early platform specific architectural setup here. At the
233 * moment this is only initializes the mmu in a quick and dirty way.
234 ******************************************************************************/
235void arm_bl2_plat_arch_setup(void)
236{
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100237 arm_setup_page_tables(bl2_tzram_layout.total_base,
Dan Handley9df48042015-03-19 18:58:55 +0000238 bl2_tzram_layout.total_size,
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +0100239 BL_CODE_BASE,
Masahiro Yamada51bef612017-01-18 02:10:08 +0900240 BL_CODE_END,
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +0100241 BL_RO_DATA_BASE,
Masahiro Yamada51bef612017-01-18 02:10:08 +0900242 BL_RO_DATA_END
Dan Handley9df48042015-03-19 18:58:55 +0000243#if USE_COHERENT_MEM
Masahiro Yamada0fac5af2016-12-28 16:11:41 +0900244 , BL_COHERENT_RAM_BASE,
245 BL_COHERENT_RAM_END
Dan Handley9df48042015-03-19 18:58:55 +0000246#endif
247 );
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100248
249#ifdef AARCH32
250 enable_mmu_secure(0);
251#else
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100252 enable_mmu_el1(0);
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100253#endif
Dan Handley9df48042015-03-19 18:58:55 +0000254}
255
256void bl2_plat_arch_setup(void)
257{
258 arm_bl2_plat_arch_setup();
259}
260
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100261#if LOAD_IMAGE_V2
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000262int arm_bl2_handle_post_image_load(unsigned int image_id)
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100263{
264 int err = 0;
265 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
Summer Qin9db8f2e2017-04-24 16:49:28 +0100266#ifdef SPD_opteed
267 bl_mem_params_node_t *pager_mem_params = NULL;
268 bl_mem_params_node_t *paged_mem_params = NULL;
269#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100270 assert(bl_mem_params);
271
272 switch (image_id) {
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100273#ifdef AARCH64
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100274 case BL32_IMAGE_ID:
Summer Qin9db8f2e2017-04-24 16:49:28 +0100275#ifdef SPD_opteed
276 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
277 assert(pager_mem_params);
278
279 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
280 assert(paged_mem_params);
281
282 err = parse_optee_header(&bl_mem_params->ep_info,
283 &pager_mem_params->image_info,
284 &paged_mem_params->image_info);
285 if (err != 0) {
286 WARN("OPTEE header parse error.\n");
287 }
288#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100289 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry();
290 break;
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100291#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100292
293 case BL33_IMAGE_ID:
294 /* BL33 expects to receive the primary CPU MPID (through r0) */
295 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
296 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry();
297 break;
298
299#ifdef SCP_BL2_BASE
300 case SCP_BL2_IMAGE_ID:
301 /* The subsequent handling of SCP_BL2 is platform specific */
302 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info);
303 if (err) {
304 WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
305 }
306 break;
307#endif
Jonathan Wrightff957ed2018-03-14 15:24:00 +0000308 default:
309 /* Do nothing in default case */
310 break;
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100311 }
312
313 return err;
314}
315
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000316/*******************************************************************************
317 * This function can be used by the platforms to update/use image
318 * information for given `image_id`.
319 ******************************************************************************/
320int bl2_plat_handle_post_image_load(unsigned int image_id)
321{
322 return arm_bl2_handle_post_image_load(image_id);
323}
324
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100325#else /* LOAD_IMAGE_V2 */
326
Dan Handley9df48042015-03-19 18:58:55 +0000327/*******************************************************************************
Juan Castilloa72b6472015-12-10 15:49:17 +0000328 * Populate the extents of memory available for loading SCP_BL2 (if used),
Dan Handley9df48042015-03-19 18:58:55 +0000329 * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2.
330 ******************************************************************************/
Juan Castilloa72b6472015-12-10 15:49:17 +0000331void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo)
Dan Handley9df48042015-03-19 18:58:55 +0000332{
Juan Castilloa72b6472015-12-10 15:49:17 +0000333 *scp_bl2_meminfo = bl2_tzram_layout;
Dan Handley9df48042015-03-19 18:58:55 +0000334}
335
336/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000337 * Before calling this function BL31 is loaded in memory and its entrypoint
Dan Handley9df48042015-03-19 18:58:55 +0000338 * is set by load_image. This is a placeholder for the platform to change
Juan Castillo7d199412015-12-14 09:35:25 +0000339 * the entrypoint of BL31 and set SPSR and security state.
Dan Handley9df48042015-03-19 18:58:55 +0000340 * On ARM standard platforms we only set the security state of the entrypoint
341 ******************************************************************************/
342void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
343 entry_point_info_t *bl31_ep_info)
344{
345 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
346 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
347 DISABLE_ALL_EXCEPTIONS);
348}
349
350
351/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000352 * Before calling this function BL32 is loaded in memory and its entrypoint
Dan Handley9df48042015-03-19 18:58:55 +0000353 * is set by load_image. This is a placeholder for the platform to change
Juan Castillo7d199412015-12-14 09:35:25 +0000354 * the entrypoint of BL32 and set SPSR and security state.
Dan Handley9df48042015-03-19 18:58:55 +0000355 * On ARM standard platforms we only set the security state of the entrypoint
356 ******************************************************************************/
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100357#ifdef BL32_BASE
Dan Handley9df48042015-03-19 18:58:55 +0000358void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
359 entry_point_info_t *bl32_ep_info)
360{
361 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
362 bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry();
363}
364
365/*******************************************************************************
Dan Handley9df48042015-03-19 18:58:55 +0000366 * Populate the extents of memory available for loading BL32
367 ******************************************************************************/
368void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
369{
370 /*
371 * Populate the extents of memory available for loading BL32.
372 */
373 bl32_meminfo->total_base = BL32_BASE;
374 bl32_meminfo->free_base = BL32_BASE;
375 bl32_meminfo->total_size =
376 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
377 bl32_meminfo->free_size =
378 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
379}
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100380#endif /* BL32_BASE */
Dan Handley9df48042015-03-19 18:58:55 +0000381
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100382/*******************************************************************************
383 * Before calling this function BL33 is loaded in memory and its entrypoint
384 * is set by load_image. This is a placeholder for the platform to change
385 * the entrypoint of BL33 and set SPSR and security state.
386 * On ARM standard platforms we only set the security state of the entrypoint
387 ******************************************************************************/
388void bl2_plat_set_bl33_ep_info(image_info_t *image,
389 entry_point_info_t *bl33_ep_info)
390{
391 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
392 bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry();
393}
Dan Handley9df48042015-03-19 18:58:55 +0000394
395/*******************************************************************************
396 * Populate the extents of memory available for loading BL33
397 ******************************************************************************/
398void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
399{
400 bl33_meminfo->total_base = ARM_NS_DRAM1_BASE;
401 bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE;
402 bl33_meminfo->free_base = ARM_NS_DRAM1_BASE;
403 bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE;
404}
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100405
406#endif /* LOAD_IMAGE_V2 */