| John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 1 | /* |
| Bipin Ravi | af40d69 | 2021-12-22 14:35:21 -0600 | [diff] [blame] | 2 | * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. |
| John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef DSU_DEF_H |
| 8 | #define DSU_DEF_H |
| 9 | |
| Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <lib/utils_def.h> |
| John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 11 | |
| 12 | /******************************************************************** |
| Louis Mayencourt | 254f6f0 | 2019-04-09 14:11:06 +0100 | [diff] [blame] | 13 | * DSU Cluster Configuration registers definitions |
| John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 14 | ********************************************************************/ |
| 15 | #define CLUSTERCFR_EL1 S3_0_C15_C3_0 |
| Louis Mayencourt | 254f6f0 | 2019-04-09 14:11:06 +0100 | [diff] [blame] | 16 | |
| 17 | #define CLUSTERCFR_ACP_SHIFT U(11) |
| John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 18 | |
| 19 | /******************************************************************** |
| Louis Mayencourt | 254f6f0 | 2019-04-09 14:11:06 +0100 | [diff] [blame] | 20 | * DSU Cluster Main Revision ID registers definitions |
| John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 21 | ********************************************************************/ |
| Louis Mayencourt | 254f6f0 | 2019-04-09 14:11:06 +0100 | [diff] [blame] | 22 | #define CLUSTERIDR_EL1 S3_0_C15_C3_1 |
| 23 | |
| John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 24 | #define CLUSTERIDR_REV_SHIFT U(0) |
| 25 | #define CLUSTERIDR_REV_BITS U(4) |
| 26 | #define CLUSTERIDR_VAR_SHIFT U(4) |
| 27 | #define CLUSTERIDR_VAR_BITS U(4) |
| Louis Mayencourt | 254f6f0 | 2019-04-09 14:11:06 +0100 | [diff] [blame] | 28 | |
| 29 | /******************************************************************** |
| 30 | * DSU Cluster Auxiliary Control registers definitions |
| 31 | ********************************************************************/ |
| 32 | #define CLUSTERACTLR_EL1 S3_0_C15_C3_3 |
| John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 33 | |
| Louis Mayencourt | 4498b15 | 2019-04-09 16:29:01 +0100 | [diff] [blame] | 34 | #define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING (ULL(1) << 15) |
| Bipin Ravi | af40d69 | 2021-12-22 14:35:21 -0600 | [diff] [blame] | 35 | #define CLUSTERACTLR_EL1_DISABLE_SCLK_GATING (ULL(3) << 15) |
| Louis Mayencourt | 4498b15 | 2019-04-09 16:29:01 +0100 | [diff] [blame] | 36 | |
| John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 37 | /******************************************************************** |
| Louis Mayencourt | 254f6f0 | 2019-04-09 14:11:06 +0100 | [diff] [blame] | 38 | * Masks applied for DSU errata workarounds |
| John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 39 | ********************************************************************/ |
| Antonio Nino Diaz | 5e79cfe | 2019-02-11 13:34:15 +0000 | [diff] [blame] | 40 | #define DSU_ERRATA_936184_MASK (U(0x3) << 15) |
| John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 41 | |
| 42 | #endif /* DSU_DEF_H */ |