DSU: Small fix and reformat on errata framework
Change-Id: I50708f6ccc33059fbfe6d36fd66351f0b894311f
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
diff --git a/include/lib/cpus/aarch64/dsu_def.h b/include/lib/cpus/aarch64/dsu_def.h
index b7ba28a..4ec64ee 100644
--- a/include/lib/cpus/aarch64/dsu_def.h
+++ b/include/lib/cpus/aarch64/dsu_def.h
@@ -10,23 +10,29 @@
#include <lib/utils_def.h>
/********************************************************************
- * DSU control registers definitions *
+ * DSU Cluster Configuration registers definitions
********************************************************************/
#define CLUSTERCFR_EL1 S3_0_C15_C3_0
-#define CLUSTERIDR_EL1 S3_0_C15_C3_1
-#define CLUSTERACTLR_EL1 S3_0_C15_C3_3
+
+#define CLUSTERCFR_ACP_SHIFT U(11)
/********************************************************************
- * DSU control registers bit fields *
+ * DSU Cluster Main Revision ID registers definitions
********************************************************************/
+#define CLUSTERIDR_EL1 S3_0_C15_C3_1
+
#define CLUSTERIDR_REV_SHIFT U(0)
#define CLUSTERIDR_REV_BITS U(4)
#define CLUSTERIDR_VAR_SHIFT U(4)
#define CLUSTERIDR_VAR_BITS U(4)
-#define CLUSTERCFR_ACP_SHIFT U(11)
+
+/********************************************************************
+ * DSU Cluster Auxiliary Control registers definitions
+ ********************************************************************/
+#define CLUSTERACTLR_EL1 S3_0_C15_C3_3
/********************************************************************
- * Masks applied for DSU errata workarounds *
+ * Masks applied for DSU errata workarounds
********************************************************************/
#define DSU_ERRATA_936184_MASK (U(0x3) << 15)