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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Soby Mathew0b4c5a32016-10-21 17:51:22 +01002 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
7#include <arch_helpers.h>
Soby Mathew0d9e8522015-07-15 13:36:24 +01008#include <arm_def.h>
Soby Mathew61e8d0b2015-10-12 17:32:29 +01009#include <arm_gic.h>
Dan Handley9df48042015-03-19 18:58:55 +000010#include <assert.h>
Soby Mathew61e8d0b2015-10-12 17:32:29 +010011#include <console.h>
Dan Handley9df48042015-03-19 18:58:55 +000012#include <errno.h>
Soby Mathew7799cf72015-04-16 14:49:09 +010013#include <plat_arm.h>
Soby Mathewfeac8fc2015-09-29 15:47:16 +010014#include <platform_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000015#include <psci.h>
16
Soby Mathew0b4c5a32016-10-21 17:51:22 +010017/* Allow ARM Standard platforms to override this function */
18#pragma weak plat_arm_psci_override_pm_ops
19
Soby Mathewfeac8fc2015-09-29 15:47:16 +010020/* Standard ARM platforms are expected to export plat_arm_psci_pm_ops */
Soby Mathew0b4c5a32016-10-21 17:51:22 +010021extern plat_psci_ops_t plat_arm_psci_pm_ops;
Soby Mathewfeac8fc2015-09-29 15:47:16 +010022
Soby Mathew7799cf72015-04-16 14:49:09 +010023#if ARM_RECOM_STATE_ID_ENC
24extern unsigned int arm_pm_idle_states[];
25#endif /* __ARM_RECOM_STATE_ID_ENC__ */
26
Soby Mathew7799cf72015-04-16 14:49:09 +010027#if !ARM_RECOM_STATE_ID_ENC
Dan Handley9df48042015-03-19 18:58:55 +000028/*******************************************************************************
Soby Mathewfec4eb72015-07-01 16:16:20 +010029 * ARM standard platform handler called to check the validity of the power state
30 * parameter.
Dan Handley9df48042015-03-19 18:58:55 +000031 ******************************************************************************/
Soby Mathewfec4eb72015-07-01 16:16:20 +010032int arm_validate_power_state(unsigned int power_state,
33 psci_power_state_t *req_state)
Dan Handley9df48042015-03-19 18:58:55 +000034{
Soby Mathewfec4eb72015-07-01 16:16:20 +010035 int pstate = psci_get_pstate_type(power_state);
36 int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
37 int i;
Dan Handley9df48042015-03-19 18:58:55 +000038
Soby Mathewfec4eb72015-07-01 16:16:20 +010039 assert(req_state);
Dan Handley9df48042015-03-19 18:58:55 +000040
Soby Mathewfec4eb72015-07-01 16:16:20 +010041 if (pwr_lvl > PLAT_MAX_PWR_LVL)
42 return PSCI_E_INVALID_PARAMS;
Dan Handley9df48042015-03-19 18:58:55 +000043
Dan Handley9df48042015-03-19 18:58:55 +000044 /* Sanity check the requested state */
Soby Mathewfec4eb72015-07-01 16:16:20 +010045 if (pstate == PSTATE_TYPE_STANDBY) {
Dan Handley9df48042015-03-19 18:58:55 +000046 /*
Soby Mathewfec4eb72015-07-01 16:16:20 +010047 * It's possible to enter standby only on power level 0
48 * Ignore any other power level.
Dan Handley9df48042015-03-19 18:58:55 +000049 */
Soby Mathewfec4eb72015-07-01 16:16:20 +010050 if (pwr_lvl != ARM_PWR_LVL0)
Dan Handley9df48042015-03-19 18:58:55 +000051 return PSCI_E_INVALID_PARAMS;
Soby Mathewfec4eb72015-07-01 16:16:20 +010052
53 req_state->pwr_domain_state[ARM_PWR_LVL0] =
54 ARM_LOCAL_STATE_RET;
55 } else {
56 for (i = ARM_PWR_LVL0; i <= pwr_lvl; i++)
57 req_state->pwr_domain_state[i] =
58 ARM_LOCAL_STATE_OFF;
Dan Handley9df48042015-03-19 18:58:55 +000059 }
60
61 /*
62 * We expect the 'state id' to be zero.
63 */
64 if (psci_get_pstate_id(power_state))
65 return PSCI_E_INVALID_PARAMS;
66
Soby Mathew7799cf72015-04-16 14:49:09 +010067 return PSCI_E_SUCCESS;
68}
69
70#else
71/*******************************************************************************
72 * ARM standard platform handler called to check the validity of the power
73 * state parameter. The power state parameter has to be a composite power
74 * state.
75 ******************************************************************************/
76int arm_validate_power_state(unsigned int power_state,
77 psci_power_state_t *req_state)
78{
79 unsigned int state_id;
80 int i;
81
82 assert(req_state);
83
84 /*
85 * Currently we are using a linear search for finding the matching
86 * entry in the idle power state array. This can be made a binary
87 * search if the number of entries justify the additional complexity.
88 */
89 for (i = 0; !!arm_pm_idle_states[i]; i++) {
90 if (power_state == arm_pm_idle_states[i])
91 break;
92 }
93
94 /* Return error if entry not found in the idle state array */
95 if (!arm_pm_idle_states[i])
96 return PSCI_E_INVALID_PARAMS;
97
98 i = 0;
99 state_id = psci_get_pstate_id(power_state);
100
101 /* Parse the State ID and populate the state info parameter */
102 while (state_id) {
103 req_state->pwr_domain_state[i++] = state_id &
104 ARM_LOCAL_PSTATE_MASK;
105 state_id >>= ARM_LOCAL_PSTATE_WIDTH;
106 }
107
Dan Handley9df48042015-03-19 18:58:55 +0000108 return PSCI_E_SUCCESS;
109}
Soby Mathew7799cf72015-04-16 14:49:09 +0100110#endif /* __ARM_RECOM_STATE_ID_ENC__ */
Soby Mathew0d9e8522015-07-15 13:36:24 +0100111
112/*******************************************************************************
113 * ARM standard platform handler called to check the validity of the non secure
114 * entrypoint.
115 ******************************************************************************/
116int arm_validate_ns_entrypoint(uintptr_t entrypoint)
117{
118 /*
119 * Check if the non secure entrypoint lies within the non
120 * secure DRAM.
121 */
122 if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint <
123 (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE)))
124 return PSCI_E_SUCCESS;
dp-arm84fc2952017-05-03 12:14:10 +0100125#ifndef AARCH32
Soby Mathew0d9e8522015-07-15 13:36:24 +0100126 if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint <
127 (ARM_DRAM2_BASE + ARM_DRAM2_SIZE)))
128 return PSCI_E_SUCCESS;
dp-arm84fc2952017-05-03 12:14:10 +0100129#endif
Soby Mathew0d9e8522015-07-15 13:36:24 +0100130
131 return PSCI_E_INVALID_ADDRESS;
132}
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100133
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100134/******************************************************************************
Soby Mathew0b4c5a32016-10-21 17:51:22 +0100135 * Default definition on ARM standard platforms to override the plat_psci_ops.
136 *****************************************************************************/
137const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops)
138{
139 return ops;
140}
141
142/******************************************************************************
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100143 * Helper function to resume the platform from system suspend. Reinitialize
144 * the system components which are not in the Always ON power domain.
145 * TODO: Unify the platform setup when waking up from cold boot and system
146 * resume in arm_bl31_platform_setup().
147 *****************************************************************************/
148void arm_system_pwr_domain_resume(void)
149{
Soby Mathew2fd66be2015-12-09 11:38:43 +0000150 console_init(PLAT_ARM_BL31_RUN_UART_BASE, PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ,
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100151 ARM_CONSOLE_BAUDRATE);
152
153 /* Assert system power domain is available on the platform */
154 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2);
155
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000156 /*
157 * TODO: On GICv3 systems, figure out whether the core that wakes up
158 * first from system suspend need to initialize the re-distributor
159 * interface of all the other suspended cores.
160 */
161 plat_arm_gic_init();
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100162 plat_arm_security_setup();
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100163 arm_configure_sys_timer();
164}
165
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100166/*******************************************************************************
167 * Private function to program the mailbox for a cpu before it is released
168 * from reset. This function assumes that the Trusted mail box base is within
169 * the ARM_SHARED_RAM region
170 ******************************************************************************/
Sandrine Bailleux03897bb2015-11-26 16:31:34 +0000171void arm_program_trusted_mailbox(uintptr_t address)
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100172{
173 uintptr_t *mailbox = (void *) PLAT_ARM_TRUSTED_MAILBOX_BASE;
174
175 *mailbox = address;
176
177 /*
178 * Ensure that the PLAT_ARM_TRUSTED_MAILBOX_BASE is within
179 * ARM_SHARED_RAM region.
180 */
181 assert((PLAT_ARM_TRUSTED_MAILBOX_BASE >= ARM_SHARED_RAM_BASE) &&
182 ((PLAT_ARM_TRUSTED_MAILBOX_BASE + sizeof(*mailbox)) <= \
183 (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE)));
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100184}
185
186/*******************************************************************************
187 * The ARM Standard platform definition of platform porting API
188 * `plat_setup_psci_ops`.
189 ******************************************************************************/
190int plat_setup_psci_ops(uintptr_t sec_entrypoint,
191 const plat_psci_ops_t **psci_ops)
192{
Soby Mathew0b4c5a32016-10-21 17:51:22 +0100193 *psci_ops = plat_arm_psci_override_pm_ops(&plat_arm_psci_pm_ops);
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100194
195 /* Setup mailbox with entry point. */
196 arm_program_trusted_mailbox(sec_entrypoint);
197 return 0;
198}