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Soby Mathew991d42c2015-06-29 16:30:12 +01001/*
Soby Mathew3a9e8bf2015-05-05 16:33:16 +01002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Soby Mathew991d42c2015-06-29 16:30:12 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <arch_helpers.h>
33#include <assert.h>
34#include <bl_common.h>
35#include <bl31.h>
36#include <debug.h>
37#include <context_mgmt.h>
38#include <platform.h>
39#include <runtime_svc.h>
40#include <stddef.h>
41#include "psci_private.h"
42
Soby Mathew991d42c2015-06-29 16:30:12 +010043/*******************************************************************************
44 * This function checks whether a cpu which has been requested to be turned on
45 * is OFF to begin with.
46 ******************************************************************************/
Soby Mathew85dbf5a2015-04-07 12:16:56 +010047static int cpu_on_validate_state(aff_info_state_t aff_state)
Soby Mathew991d42c2015-06-29 16:30:12 +010048{
Soby Mathew85dbf5a2015-04-07 12:16:56 +010049 if (aff_state == AFF_STATE_ON)
Soby Mathew991d42c2015-06-29 16:30:12 +010050 return PSCI_E_ALREADY_ON;
51
Soby Mathew85dbf5a2015-04-07 12:16:56 +010052 if (aff_state == AFF_STATE_ON_PENDING)
Soby Mathew991d42c2015-06-29 16:30:12 +010053 return PSCI_E_ON_PENDING;
54
Soby Mathew85dbf5a2015-04-07 12:16:56 +010055 assert(aff_state == AFF_STATE_OFF);
Soby Mathew991d42c2015-06-29 16:30:12 +010056 return PSCI_E_SUCCESS;
57}
58
59/*******************************************************************************
Soby Mathew991d42c2015-06-29 16:30:12 +010060 * Generic handler which is called to physically power on a cpu identified by
Soby Mathew6b8b3022015-06-30 11:00:24 +010061 * its mpidr. It performs the generic, architectural, platform setup and state
62 * management to power on the target cpu e.g. it will ensure that
63 * enough information is stashed for it to resume execution in the non-secure
64 * security state.
Soby Mathew991d42c2015-06-29 16:30:12 +010065 *
Soby Mathew3a9e8bf2015-05-05 16:33:16 +010066 * The state of all the relevant power domains are changed after calling the
Soby Mathew6b8b3022015-06-30 11:00:24 +010067 * platform handler as it can return error.
Soby Mathew991d42c2015-06-29 16:30:12 +010068 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +010069int psci_cpu_on_start(u_register_t target_cpu,
Sandrine Bailleux7497bff2016-04-25 09:28:43 +010070 entry_point_info_t *ep)
Soby Mathew991d42c2015-06-29 16:30:12 +010071{
72 int rc;
Soby Mathew9d754f62015-04-08 17:42:06 +010073 unsigned int target_idx = plat_core_pos_by_mpidr(target_cpu);
Soby Mathewca370502016-01-26 11:47:53 +000074 aff_info_state_t target_aff_state;
Soby Mathew991d42c2015-06-29 16:30:12 +010075
Sandrine Bailleux6181acb2016-04-22 13:00:19 +010076 /* Calling function must supply valid input arguments */
77 assert((int) target_idx >= 0);
78 assert(ep != NULL);
79
Soby Mathew991d42c2015-06-29 16:30:12 +010080 /*
81 * This function must only be called on platforms where the
82 * CPU_ON platform hooks have been implemented.
83 */
Soby Mathew3a9e8bf2015-05-05 16:33:16 +010084 assert(psci_plat_pm_ops->pwr_domain_on &&
85 psci_plat_pm_ops->pwr_domain_on_finish);
Soby Mathew991d42c2015-06-29 16:30:12 +010086
Soby Mathew9d754f62015-04-08 17:42:06 +010087 /* Protect against multiple CPUs trying to turn ON the same target CPU */
88 psci_spin_lock_cpu(target_idx);
Soby Mathew991d42c2015-06-29 16:30:12 +010089
90 /*
Soby Mathew991d42c2015-06-29 16:30:12 +010091 * Generic management: Ensure that the cpu is off to be
92 * turned on.
93 */
Soby Mathew85dbf5a2015-04-07 12:16:56 +010094 rc = cpu_on_validate_state(psci_get_aff_info_state_by_idx(target_idx));
Soby Mathew991d42c2015-06-29 16:30:12 +010095 if (rc != PSCI_E_SUCCESS)
96 goto exit;
97
98 /*
99 * Call the cpu on handler registered by the Secure Payload Dispatcher
100 * to let it do any bookeeping. If the handler encounters an error, it's
101 * expected to assert within
102 */
103 if (psci_spd_pm && psci_spd_pm->svc_on)
104 psci_spd_pm->svc_on(target_cpu);
105
106 /*
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100107 * Set the Affinity info state of the target cpu to ON_PENDING.
Soby Mathewca370502016-01-26 11:47:53 +0000108 * Flush aff_info_state as it will be accessed with caches
109 * turned OFF.
Soby Mathew991d42c2015-06-29 16:30:12 +0100110 */
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100111 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING);
Soby Mathewca370502016-01-26 11:47:53 +0000112 flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state);
113
114 /*
115 * The cache line invalidation by the target CPU after setting the
116 * state to OFF (see psci_do_cpu_off()), could cause the update to
117 * aff_info_state to be invalidated. Retry the update if the target
118 * CPU aff_info_state is not ON_PENDING.
119 */
120 target_aff_state = psci_get_aff_info_state_by_idx(target_idx);
121 if (target_aff_state != AFF_STATE_ON_PENDING) {
122 assert(target_aff_state == AFF_STATE_OFF);
123 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING);
124 flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state);
125
126 assert(psci_get_aff_info_state_by_idx(target_idx) == AFF_STATE_ON_PENDING);
127 }
Soby Mathew6b8b3022015-06-30 11:00:24 +0100128
129 /*
130 * Perform generic, architecture and platform specific handling.
131 */
Soby Mathew6b8b3022015-06-30 11:00:24 +0100132 /*
133 * Plat. management: Give the platform the current state
134 * of the target cpu to allow it to perform the necessary
135 * steps to power on.
136 */
Soby Mathew011ca182015-07-29 17:05:03 +0100137 rc = psci_plat_pm_ops->pwr_domain_on(target_cpu);
Soby Mathew991d42c2015-06-29 16:30:12 +0100138 assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL);
139
140 if (rc == PSCI_E_SUCCESS)
141 /* Store the re-entry information for the non-secure world. */
Soby Mathewb0082d22015-04-09 13:40:55 +0100142 cm_init_context_by_index(target_idx, ep);
Soby Mathewca370502016-01-26 11:47:53 +0000143 else {
Soby Mathew991d42c2015-06-29 16:30:12 +0100144 /* Restore the state on error. */
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100145 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_OFF);
Soby Mathewca370502016-01-26 11:47:53 +0000146 flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state);
147 }
Soby Mathewb0082d22015-04-09 13:40:55 +0100148
Soby Mathew991d42c2015-06-29 16:30:12 +0100149exit:
Soby Mathew9d754f62015-04-08 17:42:06 +0100150 psci_spin_unlock_cpu(target_idx);
Soby Mathew991d42c2015-06-29 16:30:12 +0100151 return rc;
152}
153
154/*******************************************************************************
Soby Mathew3a9e8bf2015-05-05 16:33:16 +0100155 * The following function finish an earlier power on request. They
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100156 * are called by the common finisher routine in psci_common.c. The `state_info`
157 * is the psci_power_state from which this CPU has woken up from.
Soby Mathew991d42c2015-06-29 16:30:12 +0100158 ******************************************************************************/
Soby Mathew9d754f62015-04-08 17:42:06 +0100159void psci_cpu_on_finish(unsigned int cpu_idx,
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100160 psci_power_state_t *state_info)
Soby Mathew991d42c2015-06-29 16:30:12 +0100161{
Soby Mathew991d42c2015-06-29 16:30:12 +0100162 /*
163 * Plat. management: Perform the platform specific actions
164 * for this cpu e.g. enabling the gic or zeroing the mailbox
165 * register. The actual state of this cpu has already been
166 * changed.
167 */
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100168 psci_plat_pm_ops->pwr_domain_on_finish(state_info);
Soby Mathew991d42c2015-06-29 16:30:12 +0100169
170 /*
171 * Arch. management: Enable data cache and manage stack memory
172 */
173 psci_do_pwrup_cache_maintenance();
174
175 /*
176 * All the platform specific actions for turning this cpu
177 * on have completed. Perform enough arch.initialization
178 * to run in the non-secure address space.
179 */
180 bl31_arch_setup();
181
182 /*
Soby Mathew9d754f62015-04-08 17:42:06 +0100183 * Lock the CPU spin lock to make sure that the context initialization
184 * is done. Since the lock is only used in this function to create
185 * a synchronization point with cpu_on_start(), it can be released
186 * immediately.
187 */
188 psci_spin_lock_cpu(cpu_idx);
189 psci_spin_unlock_cpu(cpu_idx);
190
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100191 /* Ensure we have been explicitly woken up by another cpu */
192 assert(psci_get_aff_info_state() == AFF_STATE_ON_PENDING);
193
Soby Mathew9d754f62015-04-08 17:42:06 +0100194 /*
Soby Mathew991d42c2015-06-29 16:30:12 +0100195 * Call the cpu on finish handler registered by the Secure Payload
196 * Dispatcher to let it do any bookeeping. If the handler encounters an
197 * error, it's expected to assert within
198 */
199 if (psci_spd_pm && psci_spd_pm->svc_on_finish)
200 psci_spd_pm->svc_on_finish(0);
201
Soby Mathew9d754f62015-04-08 17:42:06 +0100202 /* Populate the mpidr field within the cpu node array */
203 /* This needs to be done only once */
204 psci_cpu_pd_nodes[cpu_idx].mpidr = read_mpidr() & MPIDR_AFFINITY_MASK;
205
Soby Mathew991d42c2015-06-29 16:30:12 +0100206 /*
207 * Generic management: Now we just need to retrieve the
208 * information that we had stashed away during the cpu_on
209 * call to set this cpu on its way.
210 */
211 cm_prepare_el3_exit(NON_SECURE);
Soby Mathew991d42c2015-06-29 16:30:12 +0100212}