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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Soby Mathew7d5a2e72018-01-10 15:59:31 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
7#include <arch.h>
8#include <arch_helpers.h>
9#include <arm_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000010#include <assert.h>
11#include <bl_common.h>
Dan Handley9df48042015-03-19 18:58:55 +000012#include <console.h>
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010013#include <debug.h>
Dan Handley9df48042015-03-19 18:58:55 +000014#include <mmio.h>
15#include <plat_arm.h>
16#include <platform.h>
Jeenu Viswambharana5b5b8d2018-02-06 12:21:39 +000017#include <ras.h>
Dan Handley9df48042015-03-19 18:58:55 +000018
Soby Mathewa0fedc42016-06-16 14:52:04 +010019#define BL31_END (uintptr_t)(&__BL31_END__)
Dan Handley9df48042015-03-19 18:58:55 +000020
Dan Handley9df48042015-03-19 18:58:55 +000021/*
22 * Placeholder variables for copying the arguments that have been passed to
Juan Castillo7d199412015-12-14 09:35:25 +000023 * BL31 from BL2.
Dan Handley9df48042015-03-19 18:58:55 +000024 */
25static entry_point_info_t bl32_image_ep_info;
26static entry_point_info_t bl33_image_ep_info;
27
28
29/* Weak definitions may be overridden in specific ARM standard platform */
Soby Mathew7d5a2e72018-01-10 15:59:31 +000030#pragma weak bl31_early_platform_setup2
Dan Handley9df48042015-03-19 18:58:55 +000031#pragma weak bl31_platform_setup
32#pragma weak bl31_plat_arch_setup
33#pragma weak bl31_plat_get_next_image_ep_info
Dan Handley9df48042015-03-19 18:58:55 +000034
35
36/*******************************************************************************
37 * Return a pointer to the 'entry_point_info' structure of the next image for the
Juan Castillo7d199412015-12-14 09:35:25 +000038 * security state specified. BL33 corresponds to the non-secure image type
39 * while BL32 corresponds to the secure image type. A NULL pointer is returned
Dan Handley9df48042015-03-19 18:58:55 +000040 * if the image does not exist.
41 ******************************************************************************/
42entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
43{
44 entry_point_info_t *next_image_info;
45
46 assert(sec_state_is_valid(type));
47 next_image_info = (type == NON_SECURE)
48 ? &bl33_image_ep_info : &bl32_image_ep_info;
49 /*
50 * None of the images on the ARM development platforms can have 0x0
51 * as the entrypoint
52 */
53 if (next_image_info->pc)
54 return next_image_info;
55 else
56 return NULL;
57}
58
59/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +000060 * Perform any BL31 early platform setup common to ARM standard platforms.
Dan Handley9df48042015-03-19 18:58:55 +000061 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1
62 * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be
63 * done before the MMU is initialized so that the memory layout can be used
64 * while creating page tables. BL2 has flushed this information to memory, so
65 * we are guaranteed to pick up good data.
66 ******************************************************************************/
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010067#if LOAD_IMAGE_V2
Soby Mathew7d5a2e72018-01-10 15:59:31 +000068void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config,
69 uintptr_t hw_config, void *plat_params_from_bl2)
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010070#else
Soby Mathew7d5a2e72018-01-10 15:59:31 +000071void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, uintptr_t soc_fw_config,
72 uintptr_t hw_config, void *plat_params_from_bl2)
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010073#endif
Dan Handley9df48042015-03-19 18:58:55 +000074{
75 /* Initialize the console to provide early debug support */
Antonio Nino Diazb37eba92018-05-15 13:12:50 +010076 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ,
77 ARM_CONSOLE_BAUDRATE);
Dan Handley9df48042015-03-19 18:58:55 +000078
79#if RESET_TO_BL31
Juan Castillo7d199412015-12-14 09:35:25 +000080 /* There are no parameters from BL2 if BL31 is a reset vector */
Dan Handley9df48042015-03-19 18:58:55 +000081 assert(from_bl2 == NULL);
82 assert(plat_params_from_bl2 == NULL);
83
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +010084# ifdef BL32_BASE
Juan Castillo7d199412015-12-14 09:35:25 +000085 /* Populate entry point information for BL32 */
Dan Handley9df48042015-03-19 18:58:55 +000086 SET_PARAM_HEAD(&bl32_image_ep_info,
87 PARAM_EP,
88 VERSION_1,
89 0);
90 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
91 bl32_image_ep_info.pc = BL32_BASE;
92 bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +010093# endif /* BL32_BASE */
Dan Handley9df48042015-03-19 18:58:55 +000094
Juan Castillo7d199412015-12-14 09:35:25 +000095 /* Populate entry point information for BL33 */
Dan Handley9df48042015-03-19 18:58:55 +000096 SET_PARAM_HEAD(&bl33_image_ep_info,
97 PARAM_EP,
98 VERSION_1,
99 0);
100 /*
Juan Castillo7d199412015-12-14 09:35:25 +0000101 * Tell BL31 where the non-trusted software image
Dan Handley9df48042015-03-19 18:58:55 +0000102 * is located and the entry state information
103 */
104 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
Soby Mathew4876ae32016-05-09 17:20:10 +0100105
Dan Handley9df48042015-03-19 18:58:55 +0000106 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
107 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
108
Antonio Nino Diazd9166ac2018-05-11 11:15:10 +0100109# if ARM_LINUX_KERNEL_AS_BL33
110 /*
111 * According to the file ``Documentation/arm64/booting.txt`` of the
112 * Linux kernel tree, Linux expects the physical address of the device
113 * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
114 * must be 0.
115 */
116 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
117 bl33_image_ep_info.args.arg1 = 0U;
118 bl33_image_ep_info.args.arg2 = 0U;
119 bl33_image_ep_info.args.arg3 = 0U;
120# endif
121
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100122#else /* RESET_TO_BL31 */
123
Dan Handley9df48042015-03-19 18:58:55 +0000124 /*
125 * In debug builds, we pass a special value in 'plat_params_from_bl2'
Juan Castillo7d199412015-12-14 09:35:25 +0000126 * to verify platform parameters from BL2 to BL31.
Dan Handley9df48042015-03-19 18:58:55 +0000127 * In release builds, it's not used.
128 */
129 assert(((unsigned long long)plat_params_from_bl2) ==
130 ARM_BL31_PLAT_PARAM_VAL);
131
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100132# if LOAD_IMAGE_V2
133 /*
134 * Check params passed from BL2 should not be NULL,
135 */
136 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
137 assert(params_from_bl2 != NULL);
138 assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
139 assert(params_from_bl2->h.version >= VERSION_2);
140
141 bl_params_node_t *bl_params = params_from_bl2->head;
142
143 /*
144 * Copy BL33 and BL32 (if present), entry point information.
145 * They are stored in Secure RAM, in BL2's address space.
146 */
147 while (bl_params) {
148 if (bl_params->image_id == BL32_IMAGE_ID)
149 bl32_image_ep_info = *bl_params->ep_info;
150
151 if (bl_params->image_id == BL33_IMAGE_ID)
152 bl33_image_ep_info = *bl_params->ep_info;
153
154 bl_params = bl_params->next_params_info;
155 }
156
157 if (bl33_image_ep_info.pc == 0)
158 panic();
159
160# else /* LOAD_IMAGE_V2 */
161
162 /*
163 * Check params passed from BL2 should not be NULL,
164 */
165 assert(from_bl2 != NULL);
166 assert(from_bl2->h.type == PARAM_BL31);
167 assert(from_bl2->h.version >= VERSION_1);
168
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000169 /* Dynamic Config is not supported for LOAD_IMAGE_V1 */
170 assert(soc_fw_config == 0);
171 assert(hw_config == 0);
172
Dan Handley9df48042015-03-19 18:58:55 +0000173 /*
Juan Castillo7d199412015-12-14 09:35:25 +0000174 * Copy BL32 (if populated by BL2) and BL33 entry point information.
Dan Handley9df48042015-03-19 18:58:55 +0000175 * They are stored in Secure RAM, in BL2's address space.
176 */
Juan Castillo456deef2015-11-06 10:01:37 +0000177 if (from_bl2->bl32_ep_info)
178 bl32_image_ep_info = *from_bl2->bl32_ep_info;
Dan Handley9df48042015-03-19 18:58:55 +0000179 bl33_image_ep_info = *from_bl2->bl33_ep_info;
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100180
181# endif /* LOAD_IMAGE_V2 */
182#endif /* RESET_TO_BL31 */
Dan Handley9df48042015-03-19 18:58:55 +0000183}
184
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000185void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
186 u_register_t arg2, u_register_t arg3)
Dan Handley9df48042015-03-19 18:58:55 +0000187{
Soby Mathew7d5a2e72018-01-10 15:59:31 +0000188 arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3);
Dan Handley9df48042015-03-19 18:58:55 +0000189
190 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000191 * Initialize Interconnect for this cluster during cold boot.
Dan Handley9df48042015-03-19 18:58:55 +0000192 * No need for locks as no other CPU is active.
193 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000194 plat_arm_interconnect_init();
Sandrine Bailleuxda797f62015-05-14 14:13:05 +0100195
Dan Handley9df48042015-03-19 18:58:55 +0000196 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000197 * Enable Interconnect coherency for the primary CPU's cluster.
Sandrine Bailleuxda797f62015-05-14 14:13:05 +0100198 * Earlier bootloader stages might already do this (e.g. Trusted
199 * Firmware's BL1 does it) but we can't assume so. There is no harm in
200 * executing this code twice anyway.
Dan Handley9df48042015-03-19 18:58:55 +0000201 * Platform specific PSCI code will enable coherency for other
202 * clusters.
203 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000204 plat_arm_interconnect_enter_coherency();
Dan Handley9df48042015-03-19 18:58:55 +0000205}
206
207/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000208 * Perform any BL31 platform setup common to ARM standard platforms
Dan Handley9df48042015-03-19 18:58:55 +0000209 ******************************************************************************/
210void arm_bl31_platform_setup(void)
211{
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000212 /* Initialize the GIC driver, cpu and distributor interfaces */
213 plat_arm_gic_driver_init();
Dan Handley9df48042015-03-19 18:58:55 +0000214 plat_arm_gic_init();
Dan Handley9df48042015-03-19 18:58:55 +0000215
216#if RESET_TO_BL31
217 /*
218 * Do initial security configuration to allow DRAM/device access
219 * (if earlier BL has not already done so).
220 */
221 plat_arm_security_setup();
222
Roberto Vargas550eb082018-01-05 16:00:05 +0000223#if defined(PLAT_ARM_MEM_PROT_ADDR)
224 arm_nor_psci_do_dyn_mem_protect();
225#endif /* PLAT_ARM_MEM_PROT_ADDR */
226
Dan Handley9df48042015-03-19 18:58:55 +0000227#endif /* RESET_TO_BL31 */
228
229 /* Enable and initialize the System level generic timer */
230 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
231 CNTCR_FCREQ(0) | CNTCR_EN);
232
233 /* Allow access to the System counter timer module */
Soby Mathew61e8d0b2015-10-12 17:32:29 +0100234 arm_configure_sys_timer();
Dan Handley9df48042015-03-19 18:58:55 +0000235
236 /* Initialize power controller before setting up topology */
237 plat_arm_pwrc_setup();
Jeenu Viswambharana5b5b8d2018-02-06 12:21:39 +0000238
239#if RAS_EXTENSION
240 ras_init();
241#endif
Dan Handley9df48042015-03-19 18:58:55 +0000242}
243
Soby Mathew2fd66be2015-12-09 11:38:43 +0000244/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000245 * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM
Soby Mathew2fd66be2015-12-09 11:38:43 +0000246 * standard platforms
247 ******************************************************************************/
248void arm_bl31_plat_runtime_setup(void)
249{
250 /* Initialize the runtime console */
Antonio Nino Diazb37eba92018-05-15 13:12:50 +0100251 console_init(PLAT_ARM_BL31_RUN_UART_BASE, PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ,
252 ARM_CONSOLE_BAUDRATE);
Soby Mathew2fd66be2015-12-09 11:38:43 +0000253}
254
Dan Handley9df48042015-03-19 18:58:55 +0000255void bl31_platform_setup(void)
256{
257 arm_bl31_platform_setup();
258}
259
Soby Mathew2fd66be2015-12-09 11:38:43 +0000260void bl31_plat_runtime_setup(void)
261{
262 arm_bl31_plat_runtime_setup();
263}
264
Dan Handley9df48042015-03-19 18:58:55 +0000265/*******************************************************************************
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100266 * Perform the very early platform specific architectural setup shared between
267 * ARM standard platforms. This only does basic initialization. Later
268 * architectural setup (bl31_arch_setup()) does not do anything platform
269 * specific.
Dan Handley9df48042015-03-19 18:58:55 +0000270 ******************************************************************************/
271void arm_bl31_plat_arch_setup(void)
272{
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +0100273 arm_setup_page_tables(BL31_BASE,
274 BL31_END - BL31_BASE,
275 BL_CODE_BASE,
Masahiro Yamada51bef612017-01-18 02:10:08 +0900276 BL_CODE_END,
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +0100277 BL_RO_DATA_BASE,
Masahiro Yamada51bef612017-01-18 02:10:08 +0900278 BL_RO_DATA_END
Dan Handley9df48042015-03-19 18:58:55 +0000279#if USE_COHERENT_MEM
Masahiro Yamada0fac5af2016-12-28 16:11:41 +0900280 , BL_COHERENT_RAM_BASE,
281 BL_COHERENT_RAM_END
Dan Handley9df48042015-03-19 18:58:55 +0000282#endif
283 );
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100284 enable_mmu_el3(0);
Dan Handley9df48042015-03-19 18:58:55 +0000285}
286
287void bl31_plat_arch_setup(void)
288{
289 arm_bl31_plat_arch_setup();
290}