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Achin Guptae1aa5162014-06-26 09:58:52 +01001/*
Soby Mathew0d786072016-03-24 16:56:29 +00002 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
Achin Guptae1aa5162014-06-26 09:58:52 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Guptae1aa5162014-06-26 09:58:52 +01005 */
6
Achin Guptae1aa5162014-06-26 09:58:52 +01007#include <asm_macros.S>
Achin Guptaf6b9e992014-07-31 11:19:11 +01008#include <assert_macros.S>
Achin Guptae1aa5162014-06-26 09:58:52 +01009#include <platform_def.h>
Achin Guptaf6b9e992014-07-31 11:19:11 +010010#include <psci.h>
Achin Guptae1aa5162014-06-26 09:58:52 +010011
12 .globl psci_do_pwrdown_cache_maintenance
13 .globl psci_do_pwrup_cache_maintenance
Soby Mathewd0194872016-04-29 19:01:30 +010014 .globl psci_power_down_wfi
15#if !ERROR_DEPRECATED
16 .globl psci_entrypoint
17#endif
Achin Guptae1aa5162014-06-26 09:58:52 +010018
19/* -----------------------------------------------------------------------
Soby Mathew011ca182015-07-29 17:05:03 +010020 * void psci_do_pwrdown_cache_maintenance(unsigned int power level);
Achin Guptae1aa5162014-06-26 09:58:52 +010021 *
Soby Mathew981487a2015-07-13 14:10:57 +010022 * This function performs cache maintenance for the specified power
23 * level. The levels of cache affected are determined by the power
24 * level which is passed as the argument i.e. level 0 results
25 * in a flush of the L1 cache. Both the L1 and L2 caches are flushed
26 * for a higher power level.
Achin Guptaf6b9e992014-07-31 11:19:11 +010027 *
28 * Additionally, this function also ensures that stack memory is correctly
29 * flushed out to avoid coherency issues due to a change in its memory
30 * attributes after the data cache is disabled.
Achin Guptae1aa5162014-06-26 09:58:52 +010031 * -----------------------------------------------------------------------
32 */
33func psci_do_pwrdown_cache_maintenance
34 stp x29, x30, [sp,#-16]!
35 stp x19, x20, [sp,#-16]!
36
37 /* ---------------------------------------------
Jeenu Viswambharanee5eb802016-11-18 12:58:28 +000038 * Invoke CPU-specific power down operations for
39 * the appropriate level
Achin Guptae1aa5162014-06-26 09:58:52 +010040 * ---------------------------------------------
41 */
Jeenu Viswambharanee5eb802016-11-18 12:58:28 +000042 bl prepare_cpu_pwr_dwn
Achin Guptae1aa5162014-06-26 09:58:52 +010043
44 /* ---------------------------------------------
45 * Do stack maintenance by flushing the used
46 * stack to the main memory and invalidating the
47 * remainder.
48 * ---------------------------------------------
49 */
Soby Mathew981487a2015-07-13 14:10:57 +010050 bl plat_get_my_stack
Achin Guptae1aa5162014-06-26 09:58:52 +010051
52 /* ---------------------------------------------
53 * Calculate and store the size of the used
54 * stack memory in x1.
55 * ---------------------------------------------
56 */
57 mov x19, x0
58 mov x1, sp
59 sub x1, x0, x1
60 mov x0, sp
61 bl flush_dcache_range
62
63 /* ---------------------------------------------
64 * Calculate and store the size of the unused
65 * stack memory in x1. Calculate and store the
66 * stack base address in x0.
67 * ---------------------------------------------
68 */
69 sub x0, x19, #PLATFORM_STACK_SIZE
70 sub x1, sp, x0
71 bl inv_dcache_range
72
Achin Guptae1aa5162014-06-26 09:58:52 +010073 ldp x19, x20, [sp], #16
74 ldp x29, x30, [sp], #16
75 ret
Kévin Petita877c252015-03-24 14:03:57 +000076endfunc psci_do_pwrdown_cache_maintenance
Achin Guptae1aa5162014-06-26 09:58:52 +010077
78
79/* -----------------------------------------------------------------------
80 * void psci_do_pwrup_cache_maintenance(void);
81 *
82 * This function performs cache maintenance after this cpu is powered up.
83 * Currently, this involves managing the used stack memory before turning
84 * on the data cache.
85 * -----------------------------------------------------------------------
86 */
87func psci_do_pwrup_cache_maintenance
88 stp x29, x30, [sp,#-16]!
89
90 /* ---------------------------------------------
91 * Ensure any inflight stack writes have made it
92 * to main memory.
93 * ---------------------------------------------
94 */
95 dmb st
96
97 /* ---------------------------------------------
98 * Calculate and store the size of the used
99 * stack memory in x1. Calculate and store the
100 * stack base address in x0.
101 * ---------------------------------------------
102 */
Soby Mathew981487a2015-07-13 14:10:57 +0100103 bl plat_get_my_stack
Achin Guptae1aa5162014-06-26 09:58:52 +0100104 mov x1, sp
105 sub x1, x0, x1
106 mov x0, sp
107 bl inv_dcache_range
108
109 /* ---------------------------------------------
110 * Enable the data cache.
111 * ---------------------------------------------
112 */
113 mrs x0, sctlr_el3
114 orr x0, x0, #SCTLR_C_BIT
115 msr sctlr_el3, x0
116 isb
117
118 ldp x29, x30, [sp], #16
119 ret
Kévin Petita877c252015-03-24 14:03:57 +0000120endfunc psci_do_pwrup_cache_maintenance
Soby Mathewd0194872016-04-29 19:01:30 +0100121
122/* -----------------------------------------------------------------------
123 * void psci_power_down_wfi(void);
124 * This function is called to indicate to the power controller that it
125 * is safe to power down this cpu. It should not exit the wfi and will
126 * be released from reset upon power up.
127 * -----------------------------------------------------------------------
128 */
129func psci_power_down_wfi
130 dsb sy // ensure write buffer empty
131 wfi
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000132 no_ret plat_panic_handler
Soby Mathewd0194872016-04-29 19:01:30 +0100133endfunc psci_power_down_wfi
134
135/* -----------------------------------------------------------------------
136 * void psci_entrypoint(void);
137 * The deprecated entry point for PSCI on warm boot for AArch64.
138 * -----------------------------------------------------------------------
139 */
140func_deprecated psci_entrypoint
141 b bl31_warm_entrypoint
142endfunc_deprecated psci_entrypoint