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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Douglas Raillarda8954fc2017-01-26 15:54:44 +00002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
7#include <arch_helpers.h>
8#include <arm_def.h>
Yatharth Kocharf9a0f162016-09-13 17:07:57 +01009#include <assert.h>
Dan Handley9df48042015-03-19 18:58:55 +000010#include <bl_common.h>
11#include <console.h>
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010012#include <debug.h>
13#include <desc_image_load.h>
Soby Mathew1ced6b82017-06-12 12:37:10 +010014#include <generic_delay_timer.h>
Summer Qin9db8f2e2017-04-24 16:49:28 +010015#ifdef SPD_opteed
16#include <optee_utils.h>
17#endif
Dan Handley9df48042015-03-19 18:58:55 +000018#include <plat_arm.h>
dp-arm7f297ca2017-05-02 11:49:33 +010019#include <platform.h>
Isla Mitchelld2548792017-07-14 10:48:25 +010020#include <platform_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000021#include <string.h>
Douglas Raillarda8954fc2017-01-26 15:54:44 +000022#include <utils.h>
Dan Handley9df48042015-03-19 18:58:55 +000023
Dan Handley9df48042015-03-19 18:58:55 +000024/* Data structure which holds the extents of the trusted SRAM for BL2 */
25static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
26
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010027/* Weak definitions may be overridden in specific ARM standard platform */
28#pragma weak bl2_early_platform_setup
29#pragma weak bl2_platform_setup
30#pragma weak bl2_plat_arch_setup
31#pragma weak bl2_plat_sec_mem_layout
32
33#if LOAD_IMAGE_V2
34
35#pragma weak bl2_plat_handle_post_image_load
36
37#else /* LOAD_IMAGE_V2 */
Dan Handley9df48042015-03-19 18:58:55 +000038
39/*******************************************************************************
40 * This structure represents the superset of information that is passed to
Juan Castillo7d199412015-12-14 09:35:25 +000041 * BL31, e.g. while passing control to it from BL2, bl31_params
Dan Handley9df48042015-03-19 18:58:55 +000042 * and other platform specific params
43 ******************************************************************************/
44typedef struct bl2_to_bl31_params_mem {
45 bl31_params_t bl31_params;
46 image_info_t bl31_image_info;
47 image_info_t bl32_image_info;
48 image_info_t bl33_image_info;
49 entry_point_info_t bl33_ep_info;
50 entry_point_info_t bl32_ep_info;
51 entry_point_info_t bl31_ep_info;
52} bl2_to_bl31_params_mem_t;
53
54
55static bl2_to_bl31_params_mem_t bl31_params_mem;
56
57
58/* Weak definitions may be overridden in specific ARM standard platform */
Dan Handley9df48042015-03-19 18:58:55 +000059#pragma weak bl2_plat_get_bl31_params
60#pragma weak bl2_plat_get_bl31_ep_info
61#pragma weak bl2_plat_flush_bl31_params
62#pragma weak bl2_plat_set_bl31_ep_info
Juan Castilloa72b6472015-12-10 15:49:17 +000063#pragma weak bl2_plat_get_scp_bl2_meminfo
Dan Handley9df48042015-03-19 18:58:55 +000064#pragma weak bl2_plat_get_bl32_meminfo
65#pragma weak bl2_plat_set_bl32_ep_info
66#pragma weak bl2_plat_get_bl33_meminfo
67#pragma weak bl2_plat_set_bl33_ep_info
68
David Wang0ba499f2016-03-07 11:02:57 +080069#if ARM_BL31_IN_DRAM
70meminfo_t *bl2_plat_sec_mem_layout(void)
71{
72 static meminfo_t bl2_dram_layout
73 __aligned(CACHE_WRITEBACK_GRANULE) = {
74 .total_base = BL31_BASE,
75 .total_size = (ARM_AP_TZC_DRAM1_BASE +
76 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE,
77 .free_base = BL31_BASE,
78 .free_size = (ARM_AP_TZC_DRAM1_BASE +
79 ARM_AP_TZC_DRAM1_SIZE) - BL31_BASE
80 };
Dan Handley9df48042015-03-19 18:58:55 +000081
David Wang0ba499f2016-03-07 11:02:57 +080082 return &bl2_dram_layout;
83}
84#else
Dan Handley9df48042015-03-19 18:58:55 +000085meminfo_t *bl2_plat_sec_mem_layout(void)
86{
87 return &bl2_tzram_layout;
88}
Yatharth Kocharf9a0f162016-09-13 17:07:57 +010089#endif /* ARM_BL31_IN_DRAM */
Dan Handley9df48042015-03-19 18:58:55 +000090
91/*******************************************************************************
92 * This function assigns a pointer to the memory that the platform has kept
93 * aside to pass platform specific and trusted firmware related information
94 * to BL31. This memory is allocated by allocating memory to
95 * bl2_to_bl31_params_mem_t structure which is a superset of all the
96 * structure whose information is passed to BL31
97 * NOTE: This function should be called only once and should be done
98 * before generating params to BL31
99 ******************************************************************************/
100bl31_params_t *bl2_plat_get_bl31_params(void)
101{
102 bl31_params_t *bl2_to_bl31_params;
103
104 /*
105 * Initialise the memory for all the arguments that needs to
Juan Castillo7d199412015-12-14 09:35:25 +0000106 * be passed to BL31
Dan Handley9df48042015-03-19 18:58:55 +0000107 */
Douglas Raillarda8954fc2017-01-26 15:54:44 +0000108 zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t));
Dan Handley9df48042015-03-19 18:58:55 +0000109
110 /* Assign memory for TF related information */
111 bl2_to_bl31_params = &bl31_params_mem.bl31_params;
112 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
113
Juan Castillo7d199412015-12-14 09:35:25 +0000114 /* Fill BL31 related information */
Dan Handley9df48042015-03-19 18:58:55 +0000115 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info;
116 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
117 VERSION_1, 0);
118
Juan Castillo7d199412015-12-14 09:35:25 +0000119 /* Fill BL32 related information if it exists */
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100120#ifdef BL32_BASE
Dan Handley9df48042015-03-19 18:58:55 +0000121 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
122 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
123 VERSION_1, 0);
124 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
125 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
126 VERSION_1, 0);
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100127#endif /* BL32_BASE */
Dan Handley9df48042015-03-19 18:58:55 +0000128
Juan Castillo7d199412015-12-14 09:35:25 +0000129 /* Fill BL33 related information */
Dan Handley9df48042015-03-19 18:58:55 +0000130 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
131 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
132 PARAM_EP, VERSION_1, 0);
133
Juan Castillo7d199412015-12-14 09:35:25 +0000134 /* BL33 expects to receive the primary CPU MPID (through x0) */
Dan Handley9df48042015-03-19 18:58:55 +0000135 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
136
137 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
138 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
139 VERSION_1, 0);
140
141 return bl2_to_bl31_params;
142}
143
144/* Flush the TF params and the TF plat params */
145void bl2_plat_flush_bl31_params(void)
146{
147 flush_dcache_range((unsigned long)&bl31_params_mem,
148 sizeof(bl2_to_bl31_params_mem_t));
149}
150
151/*******************************************************************************
152 * This function returns a pointer to the shared memory that the platform
153 * has kept to point to entry point information of BL31 to BL2
154 ******************************************************************************/
155struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
156{
157#if DEBUG
158 bl31_params_mem.bl31_ep_info.args.arg1 = ARM_BL31_PLAT_PARAM_VAL;
159#endif
160
161 return &bl31_params_mem.bl31_ep_info;
162}
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100163#endif /* LOAD_IMAGE_V2 */
Dan Handley9df48042015-03-19 18:58:55 +0000164
165/*******************************************************************************
166 * BL1 has passed the extents of the trusted SRAM that should be visible to BL2
167 * in x0. This memory layout is sitting at the base of the free trusted SRAM.
168 * Copy it to a safe location before its reclaimed by later BL2 functionality.
169 ******************************************************************************/
170void arm_bl2_early_platform_setup(meminfo_t *mem_layout)
171{
172 /* Initialize the console to provide early debug support */
173 console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ,
174 ARM_CONSOLE_BAUDRATE);
175
176 /* Setup the BL2 memory layout */
177 bl2_tzram_layout = *mem_layout;
178
179 /* Initialise the IO layer and register platform IO devices */
180 plat_arm_io_setup();
181}
182
183void bl2_early_platform_setup(meminfo_t *mem_layout)
184{
185 arm_bl2_early_platform_setup(mem_layout);
Soby Mathew1ced6b82017-06-12 12:37:10 +0100186 generic_delay_timer_init();
Dan Handley9df48042015-03-19 18:58:55 +0000187}
188
189/*
190 * Perform ARM standard platform setup.
191 */
192void arm_bl2_platform_setup(void)
193{
194 /* Initialize the secure environment */
195 plat_arm_security_setup();
196}
197
198void bl2_platform_setup(void)
199{
200 arm_bl2_platform_setup();
201}
202
203/*******************************************************************************
204 * Perform the very early platform specific architectural setup here. At the
205 * moment this is only initializes the mmu in a quick and dirty way.
206 ******************************************************************************/
207void arm_bl2_plat_arch_setup(void)
208{
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100209 arm_setup_page_tables(bl2_tzram_layout.total_base,
Dan Handley9df48042015-03-19 18:58:55 +0000210 bl2_tzram_layout.total_size,
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +0100211 BL_CODE_BASE,
Masahiro Yamada51bef612017-01-18 02:10:08 +0900212 BL_CODE_END,
Sandrine Bailleuxecdc4d32016-07-08 14:38:16 +0100213 BL_RO_DATA_BASE,
Masahiro Yamada51bef612017-01-18 02:10:08 +0900214 BL_RO_DATA_END
Dan Handley9df48042015-03-19 18:58:55 +0000215#if USE_COHERENT_MEM
Masahiro Yamada0fac5af2016-12-28 16:11:41 +0900216 , BL_COHERENT_RAM_BASE,
217 BL_COHERENT_RAM_END
Dan Handley9df48042015-03-19 18:58:55 +0000218#endif
219 );
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100220
221#ifdef AARCH32
222 enable_mmu_secure(0);
223#else
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100224 enable_mmu_el1(0);
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100225#endif
Dan Handley9df48042015-03-19 18:58:55 +0000226}
227
228void bl2_plat_arch_setup(void)
229{
230 arm_bl2_plat_arch_setup();
231}
232
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100233#if LOAD_IMAGE_V2
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000234int arm_bl2_handle_post_image_load(unsigned int image_id)
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100235{
236 int err = 0;
237 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
Summer Qin9db8f2e2017-04-24 16:49:28 +0100238#ifdef SPD_opteed
239 bl_mem_params_node_t *pager_mem_params = NULL;
240 bl_mem_params_node_t *paged_mem_params = NULL;
241#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100242 assert(bl_mem_params);
243
244 switch (image_id) {
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100245#ifdef AARCH64
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100246 case BL32_IMAGE_ID:
Summer Qin9db8f2e2017-04-24 16:49:28 +0100247#ifdef SPD_opteed
248 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
249 assert(pager_mem_params);
250
251 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
252 assert(paged_mem_params);
253
254 err = parse_optee_header(&bl_mem_params->ep_info,
255 &pager_mem_params->image_info,
256 &paged_mem_params->image_info);
257 if (err != 0) {
258 WARN("OPTEE header parse error.\n");
259 }
260#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100261 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl32_entry();
262 break;
Yatharth Kochara5f77d32016-07-04 11:26:14 +0100263#endif
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100264
265 case BL33_IMAGE_ID:
266 /* BL33 expects to receive the primary CPU MPID (through r0) */
267 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
268 bl_mem_params->ep_info.spsr = arm_get_spsr_for_bl33_entry();
269 break;
270
271#ifdef SCP_BL2_BASE
272 case SCP_BL2_IMAGE_ID:
273 /* The subsequent handling of SCP_BL2 is platform specific */
274 err = plat_arm_bl2_handle_scp_bl2(&bl_mem_params->image_info);
275 if (err) {
276 WARN("Failure in platform-specific handling of SCP_BL2 image.\n");
277 }
278 break;
279#endif
280 }
281
282 return err;
283}
284
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000285/*******************************************************************************
286 * This function can be used by the platforms to update/use image
287 * information for given `image_id`.
288 ******************************************************************************/
289int bl2_plat_handle_post_image_load(unsigned int image_id)
290{
291 return arm_bl2_handle_post_image_load(image_id);
292}
293
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100294#else /* LOAD_IMAGE_V2 */
295
Dan Handley9df48042015-03-19 18:58:55 +0000296/*******************************************************************************
Juan Castilloa72b6472015-12-10 15:49:17 +0000297 * Populate the extents of memory available for loading SCP_BL2 (if used),
Dan Handley9df48042015-03-19 18:58:55 +0000298 * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2.
299 ******************************************************************************/
Juan Castilloa72b6472015-12-10 15:49:17 +0000300void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo)
Dan Handley9df48042015-03-19 18:58:55 +0000301{
Juan Castilloa72b6472015-12-10 15:49:17 +0000302 *scp_bl2_meminfo = bl2_tzram_layout;
Dan Handley9df48042015-03-19 18:58:55 +0000303}
304
305/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000306 * Before calling this function BL31 is loaded in memory and its entrypoint
Dan Handley9df48042015-03-19 18:58:55 +0000307 * is set by load_image. This is a placeholder for the platform to change
Juan Castillo7d199412015-12-14 09:35:25 +0000308 * the entrypoint of BL31 and set SPSR and security state.
Dan Handley9df48042015-03-19 18:58:55 +0000309 * On ARM standard platforms we only set the security state of the entrypoint
310 ******************************************************************************/
311void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
312 entry_point_info_t *bl31_ep_info)
313{
314 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
315 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
316 DISABLE_ALL_EXCEPTIONS);
317}
318
319
320/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000321 * Before calling this function BL32 is loaded in memory and its entrypoint
Dan Handley9df48042015-03-19 18:58:55 +0000322 * is set by load_image. This is a placeholder for the platform to change
Juan Castillo7d199412015-12-14 09:35:25 +0000323 * the entrypoint of BL32 and set SPSR and security state.
Dan Handley9df48042015-03-19 18:58:55 +0000324 * On ARM standard platforms we only set the security state of the entrypoint
325 ******************************************************************************/
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100326#ifdef BL32_BASE
Dan Handley9df48042015-03-19 18:58:55 +0000327void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
328 entry_point_info_t *bl32_ep_info)
329{
330 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
331 bl32_ep_info->spsr = arm_get_spsr_for_bl32_entry();
332}
333
334/*******************************************************************************
Dan Handley9df48042015-03-19 18:58:55 +0000335 * Populate the extents of memory available for loading BL32
336 ******************************************************************************/
337void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
338{
339 /*
340 * Populate the extents of memory available for loading BL32.
341 */
342 bl32_meminfo->total_base = BL32_BASE;
343 bl32_meminfo->free_base = BL32_BASE;
344 bl32_meminfo->total_size =
345 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
346 bl32_meminfo->free_size =
347 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
348}
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100349#endif /* BL32_BASE */
Dan Handley9df48042015-03-19 18:58:55 +0000350
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100351/*******************************************************************************
352 * Before calling this function BL33 is loaded in memory and its entrypoint
353 * is set by load_image. This is a placeholder for the platform to change
354 * the entrypoint of BL33 and set SPSR and security state.
355 * On ARM standard platforms we only set the security state of the entrypoint
356 ******************************************************************************/
357void bl2_plat_set_bl33_ep_info(image_info_t *image,
358 entry_point_info_t *bl33_ep_info)
359{
360 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
361 bl33_ep_info->spsr = arm_get_spsr_for_bl33_entry();
362}
Dan Handley9df48042015-03-19 18:58:55 +0000363
364/*******************************************************************************
365 * Populate the extents of memory available for loading BL33
366 ******************************************************************************/
367void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
368{
369 bl33_meminfo->total_base = ARM_NS_DRAM1_BASE;
370 bl33_meminfo->total_size = ARM_NS_DRAM1_SIZE;
371 bl33_meminfo->free_base = ARM_NS_DRAM1_BASE;
372 bl33_meminfo->free_size = ARM_NS_DRAM1_SIZE;
373}
Yatharth Kocharf9a0f162016-09-13 17:07:57 +0100374
375#endif /* LOAD_IMAGE_V2 */