Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 1 | /* |
johpow01 | 9131eb8 | 2020-10-06 17:55:25 -0500 | [diff] [blame] | 2 | * Copyright (c) 2019-2021, ARM Limited. All rights reserved. |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
Jimmy Brisson | 7ec175e | 2020-06-01 16:49:34 -0500 | [diff] [blame] | 10 | #include <cortex_a78.h> |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
| 13 | |
| 14 | /* Hardware handled coherency */ |
| 15 | #if HW_ASSISTED_COHERENCY == 0 |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 16 | #error "cortex_a78 must be compiled with HW_ASSISTED_COHERENCY enabled" |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 17 | #endif |
| 18 | |
Madhukar Pappireddy | 4efede7 | 2019-12-18 15:56:27 -0600 | [diff] [blame] | 19 | |
| 20 | /* -------------------------------------------------- |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 21 | * Errata Workaround for A78 Erratum 1688305. |
| 22 | * This applies to revision r0p0 and r1p0 of A78. |
Madhukar Pappireddy | 4efede7 | 2019-12-18 15:56:27 -0600 | [diff] [blame] | 23 | * Inputs: |
| 24 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 25 | * Shall clobber: x0-x17 |
| 26 | * -------------------------------------------------- |
| 27 | */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 28 | func errata_a78_1688305_wa |
Madhukar Pappireddy | 4efede7 | 2019-12-18 15:56:27 -0600 | [diff] [blame] | 29 | /* Compare x0 against revision r1p0 */ |
| 30 | mov x17, x30 |
| 31 | bl check_errata_1688305 |
| 32 | cbz x0, 1f |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 33 | mrs x1, CORTEX_A78_ACTLR2_EL1 |
johpow01 | 9131eb8 | 2020-10-06 17:55:25 -0500 | [diff] [blame] | 34 | orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_1 |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 35 | msr CORTEX_A78_ACTLR2_EL1, x1 |
Madhukar Pappireddy | 4efede7 | 2019-12-18 15:56:27 -0600 | [diff] [blame] | 36 | isb |
| 37 | 1: |
| 38 | ret x17 |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 39 | endfunc errata_a78_1688305_wa |
Madhukar Pappireddy | 4efede7 | 2019-12-18 15:56:27 -0600 | [diff] [blame] | 40 | |
| 41 | func check_errata_1688305 |
| 42 | /* Applies to r0p0 and r1p0 */ |
| 43 | mov x1, #0x10 |
| 44 | b cpu_rev_var_ls |
| 45 | endfunc check_errata_1688305 |
| 46 | |
johpow01 | b3e8294 | 2021-04-30 18:08:52 -0500 | [diff] [blame] | 47 | /* -------------------------------------------------- |
| 48 | * Errata Workaround for Cortex A78 Errata #1941498. |
| 49 | * This applies to revisions r0p0, r1p0, and r1p1. |
| 50 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 51 | * Shall clobber: x0-x17 |
| 52 | * -------------------------------------------------- |
| 53 | */ |
johpow01 | 9131eb8 | 2020-10-06 17:55:25 -0500 | [diff] [blame] | 54 | func errata_a78_1941498_wa |
| 55 | /* Compare x0 against revision <= r1p1 */ |
| 56 | mov x17, x30 |
| 57 | bl check_errata_1941498 |
| 58 | cbz x0, 1f |
| 59 | |
| 60 | /* Set bit 8 in ECTLR_EL1 */ |
| 61 | mrs x1, CORTEX_A78_CPUECTLR_EL1 |
| 62 | orr x1, x1, #CORTEX_A78_CPUECTLR_EL1_BIT_8 |
| 63 | msr CORTEX_A78_CPUECTLR_EL1, x1 |
| 64 | isb |
| 65 | 1: |
| 66 | ret x17 |
| 67 | endfunc errata_a78_1941498_wa |
| 68 | |
| 69 | func check_errata_1941498 |
| 70 | /* Check for revision <= r1p1, might need to be updated later. */ |
| 71 | mov x1, #0x11 |
| 72 | b cpu_rev_var_ls |
| 73 | endfunc check_errata_1941498 |
| 74 | |
johpow01 | b3e8294 | 2021-04-30 18:08:52 -0500 | [diff] [blame] | 75 | /* -------------------------------------------------- |
| 76 | * Errata Workaround for A78 Erratum 1951500. |
| 77 | * This applies to revisions r1p0 and r1p1 of A78. |
| 78 | * The issue also exists in r0p0 but there is no fix |
| 79 | * in that revision. |
| 80 | * Inputs: |
| 81 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 82 | * Shall clobber: x0-x17 |
| 83 | * -------------------------------------------------- |
| 84 | */ |
johpow01 | 85ea43d | 2020-10-07 15:08:01 -0500 | [diff] [blame] | 85 | func errata_a78_1951500_wa |
| 86 | /* Compare x0 against revisions r1p0 - r1p1 */ |
| 87 | mov x17, x30 |
| 88 | bl check_errata_1951500 |
| 89 | cbz x0, 1f |
| 90 | |
| 91 | msr S3_6_c15_c8_0, xzr |
| 92 | ldr x0, =0x10E3900002 |
| 93 | msr S3_6_c15_c8_2, x0 |
| 94 | ldr x0, =0x10FFF00083 |
| 95 | msr S3_6_c15_c8_3, x0 |
| 96 | ldr x0, =0x2001003FF |
| 97 | msr S3_6_c15_c8_1, x0 |
| 98 | |
| 99 | mov x0, #1 |
| 100 | msr S3_6_c15_c8_0, x0 |
| 101 | ldr x0, =0x10E3800082 |
| 102 | msr S3_6_c15_c8_2, x0 |
| 103 | ldr x0, =0x10FFF00083 |
| 104 | msr S3_6_c15_c8_3, x0 |
| 105 | ldr x0, =0x2001003FF |
| 106 | msr S3_6_c15_c8_1, x0 |
| 107 | |
| 108 | mov x0, #2 |
| 109 | msr S3_6_c15_c8_0, x0 |
| 110 | ldr x0, =0x10E3800200 |
| 111 | msr S3_6_c15_c8_2, x0 |
| 112 | ldr x0, =0x10FFF003E0 |
| 113 | msr S3_6_c15_c8_3, x0 |
| 114 | ldr x0, =0x2001003FF |
| 115 | msr S3_6_c15_c8_1, x0 |
| 116 | |
| 117 | isb |
| 118 | 1: |
| 119 | ret x17 |
| 120 | endfunc errata_a78_1951500_wa |
| 121 | |
| 122 | func check_errata_1951500 |
| 123 | /* Applies to revisions r1p0 and r1p1. */ |
| 124 | mov x1, #CPU_REV(1, 0) |
| 125 | mov x2, #CPU_REV(1, 1) |
| 126 | b cpu_rev_var_range |
| 127 | endfunc check_errata_1951500 |
| 128 | |
johpow01 | b3e8294 | 2021-04-30 18:08:52 -0500 | [diff] [blame] | 129 | /* -------------------------------------------------- |
| 130 | * Errata Workaround for Cortex A78 Errata #1821534. |
| 131 | * This applies to revisions r0p0 and r1p0. |
| 132 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 133 | * Shall clobber: x0-x17 |
| 134 | * -------------------------------------------------- |
| 135 | */ |
| 136 | func errata_a78_1821534_wa |
| 137 | /* Check revision. */ |
| 138 | mov x17, x30 |
| 139 | bl check_errata_1821534 |
| 140 | cbz x0, 1f |
| 141 | |
| 142 | /* Set bit 2 in ACTLR2_EL1 */ |
| 143 | mrs x1, CORTEX_A78_ACTLR2_EL1 |
| 144 | orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_2 |
| 145 | msr CORTEX_A78_ACTLR2_EL1, x1 |
| 146 | isb |
| 147 | 1: |
| 148 | ret x17 |
| 149 | endfunc errata_a78_1821534_wa |
| 150 | |
| 151 | func check_errata_1821534 |
| 152 | /* Applies to r0p0 and r1p0 */ |
| 153 | mov x1, #0x10 |
| 154 | b cpu_rev_var_ls |
| 155 | endfunc check_errata_1821534 |
| 156 | |
nayanpatel-arm | 80bf7a5 | 2021-08-11 13:33:00 -0700 | [diff] [blame] | 157 | /* -------------------------------------------------- |
| 158 | * Errata Workaround for Cortex A78 Errata 1952683. |
| 159 | * This applies to revision r0p0. |
| 160 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 161 | * Shall clobber: x0-x17 |
| 162 | * -------------------------------------------------- |
| 163 | */ |
| 164 | func errata_a78_1952683_wa |
| 165 | /* Check revision. */ |
| 166 | mov x17, x30 |
| 167 | bl check_errata_1952683 |
| 168 | cbz x0, 1f |
| 169 | |
| 170 | ldr x0,=0x5 |
| 171 | msr S3_6_c15_c8_0,x0 |
| 172 | ldr x0,=0xEEE10A10 |
| 173 | msr S3_6_c15_c8_2,x0 |
| 174 | ldr x0,=0xFFEF0FFF |
| 175 | msr S3_6_c15_c8_3,x0 |
| 176 | ldr x0,=0x0010F000 |
| 177 | msr S3_6_c15_c8_4,x0 |
| 178 | ldr x0,=0x0010F000 |
| 179 | msr S3_6_c15_c8_5,x0 |
| 180 | ldr x0,=0x40000080023ff |
| 181 | msr S3_6_c15_c8_1,x0 |
| 182 | ldr x0,=0x6 |
| 183 | msr S3_6_c15_c8_0,x0 |
| 184 | ldr x0,=0xEE640F34 |
| 185 | msr S3_6_c15_c8_2,x0 |
| 186 | ldr x0,=0xFFEF0FFF |
| 187 | msr S3_6_c15_c8_3,x0 |
| 188 | ldr x0,=0x40000080023ff |
| 189 | msr S3_6_c15_c8_1,x0 |
| 190 | isb |
| 191 | 1: |
| 192 | ret x17 |
| 193 | endfunc errata_a78_1952683_wa |
| 194 | |
| 195 | func check_errata_1952683 |
| 196 | /* Applies to r0p0 only */ |
| 197 | mov x1, #0x00 |
| 198 | b cpu_rev_var_ls |
| 199 | endfunc check_errata_1952683 |
| 200 | |
nayanpatel-arm | 39e0865 | 2021-09-28 17:31:50 -0700 | [diff] [blame] | 201 | /* -------------------------------------------------- |
| 202 | * Errata Workaround for Cortex A78 Errata 2132060. |
| 203 | * This applies to revisions r0p0, r1p0, r1p1, and r1p2. |
| 204 | * It is still open. |
| 205 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 206 | * Shall clobber: x0-x1, x17 |
| 207 | * -------------------------------------------------- |
| 208 | */ |
| 209 | func errata_a78_2132060_wa |
| 210 | /* Check revision. */ |
| 211 | mov x17, x30 |
| 212 | bl check_errata_2132060 |
| 213 | cbz x0, 1f |
| 214 | |
| 215 | /* Apply the workaround. */ |
| 216 | mrs x1, CORTEX_A78_CPUECTLR_EL1 |
| 217 | mov x0, #CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV |
| 218 | bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH |
| 219 | msr CORTEX_A78_CPUECTLR_EL1, x1 |
| 220 | 1: |
| 221 | ret x17 |
| 222 | endfunc errata_a78_2132060_wa |
| 223 | |
| 224 | func check_errata_2132060 |
| 225 | /* Applies to r0p0, r0p1, r1p1, and r1p2 */ |
| 226 | mov x1, #0x12 |
| 227 | b cpu_rev_var_ls |
| 228 | endfunc check_errata_2132060 |
| 229 | |
Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 230 | /* ------------------------------------------------- |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 231 | * The CPU Ops reset function for Cortex-A78 |
Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 232 | * ------------------------------------------------- |
| 233 | */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 234 | func cortex_a78_reset_func |
Madhukar Pappireddy | 4efede7 | 2019-12-18 15:56:27 -0600 | [diff] [blame] | 235 | mov x19, x30 |
| 236 | bl cpu_get_rev_var |
| 237 | mov x18, x0 |
| 238 | |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 239 | #if ERRATA_A78_1688305 |
Madhukar Pappireddy | 4efede7 | 2019-12-18 15:56:27 -0600 | [diff] [blame] | 240 | mov x0, x18 |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 241 | bl errata_a78_1688305_wa |
Madhukar Pappireddy | 4efede7 | 2019-12-18 15:56:27 -0600 | [diff] [blame] | 242 | #endif |
| 243 | |
johpow01 | 9131eb8 | 2020-10-06 17:55:25 -0500 | [diff] [blame] | 244 | #if ERRATA_A78_1941498 |
| 245 | mov x0, x18 |
| 246 | bl errata_a78_1941498_wa |
| 247 | #endif |
| 248 | |
johpow01 | 85ea43d | 2020-10-07 15:08:01 -0500 | [diff] [blame] | 249 | #if ERRATA_A78_1951500 |
| 250 | mov x0, x18 |
| 251 | bl errata_a78_1951500_wa |
| 252 | #endif |
| 253 | |
johpow01 | b3e8294 | 2021-04-30 18:08:52 -0500 | [diff] [blame] | 254 | #if ERRATA_A78_1821534 |
| 255 | mov x0, x18 |
| 256 | bl errata_a78_1821534_wa |
| 257 | #endif |
| 258 | |
nayanpatel-arm | 80bf7a5 | 2021-08-11 13:33:00 -0700 | [diff] [blame] | 259 | #if ERRATA_A78_1952683 |
| 260 | mov x0, x18 |
| 261 | bl errata_a78_1952683_wa |
| 262 | #endif |
| 263 | |
nayanpatel-arm | 39e0865 | 2021-09-28 17:31:50 -0700 | [diff] [blame] | 264 | #if ERRATA_A78_2132060 |
| 265 | mov x0, x18 |
| 266 | bl errata_a78_2132060_wa |
| 267 | #endif |
| 268 | |
Madhukar Pappireddy | 4efede7 | 2019-12-18 15:56:27 -0600 | [diff] [blame] | 269 | #if ENABLE_AMU |
Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 270 | /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ |
| 271 | mrs x0, actlr_el3 |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 272 | bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT |
Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 273 | msr actlr_el3, x0 |
| 274 | |
| 275 | /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ |
| 276 | mrs x0, actlr_el2 |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 277 | bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT |
Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 278 | msr actlr_el2, x0 |
| 279 | |
| 280 | /* Enable group0 counters */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 281 | mov x0, #CORTEX_A78_AMU_GROUP0_MASK |
Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 282 | msr CPUAMCNTENSET0_EL0, x0 |
| 283 | |
| 284 | /* Enable group1 counters */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 285 | mov x0, #CORTEX_A78_AMU_GROUP1_MASK |
Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 286 | msr CPUAMCNTENSET1_EL0, x0 |
Madhukar Pappireddy | 4efede7 | 2019-12-18 15:56:27 -0600 | [diff] [blame] | 287 | #endif |
Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 288 | |
Madhukar Pappireddy | 4efede7 | 2019-12-18 15:56:27 -0600 | [diff] [blame] | 289 | isb |
| 290 | ret x19 |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 291 | endfunc cortex_a78_reset_func |
Balint Dobszay | db2ec85 | 2019-07-15 11:46:20 +0200 | [diff] [blame] | 292 | |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 293 | /* --------------------------------------------- |
| 294 | * HW will do the cache maintenance while powering down |
| 295 | * --------------------------------------------- |
| 296 | */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 297 | func cortex_a78_core_pwr_dwn |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 298 | /* --------------------------------------------- |
| 299 | * Enable CPU power down bit in power control register |
| 300 | * --------------------------------------------- |
| 301 | */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 302 | mrs x0, CORTEX_A78_CPUPWRCTLR_EL1 |
| 303 | orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT |
| 304 | msr CORTEX_A78_CPUPWRCTLR_EL1, x0 |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 305 | isb |
| 306 | ret |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 307 | endfunc cortex_a78_core_pwr_dwn |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 308 | |
| 309 | /* |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 310 | * Errata printing function for cortex_a78. Must follow AAPCS. |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 311 | */ |
| 312 | #if REPORT_ERRATA |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 313 | func cortex_a78_errata_report |
Madhukar Pappireddy | 4efede7 | 2019-12-18 15:56:27 -0600 | [diff] [blame] | 314 | stp x8, x30, [sp, #-16]! |
| 315 | |
| 316 | bl cpu_get_rev_var |
| 317 | mov x8, x0 |
| 318 | |
| 319 | /* |
| 320 | * Report all errata. The revision-variant information is passed to |
| 321 | * checking functions of each errata. |
| 322 | */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 323 | report_errata ERRATA_A78_1688305, cortex_a78, 1688305 |
johpow01 | 9131eb8 | 2020-10-06 17:55:25 -0500 | [diff] [blame] | 324 | report_errata ERRATA_A78_1941498, cortex_a78, 1941498 |
johpow01 | 85ea43d | 2020-10-07 15:08:01 -0500 | [diff] [blame] | 325 | report_errata ERRATA_A78_1951500, cortex_a78, 1951500 |
johpow01 | b3e8294 | 2021-04-30 18:08:52 -0500 | [diff] [blame] | 326 | report_errata ERRATA_A78_1821534, cortex_a78, 1821534 |
nayanpatel-arm | 80bf7a5 | 2021-08-11 13:33:00 -0700 | [diff] [blame] | 327 | report_errata ERRATA_A78_1952683, cortex_a78, 1952683 |
nayanpatel-arm | 39e0865 | 2021-09-28 17:31:50 -0700 | [diff] [blame] | 328 | report_errata ERRATA_A78_2132060, cortex_a78, 2132060 |
Madhukar Pappireddy | 4efede7 | 2019-12-18 15:56:27 -0600 | [diff] [blame] | 329 | |
| 330 | ldp x8, x30, [sp], #16 |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 331 | ret |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 332 | endfunc cortex_a78_errata_report |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 333 | #endif |
| 334 | |
| 335 | /* --------------------------------------------- |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 336 | * This function provides cortex_a78 specific |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 337 | * register information for crash reporting. |
| 338 | * It needs to return with x6 pointing to |
| 339 | * a list of register names in ascii and |
| 340 | * x8 - x15 having values of registers to be |
| 341 | * reported. |
| 342 | * --------------------------------------------- |
| 343 | */ |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 344 | .section .rodata.cortex_a78_regs, "aS" |
| 345 | cortex_a78_regs: /* The ascii list of register names to be reported */ |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 346 | .asciz "cpuectlr_el1", "" |
| 347 | |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 348 | func cortex_a78_cpu_reg_dump |
| 349 | adr x6, cortex_a78_regs |
| 350 | mrs x8, CORTEX_A78_CPUECTLR_EL1 |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 351 | ret |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 352 | endfunc cortex_a78_cpu_reg_dump |
Louis Mayencourt | f57f108 | 2019-05-14 11:00:45 +0100 | [diff] [blame] | 353 | |
Jimmy Brisson | 3571fb9 | 2020-06-01 10:18:22 -0500 | [diff] [blame] | 354 | declare_cpu_ops cortex_a78, CORTEX_A78_MIDR, \ |
| 355 | cortex_a78_reset_func, \ |
| 356 | cortex_a78_core_pwr_dwn |