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Juan Castillo0c70c572014-08-12 13:04:43 +01001/*
Jeenu Viswambharan75421132018-01-31 14:52:08 +00002 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
Dan Handleyed6ff952014-05-14 17:44:19 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handleyed6ff952014-05-14 17:44:19 +01005 */
6
7#ifndef __FVP_DEF_H__
8#define __FVP_DEF_H__
9
Soby Mathew47e43f22016-02-01 14:04:34 +000010#ifndef FVP_CLUSTER_COUNT
11#define FVP_CLUSTER_COUNT 2
12#endif
Jeenu Viswambharan75421132018-01-31 14:52:08 +000013
14#ifndef FVP_MAX_CPUS_PER_CLUSTER
Dan Handley2b6b5742015-03-19 19:17:53 +000015#define FVP_MAX_CPUS_PER_CLUSTER 4
Jeenu Viswambharan75421132018-01-31 14:52:08 +000016#endif
Dan Handley2b6b5742015-03-19 19:17:53 +000017
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000018#ifndef FVP_MAX_PE_PER_CPU
19# define FVP_MAX_PE_PER_CPU 1
20#endif
21
Dan Handley2b6b5742015-03-19 19:17:53 +000022#define FVP_PRIMARY_CPU 0x0
Juan Castillo0c70c572014-08-12 13:04:43 +010023
Soby Mathew7356b1e2016-03-24 10:12:42 +000024/* Defines for the Interconnect build selection */
25#define FVP_CCI 1
26#define FVP_CCN 2
27
Dan Handleyed6ff952014-05-14 17:44:19 +010028/*******************************************************************************
29 * FVP memory map related constants
30 ******************************************************************************/
31
Dan Handley2b6b5742015-03-19 19:17:53 +000032#define FLASH1_BASE 0x0c000000
33#define FLASH1_SIZE 0x04000000
Juan Castillo0c70c572014-08-12 13:04:43 +010034
Dan Handley2b6b5742015-03-19 19:17:53 +000035#define PSRAM_BASE 0x14000000
36#define PSRAM_SIZE 0x04000000
Juan Castillo42a617d2014-09-24 10:00:06 +010037
Dan Handley2b6b5742015-03-19 19:17:53 +000038#define VRAM_BASE 0x18000000
39#define VRAM_SIZE 0x02000000
Dan Handleyed6ff952014-05-14 17:44:19 +010040
41/* Aggregate of all devices in the first GB */
Dan Handley2b6b5742015-03-19 19:17:53 +000042#define DEVICE0_BASE 0x20000000
43#define DEVICE0_SIZE 0x0c200000
Dan Handleyed6ff952014-05-14 17:44:19 +010044
Soby Mathew7356b1e2016-03-24 10:12:42 +000045/*
46 * In case of FVP models with CCN, the CCN register space overlaps into
47 * the NSRAM area.
48 */
49#if FVP_INTERCONNECT_DRIVER == FVP_CCN
50#define DEVICE1_BASE 0x2e000000
51#define DEVICE1_SIZE 0x1A00000
52#else
Dan Handley2b6b5742015-03-19 19:17:53 +000053#define DEVICE1_BASE 0x2f000000
54#define DEVICE1_SIZE 0x200000
Soby Mathew7356b1e2016-03-24 10:12:42 +000055#define NSRAM_BASE 0x2e000000
56#define NSRAM_SIZE 0x10000
57#endif
Juan Castillo31a68f02015-04-14 12:49:03 +010058/* Devices in the second GB */
59#define DEVICE2_BASE 0x7fe00000
60#define DEVICE2_SIZE 0x00200000
61
Dan Handley2b6b5742015-03-19 19:17:53 +000062#define PCIE_EXP_BASE 0x40000000
63#define TZRNG_BASE 0x7fe60000
Juan Castillobfb7fa62016-01-22 11:05:57 +000064
65/* Non-volatile counters */
66#define TRUSTED_NVCTR_BASE 0x7fe70000
67#define TFW_NVCTR_BASE (TRUSTED_NVCTR_BASE + 0x0000)
68#define TFW_NVCTR_SIZE 4
69#define NTFW_CTR_BASE (TRUSTED_NVCTR_BASE + 0x0004)
70#define NTFW_CTR_SIZE 4
Juan Castillo31a68f02015-04-14 12:49:03 +010071
72/* Keys */
73#define SOC_KEYS_BASE 0x7fe80000
74#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000)
75#define TZ_PUB_KEY_HASH_SIZE 32
76#define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020)
77#define HU_KEY_SIZE 16
78#define END_KEY_BASE (SOC_KEYS_BASE + 0x0044)
79#define END_KEY_SIZE 32
Juan Castillof3e02182014-12-19 09:28:30 +000080
Dan Handley2b6b5742015-03-19 19:17:53 +000081/* Constants to distinguish FVP type */
82#define HBI_BASE_FVP 0x020
83#define REV_BASE_FVP_V0 0x0
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +010084#define REV_BASE_FVP_REVC 0x2
Juan Castillof3e02182014-12-19 09:28:30 +000085
Dan Handley2b6b5742015-03-19 19:17:53 +000086#define HBI_FOUNDATION_FVP 0x010
87#define REV_FOUNDATION_FVP_V2_0 0x0
88#define REV_FOUNDATION_FVP_V2_1 0x1
89#define REV_FOUNDATION_FVP_v9_1 0x2
Sandrine Bailleux8b33d702016-09-22 09:46:50 +010090#define REV_FOUNDATION_FVP_v9_6 0x3
Dan Handleyed6ff952014-05-14 17:44:19 +010091
Dan Handley2b6b5742015-03-19 19:17:53 +000092#define BLD_GIC_VE_MMAP 0x0
93#define BLD_GIC_A53A57_MMAP 0x1
Dan Handleyed6ff952014-05-14 17:44:19 +010094
Dan Handley2b6b5742015-03-19 19:17:53 +000095#define ARCH_MODEL 0x1
Dan Handleyed6ff952014-05-14 17:44:19 +010096
97/* FVP Power controller base address*/
Dan Handley2b6b5742015-03-19 19:17:53 +000098#define PWRC_BASE 0x1c100000
Dan Handleyed6ff952014-05-14 17:44:19 +010099
Ryan Harkinf96fc8f2015-03-17 14:54:01 +0000100/* FVP SP804 timer frequency is 35 MHz*/
Juan Castillofd383b42015-12-01 16:10:15 +0000101#define SP804_TIMER_CLKMULT 1
102#define SP804_TIMER_CLKDIV 35
103
104/* SP810 controller. FVP specific flags */
105#define FVP_SP810_CTRL_TIM0_OV (1 << 16)
106#define FVP_SP810_CTRL_TIM1_OV (1 << 18)
107#define FVP_SP810_CTRL_TIM2_OV (1 << 20)
108#define FVP_SP810_CTRL_TIM3_OV (1 << 22)
Dan Handleyed6ff952014-05-14 17:44:19 +0100109
110/*******************************************************************************
Dan Handleyed6ff952014-05-14 17:44:19 +0100111 * GIC-400 & interrupt handling related constants
112 ******************************************************************************/
113/* VE compatible GIC memory map */
114#define VE_GICD_BASE 0x2c001000
115#define VE_GICC_BASE 0x2c002000
116#define VE_GICH_BASE 0x2c004000
117#define VE_GICV_BASE 0x2c006000
118
119/* Base FVP compatible GIC memory map */
120#define BASE_GICD_BASE 0x2f000000
121#define BASE_GICR_BASE 0x2f100000
122#define BASE_GICC_BASE 0x2c000000
123#define BASE_GICH_BASE 0x2c010000
124#define BASE_GICV_BASE 0x2c02f000
125
Vikram Kanigirif3bcea22015-06-24 17:51:09 +0100126#define FVP_IRQ_TZ_WDOG 56
127#define FVP_IRQ_SEC_SYS_TIMER 57
Soby Mathew69817f72014-07-14 15:43:21 +0100128
Soby Mathew69817f72014-07-14 15:43:21 +0100129
Dan Handleyed6ff952014-05-14 17:44:19 +0100130/*******************************************************************************
131 * TrustZone address space controller related constants
132 ******************************************************************************/
Dan Handleyed6ff952014-05-14 17:44:19 +0100133
Dan Handleyed6ff952014-05-14 17:44:19 +0100134/* NSAIDs used by devices in TZC filter 0 on FVP */
135#define FVP_NSAID_DEFAULT 0
136#define FVP_NSAID_PCI 1
137#define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */
138#define FVP_NSAID_AP 9 /* Application Processors */
139#define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */
140
141/* NSAIDs used by devices in TZC filter 2 on FVP */
142#define FVP_NSAID_HDLCD0 2
143#define FVP_NSAID_CLCD 7
144
Roberto Vargasbcca6c62018-06-11 16:15:35 +0100145/*******************************************************************************
146 * Memprotect definitions
147 ******************************************************************************/
148/* PSCI memory protect definitions:
149 * This variable is stored in a non-secure flash because some ARM reference
150 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT
151 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions.
152 */
153#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
154 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
155
Dan Handleyed6ff952014-05-14 17:44:19 +0100156#endif /* __FVP_DEF_H__ */