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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Rohit Mathew96ee83a2023-12-26 22:33:03 +00002 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01006#ifndef ARM_DEF_H
7#define ARM_DEF_H
Dan Handley9df48042015-03-19 18:58:55 +00008
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009#include <arch.h>
10#include <common/interrupt_props.h>
11#include <common/tbbr/tbbr_img_def.h>
12#include <drivers/arm/gic_common.h>
13#include <lib/utils_def.h>
14#include <lib/xlat_tables/xlat_tables_defs.h>
Rohit Mathew96ee83a2023-12-26 22:33:03 +000015#include <plat/arm/board/common/rotpk/rotpk_def.h>
Manish V Badarkhe55861512020-03-27 13:25:51 +000016#include <plat/arm/common/smccc_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <plat/common/common_def.h>
Dan Handley9df48042015-03-19 18:58:55 +000018
19/******************************************************************************
20 * Definitions common to all ARM standard platforms
21 *****************************************************************************/
22
Max Shvetsov06dba292019-12-06 11:50:12 +000023
Juan Castillo7d199412015-12-14 09:35:25 +000024/* Special value used to verify platform parameters from BL2 to BL31 */
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +000025#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978)
Dan Handley9df48042015-03-19 18:58:55 +000026
Deepika Bhavnani4287c0c2019-12-13 10:23:18 -060027#define ARM_SYSTEM_COUNT U(1)
Dan Handley9df48042015-03-19 18:58:55 +000028
29#define ARM_CACHE_WRITEBACK_SHIFT 6
30
Soby Mathewfec4eb72015-07-01 16:16:20 +010031/*
32 * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The
33 * power levels have a 1:1 mapping with the MPIDR affinity levels.
34 */
35#define ARM_PWR_LVL0 MPIDR_AFFLVL0
36#define ARM_PWR_LVL1 MPIDR_AFFLVL1
Soby Mathewa869de12015-05-08 10:18:59 +010037#define ARM_PWR_LVL2 MPIDR_AFFLVL2
Chandni Cherukuri9ec4a112018-10-16 14:42:19 +053038#define ARM_PWR_LVL3 MPIDR_AFFLVL3
Soby Mathewfec4eb72015-07-01 16:16:20 +010039
40/*
41 * Macros for local power states in ARM platforms encoded by State-ID field
42 * within the power-state parameter.
43 */
44/* Local power state for power domains in Run state. */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010045#define ARM_LOCAL_STATE_RUN U(0)
Soby Mathewfec4eb72015-07-01 16:16:20 +010046/* Local power state for retention. Valid only for CPU power domains */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010047#define ARM_LOCAL_STATE_RET U(1)
Soby Mathewfec4eb72015-07-01 16:16:20 +010048/* Local power state for OFF/power-down. Valid for CPU and cluster power
49 domains */
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +010050#define ARM_LOCAL_STATE_OFF U(2)
Soby Mathewfec4eb72015-07-01 16:16:20 +010051
Dan Handley9df48042015-03-19 18:58:55 +000052/* Memory location options for TSP */
53#define ARM_TRUSTED_SRAM_ID 0
54#define ARM_TRUSTED_DRAM_ID 1
55#define ARM_DRAM_ID 2
56
Gary Morrison3d7f6542021-01-27 13:08:47 -060057#ifdef PLAT_ARM_TRUSTED_SRAM_BASE
laurenw-arm7c7b1982020-10-21 13:34:40 -050058#define ARM_TRUSTED_SRAM_BASE PLAT_ARM_TRUSTED_SRAM_BASE
59#else
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010060#define ARM_TRUSTED_SRAM_BASE UL(0x04000000)
Gary Morrison3d7f6542021-01-27 13:08:47 -060061#endif /* PLAT_ARM_TRUSTED_SRAM_BASE */
laurenw-arm7c7b1982020-10-21 13:34:40 -050062
Dan Handley9df48042015-03-19 18:58:55 +000063#define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE
Antonio Nino Diaz5f475792018-10-15 14:58:11 +010064#define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */
Dan Handley9df48042015-03-19 18:58:55 +000065
66/* The remaining Trusted SRAM is used to load the BL images */
67#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \
68 ARM_SHARED_RAM_SIZE)
69#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \
70 ARM_SHARED_RAM_SIZE)
71
72/*
Zelalem Awekec43c5632021-07-12 23:41:05 -050073 * The top 16MB (or 64MB if RME is enabled) of DRAM1 is configured as
74 * follows:
Dan Handley9df48042015-03-19 18:58:55 +000075 * - SCP TZC DRAM: If present, DRAM reserved for SCP use
Zelalem Awekec43c5632021-07-12 23:41:05 -050076 * - L1 GPT DRAM: Reserved for L1 GPT if RME is enabled
77 * - REALM DRAM: Reserved for Realm world if RME is enabled
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +000078 * - TF-A <-> RMM SHARED: Area shared for communication between TF-A and RMM
Manish V Badarkheb65ae4e2022-12-12 10:14:25 +000079 * - Event Log: Area for Event Log if MEASURED_BOOT feature is enabled
Dan Handley9df48042015-03-19 18:58:55 +000080 * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use
Zelalem Awekec43c5632021-07-12 23:41:05 -050081 *
johpow019d134022021-06-16 17:57:28 -050082 * RME enabled(64MB) RME not enabled(16MB)
83 * -------------------- -------------------
84 * | | | |
85 * | AP TZC (~28MB) | | AP TZC (~14MB) |
86 * -------------------- -------------------
Manish V Badarkheb65ae4e2022-12-12 10:14:25 +000087 * | Event Log | | Event Log |
88 * | (4KB) | | (4KB) |
89 * -------------------- -------------------
90 * | REALM (RMM) | | |
91 * | (32MB - 4KB) | | EL3 TZC (2MB) |
92 * -------------------- -------------------
johpow019d134022021-06-16 17:57:28 -050093 * | | | |
Manish V Badarkheb65ae4e2022-12-12 10:14:25 +000094 * | TF-A <-> RMM | | SCP TZC |
95 * | SHARED (4KB) | 0xFFFF_FFFF-------------------
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +000096 * --------------------
97 * | |
98 * | EL3 TZC (3MB) |
99 * --------------------
johpow019d134022021-06-16 17:57:28 -0500100 * | L1 GPT + SCP TZC |
101 * | (~1MB) |
Zelalem Awekec43c5632021-07-12 23:41:05 -0500102 * 0xFFFF_FFFF --------------------
Dan Handley9df48042015-03-19 18:58:55 +0000103 */
Zelalem Awekec43c5632021-07-12 23:41:05 -0500104#if ENABLE_RME
105#define ARM_TZC_DRAM1_SIZE UL(0x04000000) /* 64MB */
106/*
107 * Define a region within the TZC secured DRAM for use by EL3 runtime
108 * firmware. This region is meant to be NOLOAD and will not be zero
Chris Kay33bfc5e2023-02-14 11:30:04 +0000109 * initialized. Data sections with the attribute `.arm_el3_tzc_dram` will be
Zelalem Awekec43c5632021-07-12 23:41:05 -0500110 * placed here. 3MB region is reserved if RME is enabled, 2MB otherwise.
111 */
112#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00300000) /* 3MB */
113#define ARM_L1_GPT_SIZE UL(0x00100000) /* 1MB */
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +0000114/* 32MB - ARM_EL3_RMM_SHARED_SIZE */
115#define ARM_REALM_SIZE (UL(0x02000000) - \
116 ARM_EL3_RMM_SHARED_SIZE)
117#define ARM_EL3_RMM_SHARED_SIZE (PAGE_SIZE) /* 4KB */
Zelalem Awekec43c5632021-07-12 23:41:05 -0500118#else
119#define ARM_TZC_DRAM1_SIZE UL(0x01000000) /* 16MB */
120#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2MB */
121#define ARM_L1_GPT_SIZE UL(0)
122#define ARM_REALM_SIZE UL(0)
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +0000123#define ARM_EL3_RMM_SHARED_SIZE UL(0)
Zelalem Awekec43c5632021-07-12 23:41:05 -0500124#endif /* ENABLE_RME */
Dan Handley9df48042015-03-19 18:58:55 +0000125
126#define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
Zelalem Awekec43c5632021-07-12 23:41:05 -0500127 ARM_DRAM1_SIZE - \
128 (ARM_SCP_TZC_DRAM1_SIZE + \
129 ARM_L1_GPT_SIZE))
Dan Handley9df48042015-03-19 18:58:55 +0000130#define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE
131#define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \
Zelalem Awekec43c5632021-07-12 23:41:05 -0500132 ARM_SCP_TZC_DRAM1_SIZE - 1U)
Manish V Badarkheb65ae4e2022-12-12 10:14:25 +0000133
134# if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \
135MEASURED_BOOT
136#define ARM_EVENT_LOG_DRAM1_SIZE UL(0x00001000) /* 4KB */
137
138#if ENABLE_RME
139#define ARM_EVENT_LOG_DRAM1_BASE (ARM_REALM_BASE - \
140 ARM_EVENT_LOG_DRAM1_SIZE)
141#else
142#define ARM_EVENT_LOG_DRAM1_BASE (ARM_EL3_TZC_DRAM1_BASE - \
143 ARM_EVENT_LOG_DRAM1_SIZE)
144#endif /* ENABLE_RME */
145#define ARM_EVENT_LOG_DRAM1_END (ARM_EVENT_LOG_DRAM1_BASE + \
146 ARM_EVENT_LOG_DRAM1_SIZE - \
147 1U)
148#else
149#define ARM_EVENT_LOG_DRAM1_SIZE UL(0)
150#endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */
151
Zelalem Awekec43c5632021-07-12 23:41:05 -0500152#if ENABLE_RME
Rohit Mathew47a9a3f2024-01-18 22:32:52 +0000153#define ARM_L1_GPT_BASE (ARM_DRAM1_BASE + \
Zelalem Awekec43c5632021-07-12 23:41:05 -0500154 ARM_DRAM1_SIZE - \
155 ARM_L1_GPT_SIZE)
Rohit Mathew47a9a3f2024-01-18 22:32:52 +0000156#define ARM_L1_GPT_END (ARM_L1_GPT_BASE + \
Zelalem Awekec43c5632021-07-12 23:41:05 -0500157 ARM_L1_GPT_SIZE - 1U)
Dan Handley9df48042015-03-19 18:58:55 +0000158
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +0000159#define ARM_REALM_BASE (ARM_EL3_RMM_SHARED_BASE - \
160 ARM_REALM_SIZE)
161
Zelalem Awekec43c5632021-07-12 23:41:05 -0500162#define ARM_REALM_END (ARM_REALM_BASE + ARM_REALM_SIZE - 1U)
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +0000163
164#define ARM_EL3_RMM_SHARED_BASE (ARM_DRAM1_BASE + \
165 ARM_DRAM1_SIZE - \
166 (ARM_SCP_TZC_DRAM1_SIZE + \
167 ARM_L1_GPT_SIZE + \
168 ARM_EL3_RMM_SHARED_SIZE + \
169 ARM_EL3_TZC_DRAM1_SIZE))
170
171#define ARM_EL3_RMM_SHARED_END (ARM_EL3_RMM_SHARED_BASE + \
172 ARM_EL3_RMM_SHARED_SIZE - 1U)
Zelalem Awekec43c5632021-07-12 23:41:05 -0500173#endif /* ENABLE_RME */
174
175#define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \
176 ARM_EL3_TZC_DRAM1_SIZE)
Soby Mathew3b5156e2017-10-05 12:27:33 +0100177#define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \
Alexei Fedorovc7176172020-07-13 12:11:05 +0100178 ARM_EL3_TZC_DRAM1_SIZE - 1U)
Soby Mathew3b5156e2017-10-05 12:27:33 +0100179
Dan Handley9df48042015-03-19 18:58:55 +0000180#define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \
Zelalem Awekec43c5632021-07-12 23:41:05 -0500181 ARM_DRAM1_SIZE - \
182 ARM_TZC_DRAM1_SIZE)
Dan Handley9df48042015-03-19 18:58:55 +0000183#define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \
Zelalem Awekec43c5632021-07-12 23:41:05 -0500184 (ARM_SCP_TZC_DRAM1_SIZE + \
185 ARM_EL3_TZC_DRAM1_SIZE + \
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +0000186 ARM_EL3_RMM_SHARED_SIZE + \
Zelalem Awekec43c5632021-07-12 23:41:05 -0500187 ARM_REALM_SIZE + \
Manish V Badarkheb65ae4e2022-12-12 10:14:25 +0000188 ARM_L1_GPT_SIZE + \
189 ARM_EVENT_LOG_DRAM1_SIZE))
190
Dan Handley9df48042015-03-19 18:58:55 +0000191#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \
Zelalem Awekec43c5632021-07-12 23:41:05 -0500192 ARM_AP_TZC_DRAM1_SIZE - 1U)
Dan Handley9df48042015-03-19 18:58:55 +0000193
Soby Mathew7e4d6652017-05-10 11:50:30 +0100194/* Define the Access permissions for Secure peripherals to NS_DRAM */
Soby Mathew7e4d6652017-05-10 11:50:30 +0100195#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE
Soby Mathew7e4d6652017-05-10 11:50:30 +0100196
Summer Qin9db8f2e2017-04-24 16:49:28 +0100197#ifdef SPD_opteed
198/*
Jens Wiklanderae73b162017-08-24 15:39:09 +0200199 * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to
200 * load/authenticate the trusted os extra image. The first 512KB of
201 * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading
202 * for OPTEE is paged image which only include the paging part using
203 * virtual memory but without "init" data. OPTEE will copy the "init" data
204 * (from pager image) to the first 512KB of TZC_DRAM, and then copy the
205 * extra image behind the "init" data.
Summer Qin9db8f2e2017-04-24 16:49:28 +0100206 */
Jens Wiklanderae73b162017-08-24 15:39:09 +0200207#define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \
208 ARM_AP_TZC_DRAM1_SIZE - \
209 ARM_OPTEE_PAGEABLE_LOAD_SIZE)
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100210#define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000)
Summer Qin9db8f2e2017-04-24 16:49:28 +0100211#define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \
212 ARM_OPTEE_PAGEABLE_LOAD_BASE, \
213 ARM_OPTEE_PAGEABLE_LOAD_SIZE, \
214 MT_MEMORY | MT_RW | MT_SECURE)
Soby Mathew874fc9e2017-09-01 13:43:50 +0100215
216/*
217 * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging
218 * support is enabled).
219 */
220#define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \
221 BL32_BASE, \
222 BL32_LIMIT - BL32_BASE, \
223 MT_MEMORY | MT_RW | MT_SECURE)
Summer Qin9db8f2e2017-04-24 16:49:28 +0100224#endif /* SPD_opteed */
Dan Handley9df48042015-03-19 18:58:55 +0000225
226#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
227#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
228 ARM_TZC_DRAM1_SIZE)
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +0000229
Dan Handley9df48042015-03-19 18:58:55 +0000230#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
Alexei Fedorovc7176172020-07-13 12:11:05 +0100231 ARM_NS_DRAM1_SIZE - 1U)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600232#ifdef PLAT_ARM_DRAM1_BASE
laurenw-arm7c7b1982020-10-21 13:34:40 -0500233#define ARM_DRAM1_BASE PLAT_ARM_DRAM1_BASE
234#else
Sandrine Bailleux6c32fc72018-10-31 14:28:17 +0100235#define ARM_DRAM1_BASE ULL(0x80000000)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600236#endif /* PLAT_ARM_DRAM1_BASE */
laurenw-arm7c7b1982020-10-21 13:34:40 -0500237
Sandrine Bailleux6c32fc72018-10-31 14:28:17 +0100238#define ARM_DRAM1_SIZE ULL(0x80000000)
Dan Handley9df48042015-03-19 18:58:55 +0000239#define ARM_DRAM1_END (ARM_DRAM1_BASE + \
Alexei Fedorovc7176172020-07-13 12:11:05 +0100240 ARM_DRAM1_SIZE - 1U)
Dan Handley9df48042015-03-19 18:58:55 +0000241
Sami Mujawara43ae7c2019-05-09 13:35:02 +0100242#define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE
Dan Handley9df48042015-03-19 18:58:55 +0000243#define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE
244#define ARM_DRAM2_END (ARM_DRAM2_BASE + \
Alexei Fedorovc7176172020-07-13 12:11:05 +0100245 ARM_DRAM2_SIZE - 1U)
AlexeiFedorov8e754f92022-12-14 17:28:11 +0000246/* Number of DRAM banks */
AlexeiFedorov334d2352022-12-29 15:57:40 +0000247#define ARM_DRAM_NUM_BANKS 2UL
Dan Handley9df48042015-03-19 18:58:55 +0000248
249#define ARM_IRQ_SEC_PHY_TIMER 29
250
251#define ARM_IRQ_SEC_SGI_0 8
252#define ARM_IRQ_SEC_SGI_1 9
253#define ARM_IRQ_SEC_SGI_2 10
254#define ARM_IRQ_SEC_SGI_3 11
255#define ARM_IRQ_SEC_SGI_4 12
256#define ARM_IRQ_SEC_SGI_5 13
257#define ARM_IRQ_SEC_SGI_6 14
258#define ARM_IRQ_SEC_SGI_7 15
259
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000260/*
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100261 * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3
262 * terminology. On a GICv2 system or mode, the lists will be merged and treated
263 * as Group 0 interrupts.
264 */
265#define ARM_G1S_IRQ_PROPS(grp) \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100266 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100267 GIC_INTR_CFG_LEVEL), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100268 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100269 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100270 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100271 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100272 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100273 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100274 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100275 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100276 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100277 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100278 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100279 GIC_INTR_CFG_EDGE)
280
281#define ARM_G0_IRQ_PROPS(grp) \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100282 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100283 GIC_INTR_CFG_EDGE), \
Antonio Nino Diaze590fd52018-08-21 09:42:26 +0100284 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \
Jeenu Viswambharan723dce02017-09-22 08:59:59 +0100285 GIC_INTR_CFG_EDGE)
286
johpow019d134022021-06-16 17:57:28 -0500287#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
288 ARM_SHARED_RAM_BASE, \
289 ARM_SHARED_RAM_SIZE, \
290 MT_DEVICE | MT_RW | EL3_PAS)
Dan Handley9df48042015-03-19 18:58:55 +0000291
johpow019d134022021-06-16 17:57:28 -0500292#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
293 ARM_NS_DRAM1_BASE, \
294 ARM_NS_DRAM1_SIZE, \
295 MT_MEMORY | MT_RW | MT_NS)
Dan Handley9df48042015-03-19 18:58:55 +0000296
johpow019d134022021-06-16 17:57:28 -0500297#define ARM_MAP_DRAM2 MAP_REGION_FLAT( \
298 ARM_DRAM2_BASE, \
299 ARM_DRAM2_SIZE, \
300 MT_MEMORY | MT_RW | MT_NS)
Roberto Vargasf8fda102017-08-08 11:27:20 +0100301
johpow019d134022021-06-16 17:57:28 -0500302#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \
303 TSP_SEC_MEM_BASE, \
304 TSP_SEC_MEM_SIZE, \
305 MT_MEMORY | MT_RW | MT_SECURE)
Dan Handley9df48042015-03-19 18:58:55 +0000306
David Wang0ba499f2016-03-07 11:02:57 +0800307#if ARM_BL31_IN_DRAM
johpow019d134022021-06-16 17:57:28 -0500308#define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \
309 BL31_BASE, \
310 PLAT_ARM_MAX_BL31_SIZE, \
311 MT_MEMORY | MT_RW | MT_SECURE)
David Wang0ba499f2016-03-07 11:02:57 +0800312#endif
Dan Handley9df48042015-03-19 18:58:55 +0000313
johpow019d134022021-06-16 17:57:28 -0500314#define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \
315 ARM_EL3_TZC_DRAM1_BASE, \
316 ARM_EL3_TZC_DRAM1_SIZE, \
317 MT_MEMORY | MT_RW | EL3_PAS)
Soby Mathew3b5156e2017-10-05 12:27:33 +0100318
johpow019d134022021-06-16 17:57:28 -0500319#define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \
320 PLAT_ARM_TRUSTED_DRAM_BASE, \
321 PLAT_ARM_TRUSTED_DRAM_SIZE, \
322 MT_MEMORY | MT_RW | MT_SECURE)
Manish V Badarkheb65ae4e2022-12-12 10:14:25 +0000323
324# if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \
325MEASURED_BOOT
326#define ARM_MAP_EVENT_LOG_DRAM1 \
327 MAP_REGION_FLAT( \
328 ARM_EVENT_LOG_DRAM1_BASE, \
329 ARM_EVENT_LOG_DRAM1_SIZE, \
330 MT_MEMORY | MT_RW | MT_SECURE)
331#endif /* (SPD_tspd || SPD_opteed || SPD_spmd) && MEASURED_BOOT */
Achin Guptae97351d2019-10-11 15:15:19 +0100332
Zelalem Awekec43c5632021-07-12 23:41:05 -0500333#if ENABLE_RME
Soby Mathew0338e9e2022-07-06 16:01:40 +0100334/*
335 * We add the EL3_RMM_SHARED size to RMM mapping to map the region as a block.
336 * Else we end up requiring more pagetables in BL2 for ROMLIB build.
337 */
johpow019d134022021-06-16 17:57:28 -0500338#define ARM_MAP_RMM_DRAM MAP_REGION_FLAT( \
339 PLAT_ARM_RMM_BASE, \
Soby Mathew0338e9e2022-07-06 16:01:40 +0100340 (PLAT_ARM_RMM_SIZE + \
341 ARM_EL3_RMM_SHARED_SIZE), \
johpow019d134022021-06-16 17:57:28 -0500342 MT_MEMORY | MT_RW | MT_REALM)
Zelalem Awekec43c5632021-07-12 23:41:05 -0500343
344
johpow019d134022021-06-16 17:57:28 -0500345#define ARM_MAP_GPT_L1_DRAM MAP_REGION_FLAT( \
Rohit Mathew47a9a3f2024-01-18 22:32:52 +0000346 ARM_L1_GPT_BASE, \
johpow019d134022021-06-16 17:57:28 -0500347 ARM_L1_GPT_SIZE, \
348 MT_MEMORY | MT_RW | EL3_PAS)
Zelalem Awekec43c5632021-07-12 23:41:05 -0500349
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +0000350#define ARM_MAP_EL3_RMM_SHARED_MEM \
351 MAP_REGION_FLAT( \
352 ARM_EL3_RMM_SHARED_BASE, \
353 ARM_EL3_RMM_SHARED_SIZE, \
354 MT_MEMORY | MT_RW | MT_REALM)
355
Zelalem Awekec43c5632021-07-12 23:41:05 -0500356#endif /* ENABLE_RME */
Achin Guptae97351d2019-10-11 15:15:19 +0100357
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100358/*
John Tsichritzisc34341a2018-07-30 13:41:52 +0100359 * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to
360 * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides
361 * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order
362 * to be able to access the heap.
363 */
364#define ARM_MAP_BL1_RW MAP_REGION_FLAT( \
365 BL1_RW_BASE, \
366 BL1_RW_LIMIT - BL1_RW_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -0500367 MT_MEMORY | MT_RW | EL3_PAS)
John Tsichritzisc34341a2018-07-30 13:41:52 +0100368
369/*
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100370 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
371 * otherwise one region is defined containing both.
372 */
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100373#if SEPARATE_CODE_AND_RODATA
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100374#define ARM_MAP_BL_RO MAP_REGION_FLAT( \
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100375 BL_CODE_BASE, \
376 BL_CODE_END - BL_CODE_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -0500377 MT_CODE | EL3_PAS), \
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100378 MAP_REGION_FLAT( \
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100379 BL_RO_DATA_BASE, \
380 BL_RO_DATA_END \
381 - BL_RO_DATA_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -0500382 MT_RO_DATA | EL3_PAS)
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100383#else
384#define ARM_MAP_BL_RO MAP_REGION_FLAT( \
385 BL_CODE_BASE, \
386 BL_CODE_END - BL_CODE_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -0500387 MT_CODE | EL3_PAS)
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100388#endif
389#if USE_COHERENT_MEM
390#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
391 BL_COHERENT_RAM_BASE, \
392 BL_COHERENT_RAM_END \
393 - BL_COHERENT_RAM_BASE, \
Zelalem Aweke65e92632021-07-12 22:33:55 -0500394 MT_DEVICE | MT_RW | EL3_PAS)
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100395#endif
Roberto Vargase3adc372018-05-23 09:27:06 +0100396#if USE_ROMLIB
397#define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \
398 ROMLIB_RO_BASE, \
399 ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\
Zelalem Aweke65e92632021-07-12 22:33:55 -0500400 MT_CODE | EL3_PAS)
Roberto Vargase3adc372018-05-23 09:27:06 +0100401
402#define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \
403 ROMLIB_RW_BASE, \
404 ROMLIB_RW_END - ROMLIB_RW_BASE,\
Zelalem Aweke65e92632021-07-12 22:33:55 -0500405 MT_MEMORY | MT_RW | EL3_PAS)
Roberto Vargase3adc372018-05-23 09:27:06 +0100406#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100407
Dan Handley9df48042015-03-19 18:58:55 +0000408/*
Antonio Nino Diaz48bfb542018-10-11 13:02:34 +0100409 * Map mem_protect flash region with read and write permissions
410 */
411#define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \
412 V2M_FLASH_BLOCK_SIZE, \
413 MT_DEVICE | MT_RW | MT_SECURE)
Manish V Badarkhe5e3ef6c2020-07-16 05:45:25 +0100414/*
415 * Map the region for device tree configuration with read and write permissions
416 */
417#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \
418 (ARM_FW_CONFIGS_LIMIT \
419 - ARM_BL_RAM_BASE), \
Zelalem Aweke65e92632021-07-12 22:33:55 -0500420 MT_MEMORY | MT_RW | EL3_PAS)
Zelalem Awekec43c5632021-07-12 23:41:05 -0500421/*
422 * Map L0_GPT with read and write permissions
423 */
424#if ENABLE_RME
Rohit Mathew47a9a3f2024-01-18 22:32:52 +0000425#define ARM_MAP_L0_GPT_REGION MAP_REGION_FLAT(ARM_L0_GPT_BASE, \
Zelalem Awekec43c5632021-07-12 23:41:05 -0500426 ARM_L0_GPT_SIZE, \
427 MT_MEMORY | MT_RW | MT_ROOT)
428#endif
Antonio Nino Diaz48bfb542018-10-11 13:02:34 +0100429
430/*
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100431 * The max number of regions like RO(code), coherent and data required by
Dan Handley9df48042015-03-19 18:58:55 +0000432 * different BL stages which need to be mapped in the MMU.
433 */
Manish V Badarkhefc0b8532022-02-22 14:45:43 +0000434#define ARM_BL_REGIONS 7
Dan Handley9df48042015-03-19 18:58:55 +0000435
436#define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \
437 ARM_BL_REGIONS)
438
439/* Memory mapped Generic timer interfaces */
Gary Morrison3d7f6542021-01-27 13:08:47 -0600440#ifdef PLAT_ARM_SYS_CNTCTL_BASE
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600441#define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE
Gary Morrison3d7f6542021-01-27 13:08:47 -0600442#else
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100443#define ARM_SYS_CNTCTL_BASE UL(0x2a430000)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600444#endif
445
446#ifdef PLAT_ARM_SYS_CNTREAD_BASE
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600447#define ARM_SYS_CNTREAD_BASE PLAT_ARM_SYS_CNTREAD_BASE
Gary Morrison3d7f6542021-01-27 13:08:47 -0600448#else
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100449#define ARM_SYS_CNTREAD_BASE UL(0x2a800000)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600450#endif
451
452#ifdef PLAT_ARM_SYS_TIMCTL_BASE
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600453#define ARM_SYS_TIMCTL_BASE PLAT_ARM_SYS_TIMCTL_BASE
Gary Morrison3d7f6542021-01-27 13:08:47 -0600454#else
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100455#define ARM_SYS_TIMCTL_BASE UL(0x2a810000)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600456#endif
457
458#ifdef PLAT_ARM_SYS_CNT_BASE_S
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600459#define ARM_SYS_CNT_BASE_S PLAT_ARM_SYS_CNT_BASE_S
Gary Morrison3d7f6542021-01-27 13:08:47 -0600460#else
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100461#define ARM_SYS_CNT_BASE_S UL(0x2a820000)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600462#endif
463
464#ifdef PLAT_ARM_SYS_CNT_BASE_NS
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600465#define ARM_SYS_CNT_BASE_NS PLAT_ARM_SYS_CNT_BASE_NS
Gary Morrison3d7f6542021-01-27 13:08:47 -0600466#else
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100467#define ARM_SYS_CNT_BASE_NS UL(0x2a830000)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600468#endif
Dan Handley9df48042015-03-19 18:58:55 +0000469
470#define ARM_CONSOLE_BAUDRATE 115200
471
Juan Castillob6132f12015-10-06 14:01:35 +0100472/* Trusted Watchdog constants */
Gary Morrison3d7f6542021-01-27 13:08:47 -0600473#ifdef PLAT_ARM_SP805_TWDG_BASE
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600474#define ARM_SP805_TWDG_BASE PLAT_ARM_SP805_TWDG_BASE
Gary Morrison3d7f6542021-01-27 13:08:47 -0600475#else
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100476#define ARM_SP805_TWDG_BASE UL(0x2a490000)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600477#endif
Juan Castillob6132f12015-10-06 14:01:35 +0100478#define ARM_SP805_TWDG_CLK_HZ 32768
479/* The TBBR document specifies a watchdog timeout of 256 seconds. SP805
480 * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */
481#define ARM_TWDG_TIMEOUT_SEC 128
482#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \
483 ARM_TWDG_TIMEOUT_SEC)
484
Dan Handley9df48042015-03-19 18:58:55 +0000485/******************************************************************************
486 * Required platform porting definitions common to all ARM standard platforms
487 *****************************************************************************/
488
Roberto Vargasf8fda102017-08-08 11:27:20 +0100489/*
Soby Mathewfec4eb72015-07-01 16:16:20 +0100490 * This macro defines the deepest retention state possible. A higher state
491 * id will represent an invalid or a power down state.
492 */
493#define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET
494
495/*
496 * This macro defines the deepest power down states possible. Any state ID
497 * higher than this is invalid.
498 */
499#define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF
500
Dan Handley9df48042015-03-19 18:58:55 +0000501/*
502 * Some data must be aligned on the biggest cache line size in the platform.
503 * This is known only to the platform as it might have a combination of
504 * integrated and external caches.
505 */
Antonio Nino Diaz5f475792018-10-15 14:58:11 +0100506#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT)
Dan Handley9df48042015-03-19 18:58:55 +0000507
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000508/*
Manish V Badarkhe1da211a2020-05-31 10:17:59 +0100509 * To enable FW_CONFIG to be loaded by BL1, define the corresponding base
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000510 * and limit. Leave enough space of BL2 meminfo.
511 */
Manish V Badarkhe1da211a2020-05-31 10:17:59 +0100512#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
Manish V Badarkhe0bafa822020-06-29 11:14:07 +0100513#define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \
514 + (PAGE_SIZE / 2U))
Sathees Balya90950092018-11-15 14:22:30 +0000515
516/*
517 * Boot parameters passed from BL2 to BL31/BL32 are stored here
518 */
Manish V Badarkhe0bafa822020-06-29 11:14:07 +0100519#define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT)
520#define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \
521 + (PAGE_SIZE / 2U))
Sathees Balya90950092018-11-15 14:22:30 +0000522
523/*
524 * Define limit of firmware configuration memory:
Manish V Badarkhe1da211a2020-05-31 10:17:59 +0100525 * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory
Sathees Balya90950092018-11-15 14:22:30 +0000526 */
Manish V Badarkhebd305062023-06-27 11:29:34 +0100527#define ARM_FW_CONFIGS_SIZE (PAGE_SIZE * 2)
528#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + ARM_FW_CONFIGS_SIZE)
Dan Handley9df48042015-03-19 18:58:55 +0000529
Zelalem Awekec43c5632021-07-12 23:41:05 -0500530#if ENABLE_RME
531/*
532 * Store the L0 GPT on Trusted SRAM next to firmware
533 * configuration memory, 4KB aligned.
534 */
535#define ARM_L0_GPT_SIZE (PAGE_SIZE)
Rohit Mathew47a9a3f2024-01-18 22:32:52 +0000536#define ARM_L0_GPT_BASE (ARM_FW_CONFIGS_LIMIT)
537#define ARM_L0_GPT_LIMIT (ARM_L0_GPT_BASE + ARM_L0_GPT_SIZE)
Zelalem Awekec43c5632021-07-12 23:41:05 -0500538#else
539#define ARM_L0_GPT_SIZE U(0)
540#endif
541
Dan Handley9df48042015-03-19 18:58:55 +0000542/*******************************************************************************
543 * BL1 specific defines.
544 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
545 * addresses.
546 ******************************************************************************/
547#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600548#ifdef PLAT_BL1_RO_LIMIT
549#define BL1_RO_LIMIT PLAT_BL1_RO_LIMIT
550#else
Dan Handley9df48042015-03-19 18:58:55 +0000551#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \
Roberto Vargase3adc372018-05-23 09:27:06 +0100552 + (PLAT_ARM_TRUSTED_ROM_SIZE - \
553 PLAT_ARM_MAX_ROMLIB_RO_SIZE))
laurenw-arm56f1e3e2021-03-03 14:19:38 -0600554#endif
555
Dan Handley9df48042015-03-19 18:58:55 +0000556/*
Vikram Kanigiri5d86f2e2016-01-21 14:08:15 +0000557 * Put BL1 RW at the top of the Trusted SRAM.
Dan Handley9df48042015-03-19 18:58:55 +0000558 */
Dan Handley9df48042015-03-19 18:58:55 +0000559#define BL1_RW_BASE (ARM_BL_RAM_BASE + \
560 ARM_BL_RAM_SIZE - \
Roberto Vargase3adc372018-05-23 09:27:06 +0100561 (PLAT_ARM_MAX_BL1_RW_SIZE +\
562 PLAT_ARM_MAX_ROMLIB_RW_SIZE))
563#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \
564 (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE))
565
566#define ROMLIB_RO_BASE BL1_RO_LIMIT
567#define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE)
568
569#define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE)
570#define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE)
Dan Handley9df48042015-03-19 18:58:55 +0000571
572/*******************************************************************************
573 * BL2 specific defines.
574 ******************************************************************************/
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600575#if RESET_TO_BL2
Manish V Badarkhe103569f2022-06-13 18:23:01 +0100576#if ENABLE_PIE
577/*
578 * As the BL31 image size appears to be increased when built with the ENABLE_PIE
579 * option, set BL2 base address to have enough space for BL31 in Trusted SRAM.
580 */
Olivier Deprezd66c3ad2023-09-04 14:24:07 +0200581#define BL2_OFFSET (0x5000)
Manish V Badarkhe103569f2022-06-13 18:23:01 +0100582#else
Dimitris Papastamos25836492018-06-11 11:07:58 +0100583/* Put BL2 towards the middle of the Trusted SRAM */
Olivier Deprezd66c3ad2023-09-04 14:24:07 +0200584#define BL2_OFFSET (0x2000)
Manish V Badarkhe103569f2022-06-13 18:23:01 +0100585#endif /* ENABLE_PIE */
Olivier Deprezd66c3ad2023-09-04 14:24:07 +0200586
587#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \
588 (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + \
589 BL2_OFFSET)
Roberto Vargas52207802017-11-17 13:22:18 +0000590#define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
591
David Wang0ba499f2016-03-07 11:02:57 +0800592#else
Dan Handley9df48042015-03-19 18:58:55 +0000593/*
Soby Mathewaf14b462018-06-01 16:53:38 +0100594 * Put BL2 just below BL1.
Dan Handley9df48042015-03-19 18:58:55 +0000595 */
Soby Mathewaf14b462018-06-01 16:53:38 +0100596#define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
597#define BL2_LIMIT BL1_RW_BASE
David Wang0ba499f2016-03-07 11:02:57 +0800598#endif
Dan Handley9df48042015-03-19 18:58:55 +0000599
600/*******************************************************************************
Juan Castillo7d199412015-12-14 09:35:25 +0000601 * BL31 specific defines.
Dan Handley9df48042015-03-19 18:58:55 +0000602 ******************************************************************************/
Madhukar Pappireddyd7419442020-01-27 15:38:26 -0600603#if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION
David Wang0ba499f2016-03-07 11:02:57 +0800604/*
605 * Put BL31 at the bottom of TZC secured DRAM
606 */
607#define BL31_BASE ARM_AP_TZC_DRAM1_BASE
608#define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
609 PLAT_ARM_MAX_BL31_SIZE)
Madhukar Pappireddyd7419442020-01-27 15:38:26 -0600610/*
611 * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM.
612 * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten.
613 */
614#if SEPARATE_NOBITS_REGION
615#define BL31_NOBITS_BASE BL2_BASE
616#define BL31_NOBITS_LIMIT BL2_LIMIT
617#endif /* SEPARATE_NOBITS_REGION */
Qixiang Xua5f72812017-08-31 11:45:32 +0800618#elif (RESET_TO_BL31)
Manish Pandey2207e932019-11-06 13:17:46 +0000619/* Ensure Position Independent support (PIE) is enabled for this config.*/
620# if !ENABLE_PIE
621# error "BL31 must be a PIE if RESET_TO_BL31=1."
622#endif
Qixiang Xua5f72812017-08-31 11:45:32 +0800623/*
Soby Mathew68e69282018-12-12 14:13:52 +0000624 * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely
Soby Mathewc5e17452019-01-07 14:07:58 +0000625 * used for building BL31 and not used for loading BL31.
Qixiang Xua5f72812017-08-31 11:45:32 +0800626 */
Soby Mathewc5e17452019-01-07 14:07:58 +0000627# define BL31_BASE 0x0
628# define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE
David Wang0ba499f2016-03-07 11:02:57 +0800629#else
Soby Mathewaf14b462018-06-01 16:53:38 +0100630/* Put BL31 below BL2 in the Trusted SRAM.*/
631#define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
632 - PLAT_ARM_MAX_BL31_SIZE)
633#define BL31_PROGBITS_LIMIT BL2_BASE
Dimitris Papastamos25836492018-06-11 11:07:58 +0100634/*
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600635 * For RESET_TO_BL2 make sure the BL31 can grow up until BL2_BASE.
636 * This is because in the RESET_TO_BL2 configuration,
637 * BL2 is always resident.
Dimitris Papastamos25836492018-06-11 11:07:58 +0100638 */
Arvind Ram Prakash11b9b492022-11-22 14:41:00 -0600639#if RESET_TO_BL2
Dimitris Papastamos25836492018-06-11 11:07:58 +0100640#define BL31_LIMIT BL2_BASE
641#else
Dan Handley9df48042015-03-19 18:58:55 +0000642#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
David Wang0ba499f2016-03-07 11:02:57 +0800643#endif
Zelalem Awekec43c5632021-07-12 23:41:05 -0500644#endif
645
646/******************************************************************************
647 * RMM specific defines
648 *****************************************************************************/
649#if ENABLE_RME
650#define RMM_BASE (ARM_REALM_BASE)
651#define RMM_LIMIT (RMM_BASE + ARM_REALM_SIZE)
Javier Almansa Sobrino7176a772021-11-24 18:37:37 +0000652#define RMM_SHARED_BASE (ARM_EL3_RMM_SHARED_BASE)
653#define RMM_SHARED_SIZE (ARM_EL3_RMM_SHARED_SIZE)
Dimitris Papastamos25836492018-06-11 11:07:58 +0100654#endif
Dan Handley9df48042015-03-19 18:58:55 +0000655
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700656#if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME
Dan Handley9df48042015-03-19 18:58:55 +0000657/*******************************************************************************
Soby Mathewbf169232017-11-14 14:10:10 +0000658 * BL32 specific defines for EL3 runtime in AArch32 mode
659 ******************************************************************************/
660# if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME
Manish Pandey928da862021-06-10 15:22:48 +0100661/* Ensure Position Independent support (PIE) is enabled for this config.*/
662# if !ENABLE_PIE
663# error "BL32 must be a PIE if RESET_TO_SP_MIN=1."
664#endif
Soby Mathewaf14b462018-06-01 16:53:38 +0100665/*
Manish Pandey928da862021-06-10 15:22:48 +0100666 * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely
667 * used for building BL32 and not used for loading BL32.
Soby Mathewaf14b462018-06-01 16:53:38 +0100668 */
Manish Pandey928da862021-06-10 15:22:48 +0100669# define BL32_BASE 0x0
670# define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE
Soby Mathewbf169232017-11-14 14:10:10 +0000671# else
Soby Mathewaf14b462018-06-01 16:53:38 +0100672/* Put BL32 below BL2 in the Trusted SRAM.*/
673# define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\
674 - PLAT_ARM_MAX_BL32_SIZE)
675# define BL32_PROGBITS_LIMIT BL2_BASE
Soby Mathewbf169232017-11-14 14:10:10 +0000676# define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
677# endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */
678
679#else
680/*******************************************************************************
681 * BL32 specific defines for EL3 runtime in AArch64 mode
Dan Handley9df48042015-03-19 18:58:55 +0000682 ******************************************************************************/
683/*
684 * On ARM standard platforms, the TSP can execute from Trusted SRAM,
685 * Trusted DRAM (if available) or the DRAM region secured by the TrustZone
686 * controller.
687 */
Marc Bonnicif5867002021-12-20 10:53:52 +0000688# if SPM_MM || SPMC_AT_EL3
Soby Mathewbf169232017-11-14 14:10:10 +0000689# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
690# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000))
691# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
692# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000693 ARM_AP_TZC_DRAM1_SIZE)
Achin Guptae97351d2019-10-11 15:15:19 +0100694# elif defined(SPD_spmd)
695# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
696# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000))
Arunachalam Ganapathy40618cf2020-07-27 13:51:30 +0100697# define BL32_BASE PLAT_ARM_SPMC_BASE
698# define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \
699 PLAT_ARM_SPMC_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000700# elif ARM_BL31_IN_DRAM
701# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \
David Wang0ba499f2016-03-07 11:02:57 +0800702 PLAT_ARM_MAX_BL31_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000703# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \
David Wang0ba499f2016-03-07 11:02:57 +0800704 PLAT_ARM_MAX_BL31_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000705# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \
David Wang0ba499f2016-03-07 11:02:57 +0800706 PLAT_ARM_MAX_BL31_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000707# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
David Wang0ba499f2016-03-07 11:02:57 +0800708 ARM_AP_TZC_DRAM1_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000709# elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID
710# define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE
711# define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE
Soby Mathewaf14b462018-06-01 16:53:38 +0100712# define TSP_PROGBITS_LIMIT BL31_BASE
Manish V Badarkhe1da211a2020-05-31 10:17:59 +0100713# define BL32_BASE ARM_FW_CONFIGS_LIMIT
Soby Mathewbf169232017-11-14 14:10:10 +0000714# define BL32_LIMIT BL31_BASE
715# elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID
716# define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE
717# define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE
718# define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE
719# define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \
Manish V Badarkhe5a4f9b82023-04-30 09:25:15 +0100720 + SZ_4M)
Soby Mathewbf169232017-11-14 14:10:10 +0000721# elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID
722# define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE
723# define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE
724# define BL32_BASE ARM_AP_TZC_DRAM1_BASE
725# define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
Dan Handley9df48042015-03-19 18:58:55 +0000726 ARM_AP_TZC_DRAM1_SIZE)
Soby Mathewbf169232017-11-14 14:10:10 +0000727# else
728# error "Unsupported ARM_TSP_RAM_LOCATION_ID value"
729# endif
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700730#endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */
Dan Handley9df48042015-03-19 18:58:55 +0000731
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000732/*
733 * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no
Marc Bonnicif5867002021-12-20 10:53:52 +0000734 * SPD and no SPM-MM and no SPMC-AT-EL3, as they are the only ones that can be
735 * used as BL32.
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000736 */
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700737#if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME
Marc Bonnicif5867002021-12-20 10:53:52 +0000738# if defined(SPD_none) && !SPM_MM && !SPMC_AT_EL3
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000739# undef BL32_BASE
Marc Bonnicif5867002021-12-20 10:53:52 +0000740# endif /* defined(SPD_none) && !SPM_MM || !SPMC_AT_EL3 */
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700741#endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */
Antonio Nino Diaze4fa3702016-04-05 11:38:49 +0100742
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100743/*******************************************************************************
744 * FWU Images: NS_BL1U, BL2U & NS_BL2U defines.
745 ******************************************************************************/
746#define BL2U_BASE BL2_BASE
Soby Mathewbf169232017-11-14 14:10:10 +0000747#define BL2U_LIMIT BL2_LIMIT
748
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100749#define NS_BL2U_BASE ARM_NS_DRAM1_BASE
Antonio Nino Diazab5d2b12018-10-30 16:12:32 +0000750#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000))
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100751
Dan Handley9df48042015-03-19 18:58:55 +0000752/*
753 * ID of the secure physical generic timer interrupt used by the TSP.
754 */
755#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
756
757
Vikram Kanigirid79214c2015-09-09 10:52:13 +0100758/*
759 * One cache line needed for bakery locks on ARM platforms
760 */
761#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
762
Jeenu Viswambharanb1837452017-10-24 11:47:13 +0100763/* Priority levels for ARM platforms */
Manish Pandeyf90a73c2023-10-10 15:42:19 +0100764#if ENABLE_FEAT_RAS && FFH_SUPPORT
Jeenu Viswambharana5b5b8d2018-02-06 12:21:39 +0000765#define PLAT_RAS_PRI 0x10
Omkar Anand Kulkarni014ae052023-06-22 19:35:59 +0530766#endif
Jeenu Viswambharanb1837452017-10-24 11:47:13 +0100767#define PLAT_SDEI_CRITICAL_PRI 0x60
768#define PLAT_SDEI_NORMAL_PRI 0x70
769
Omkar Anand Kulkarnibc204322023-07-21 14:29:49 +0530770/* CPU Fault Handling Interrupt(FHI) PPI interrupt ID */
771#define PLAT_CORE_FAULT_IRQ 17
772
Jeenu Viswambharanb1837452017-10-24 11:47:13 +0100773/* ARM platforms use 3 upper bits of secure interrupt priority */
Sandeep Tripathy1c478392020-08-12 18:42:13 +0530774#define PLAT_PRI_BITS 3
Vikram Kanigirid79214c2015-09-09 10:52:13 +0100775
Jeenu Viswambharana5acc0a2017-09-22 08:32:10 +0100776/* SGI used for SDEI signalling */
777#define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0
778
Balint Dobszayd0dbd5e2019-12-18 15:28:00 +0100779#if SDEI_IN_FCONF
780/* ARM SDEI dynamic private event max count */
781#define ARM_SDEI_DP_EVENT_MAX_CNT 3
782
783/* ARM SDEI dynamic shared event max count */
784#define ARM_SDEI_DS_EVENT_MAX_CNT 3
785#else
Jeenu Viswambharana5acc0a2017-09-22 08:32:10 +0100786/* ARM SDEI dynamic private event numbers */
787#define ARM_SDEI_DP_EVENT_0 1000
788#define ARM_SDEI_DP_EVENT_1 1001
789#define ARM_SDEI_DP_EVENT_2 1002
790
791/* ARM SDEI dynamic shared event numbers */
792#define ARM_SDEI_DS_EVENT_0 2000
793#define ARM_SDEI_DS_EVENT_1 2001
794#define ARM_SDEI_DS_EVENT_2 2002
795
Jeenu Viswambharan6e284462017-12-08 10:38:24 +0000796#define ARM_SDEI_PRIVATE_EVENTS \
797 SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \
798 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
799 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
800 SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
801
802#define ARM_SDEI_SHARED_EVENTS \
803 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
804 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
805 SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
Balint Dobszayd0dbd5e2019-12-18 15:28:00 +0100806#endif /* SDEI_IN_FCONF */
Jeenu Viswambharan6e284462017-12-08 10:38:24 +0000807
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100808#endif /* ARM_DEF_H */