Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __CONTEXT_H__ |
| 32 | #define __CONTEXT_H__ |
| 33 | |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 34 | /******************************************************************************* |
Achin Gupta | 07f4e07 | 2014-02-02 12:02:23 +0000 | [diff] [blame] | 35 | * Constants that allow assembler code to access members of and the 'gp_regs' |
| 36 | * structure at their correct offsets. |
| 37 | ******************************************************************************/ |
| 38 | #define CTX_GPREGS_OFFSET 0x0 |
| 39 | #define CTX_GPREG_X0 0x0 |
| 40 | #define CTX_GPREG_X1 0x8 |
| 41 | #define CTX_GPREG_X2 0x10 |
| 42 | #define CTX_GPREG_X3 0x18 |
| 43 | #define CTX_GPREG_X4 0x20 |
| 44 | #define CTX_GPREG_X5 0x28 |
| 45 | #define CTX_GPREG_X6 0x30 |
| 46 | #define CTX_GPREG_X7 0x38 |
| 47 | #define CTX_GPREG_X8 0x40 |
| 48 | #define CTX_GPREG_X9 0x48 |
| 49 | #define CTX_GPREG_X10 0x50 |
| 50 | #define CTX_GPREG_X11 0x58 |
| 51 | #define CTX_GPREG_X12 0x60 |
| 52 | #define CTX_GPREG_X13 0x68 |
| 53 | #define CTX_GPREG_X14 0x70 |
| 54 | #define CTX_GPREG_X15 0x78 |
| 55 | #define CTX_GPREG_X16 0x80 |
| 56 | #define CTX_GPREG_X17 0x88 |
| 57 | #define CTX_GPREG_X18 0x90 |
Soby Mathew | 6c5192a | 2014-04-30 15:36:37 +0100 | [diff] [blame] | 58 | #define CTX_GPREG_X19 0x98 |
| 59 | #define CTX_GPREG_X20 0xa0 |
| 60 | #define CTX_GPREG_X21 0xa8 |
| 61 | #define CTX_GPREG_X22 0xb0 |
| 62 | #define CTX_GPREG_X23 0xb8 |
| 63 | #define CTX_GPREG_X24 0xc0 |
| 64 | #define CTX_GPREG_X25 0xc8 |
| 65 | #define CTX_GPREG_X26 0xd0 |
| 66 | #define CTX_GPREG_X27 0xd8 |
| 67 | #define CTX_GPREG_X28 0xe0 |
| 68 | #define CTX_GPREG_X29 0xe8 |
| 69 | #define CTX_GPREG_LR 0xf0 |
| 70 | #define CTX_GPREG_SP_EL0 0xf8 |
| 71 | #define CTX_GPREGS_END 0x100 |
Achin Gupta | 07f4e07 | 2014-02-02 12:02:23 +0000 | [diff] [blame] | 72 | |
| 73 | /******************************************************************************* |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 74 | * Constants that allow assembler code to access members of and the 'el3_state' |
| 75 | * structure at their correct offsets. Note that some of the registers are only |
| 76 | * 32-bits wide but are stored as 64-bit values for convenience |
| 77 | ******************************************************************************/ |
Achin Gupta | 07f4e07 | 2014-02-02 12:02:23 +0000 | [diff] [blame] | 78 | #define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END) |
| 79 | #define CTX_EXCEPTION_SP 0x0 |
| 80 | #define CTX_RUNTIME_SP 0x8 |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 81 | #define CTX_SPSR_EL3 0x10 |
| 82 | #define CTX_ELR_EL3 0x18 |
| 83 | #define CTX_SCR_EL3 0x20 |
| 84 | #define CTX_SCTLR_EL3 0x28 |
| 85 | #define CTX_CPTR_EL3 0x30 |
| 86 | /* Unused space to allow registers to be stored as pairs */ |
| 87 | #define CTX_CNTFRQ_EL0 0x40 |
| 88 | #define CTX_MAIR_EL3 0x48 |
| 89 | #define CTX_TCR_EL3 0x50 |
| 90 | #define CTX_TTBR0_EL3 0x58 |
| 91 | #define CTX_DAIF_EL3 0x60 |
| 92 | #define CTX_VBAR_EL3 0x68 /* Currently unused */ |
| 93 | #define CTX_EL3STATE_END 0x70 |
| 94 | |
| 95 | /******************************************************************************* |
| 96 | * Constants that allow assembler code to access members of and the |
| 97 | * 'el1_sys_regs' structure at their correct offsets. Note that some of the |
| 98 | * registers are only 32-bits wide but are stored as 64-bit values for |
| 99 | * convenience |
| 100 | ******************************************************************************/ |
| 101 | #define CTX_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END) |
| 102 | #define CTX_SPSR_EL1 0x0 |
| 103 | #define CTX_ELR_EL1 0x8 |
| 104 | #define CTX_SPSR_ABT 0x10 |
| 105 | #define CTX_SPSR_UND 0x18 |
| 106 | #define CTX_SPSR_IRQ 0x20 |
| 107 | #define CTX_SPSR_FIQ 0x28 |
| 108 | #define CTX_SCTLR_EL1 0x30 |
| 109 | #define CTX_ACTLR_EL1 0x38 |
| 110 | #define CTX_CPACR_EL1 0x40 |
| 111 | #define CTX_CSSELR_EL1 0x48 |
| 112 | #define CTX_SP_EL1 0x50 |
| 113 | #define CTX_ESR_EL1 0x58 |
| 114 | #define CTX_TTBR0_EL1 0x60 |
| 115 | #define CTX_TTBR1_EL1 0x68 |
| 116 | #define CTX_MAIR_EL1 0x70 |
| 117 | #define CTX_AMAIR_EL1 0x78 |
| 118 | #define CTX_TCR_EL1 0x80 |
| 119 | #define CTX_TPIDR_EL1 0x88 |
| 120 | #define CTX_TPIDR_EL0 0x90 |
| 121 | #define CTX_TPIDRRO_EL0 0x98 |
| 122 | #define CTX_DACR32_EL2 0xa0 |
| 123 | #define CTX_IFSR32_EL2 0xa8 |
| 124 | #define CTX_PAR_EL1 0xb0 |
| 125 | #define CTX_FAR_EL1 0xb8 |
| 126 | #define CTX_AFSR0_EL1 0xc0 |
| 127 | #define CTX_AFSR1_EL1 0xc8 |
| 128 | #define CTX_CONTEXTIDR_EL1 0xd0 |
| 129 | #define CTX_VBAR_EL1 0xd8 |
| 130 | #define CTX_CNTP_CTL_EL0 0xe0 |
| 131 | #define CTX_CNTP_CVAL_EL0 0xe8 |
| 132 | #define CTX_CNTV_CTL_EL0 0xf0 |
| 133 | #define CTX_CNTV_CVAL_EL0 0xf8 |
| 134 | #define CTX_CNTKCTL_EL1 0x100 |
| 135 | #define CTX_FP_FPEXC32_EL2 0x108 |
| 136 | #define CTX_SYSREGS_END 0x110 |
| 137 | |
| 138 | /******************************************************************************* |
| 139 | * Constants that allow assembler code to access members of and the 'fp_regs' |
| 140 | * structure at their correct offsets. |
| 141 | ******************************************************************************/ |
| 142 | #define CTX_FPREGS_OFFSET (CTX_SYSREGS_OFFSET + CTX_SYSREGS_END) |
| 143 | #define CTX_FP_Q0 0x0 |
| 144 | #define CTX_FP_Q1 0x10 |
| 145 | #define CTX_FP_Q2 0x20 |
| 146 | #define CTX_FP_Q3 0x30 |
| 147 | #define CTX_FP_Q4 0x40 |
| 148 | #define CTX_FP_Q5 0x50 |
| 149 | #define CTX_FP_Q6 0x60 |
| 150 | #define CTX_FP_Q7 0x70 |
| 151 | #define CTX_FP_Q8 0x80 |
| 152 | #define CTX_FP_Q9 0x90 |
| 153 | #define CTX_FP_Q10 0xa0 |
| 154 | #define CTX_FP_Q11 0xb0 |
| 155 | #define CTX_FP_Q12 0xc0 |
| 156 | #define CTX_FP_Q13 0xd0 |
| 157 | #define CTX_FP_Q14 0xe0 |
| 158 | #define CTX_FP_Q15 0xf0 |
| 159 | #define CTX_FP_Q16 0x100 |
| 160 | #define CTX_FP_Q17 0x110 |
| 161 | #define CTX_FP_Q18 0x120 |
| 162 | #define CTX_FP_Q19 0x130 |
| 163 | #define CTX_FP_Q20 0x140 |
| 164 | #define CTX_FP_Q21 0x150 |
| 165 | #define CTX_FP_Q22 0x160 |
| 166 | #define CTX_FP_Q23 0x170 |
| 167 | #define CTX_FP_Q24 0x180 |
| 168 | #define CTX_FP_Q25 0x190 |
| 169 | #define CTX_FP_Q26 0x1a0 |
| 170 | #define CTX_FP_Q27 0x1b0 |
| 171 | #define CTX_FP_Q28 0x1c0 |
| 172 | #define CTX_FP_Q29 0x1d0 |
| 173 | #define CTX_FP_Q30 0x1e0 |
| 174 | #define CTX_FP_Q31 0x1f0 |
| 175 | #define CTX_FP_FPSR 0x200 |
| 176 | #define CTX_FP_FPCR 0x208 |
| 177 | #define CTX_FPREGS_END 0x210 |
| 178 | |
| 179 | #ifndef __ASSEMBLY__ |
| 180 | |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 181 | #include <cassert.h> |
| 182 | #include <stdint.h> |
| 183 | |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 184 | /* |
| 185 | * Common constants to help define the 'cpu_context' structure and its |
| 186 | * members below. |
| 187 | */ |
| 188 | #define DWORD_SHIFT 3 |
| 189 | #define DEFINE_REG_STRUCT(name, num_regs) \ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 190 | typedef struct name { \ |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 191 | uint64_t _regs[num_regs]; \ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 192 | } __aligned(16) name##_t |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 193 | |
| 194 | /* Constants to determine the size of individual context structures */ |
Achin Gupta | 07f4e07 | 2014-02-02 12:02:23 +0000 | [diff] [blame] | 195 | #define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT) |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 196 | #define CTX_SYSREG_ALL (CTX_SYSREGS_END >> DWORD_SHIFT) |
| 197 | #define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT) |
| 198 | #define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT) |
| 199 | |
| 200 | /* |
Soby Mathew | 6c5192a | 2014-04-30 15:36:37 +0100 | [diff] [blame] | 201 | * AArch64 general purpose register context structure. Usually x0-x18, |
| 202 | * lr are saved as the compiler is expected to preserve the remaining |
Achin Gupta | 07f4e07 | 2014-02-02 12:02:23 +0000 | [diff] [blame] | 203 | * callee saved registers if used by the C runtime and the assembler |
Soby Mathew | 6c5192a | 2014-04-30 15:36:37 +0100 | [diff] [blame] | 204 | * does not touch the remaining. But in case of world switch during |
| 205 | * exception handling, we need to save the callee registers too. |
Achin Gupta | 07f4e07 | 2014-02-02 12:02:23 +0000 | [diff] [blame] | 206 | */ |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 207 | DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL); |
Achin Gupta | 07f4e07 | 2014-02-02 12:02:23 +0000 | [diff] [blame] | 208 | |
| 209 | /* |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 210 | * AArch64 EL1 system register context structure for preserving the |
| 211 | * architectural state during switches from one security state to |
| 212 | * another in EL1. |
| 213 | */ |
| 214 | DEFINE_REG_STRUCT(el1_sys_regs, CTX_SYSREG_ALL); |
| 215 | |
| 216 | /* |
| 217 | * AArch64 floating point register context structure for preserving |
| 218 | * the floating point state during switches from one security state to |
| 219 | * another. |
| 220 | */ |
| 221 | DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL); |
| 222 | |
| 223 | /* |
| 224 | * Miscellaneous registers used by EL3 firmware to maintain its state |
| 225 | * across exception entries and exits |
| 226 | */ |
| 227 | DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL); |
| 228 | |
| 229 | /* |
| 230 | * Macros to access members of any of the above structures using their |
| 231 | * offsets |
| 232 | */ |
| 233 | #define read_ctx_reg(ctx, offset) ((ctx)->_regs[offset >> DWORD_SHIFT]) |
| 234 | #define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[offset >> DWORD_SHIFT]) \ |
| 235 | = val) |
| 236 | |
| 237 | /* |
| 238 | * Top-level context structure which is used by EL3 firmware to |
| 239 | * preserve the state of a core at EL1 in one of the two security |
| 240 | * states and save enough EL3 meta data to be able to return to that |
| 241 | * EL and security state. The context management library will be used |
| 242 | * to ensure that SP_EL3 always points to an instance of this |
| 243 | * structure at exception entry and exit. Each instance will |
| 244 | * correspond to either the secure or the non-secure state. |
| 245 | */ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 246 | typedef struct cpu_context { |
| 247 | gp_regs_t gpregs_ctx; |
| 248 | el3_state_t el3state_ctx; |
| 249 | el1_sys_regs_t sysregs_ctx; |
| 250 | fp_regs_t fpregs_ctx; |
| 251 | } cpu_context_t; |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 252 | |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 253 | /* Macros to access members of the 'cpu_context_t' structure */ |
| 254 | #define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx) |
| 255 | #define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx) |
| 256 | #define get_sysregs_ctx(h) (&((cpu_context_t *) h)->sysregs_ctx) |
| 257 | #define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx) |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 258 | |
| 259 | /* |
| 260 | * Compile time assertions related to the 'cpu_context' structure to |
| 261 | * ensure that the assembler and the compiler view of the offsets of |
| 262 | * the structure members is the same. |
| 263 | */ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 264 | CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \ |
Achin Gupta | 07f4e07 | 2014-02-02 12:02:23 +0000 | [diff] [blame] | 265 | assert_core_context_gp_offset_mismatch); |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 266 | CASSERT(CTX_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, sysregs_ctx), \ |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 267 | assert_core_context_sys_offset_mismatch); |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 268 | CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), \ |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 269 | assert_core_context_fp_offset_mismatch); |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 270 | CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), \ |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 271 | assert_core_context_el3state_offset_mismatch); |
| 272 | |
Achin Gupta | 607084e | 2014-02-09 18:24:19 +0000 | [diff] [blame] | 273 | /* |
| 274 | * Helper macro to set the general purpose registers that correspond to |
| 275 | * parameters in an aapcs_64 call i.e. x0-x7 |
| 276 | */ |
| 277 | #define set_aapcs_args0(ctx, x0) do { \ |
| 278 | write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \ |
| 279 | } while (0); |
| 280 | #define set_aapcs_args1(ctx, x0, x1) do { \ |
| 281 | write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \ |
| 282 | set_aapcs_args0(ctx, x0); \ |
| 283 | } while (0); |
| 284 | #define set_aapcs_args2(ctx, x0, x1, x2) do { \ |
| 285 | write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \ |
| 286 | set_aapcs_args1(ctx, x0, x1); \ |
| 287 | } while (0); |
| 288 | #define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \ |
| 289 | write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \ |
| 290 | set_aapcs_args2(ctx, x0, x1, x2); \ |
| 291 | } while (0); |
| 292 | #define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \ |
| 293 | write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \ |
| 294 | set_aapcs_args3(ctx, x0, x1, x2, x3); \ |
| 295 | } while (0); |
| 296 | #define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \ |
| 297 | write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \ |
| 298 | set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \ |
| 299 | } while (0); |
| 300 | #define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \ |
| 301 | write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \ |
| 302 | set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \ |
| 303 | } while (0); |
| 304 | #define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \ |
| 305 | write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \ |
| 306 | set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \ |
| 307 | } while (0); |
| 308 | |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 309 | /******************************************************************************* |
| 310 | * Function prototypes |
| 311 | ******************************************************************************/ |
Dan Handley | e2712bc | 2014-04-10 15:37:22 +0100 | [diff] [blame] | 312 | void el3_sysregs_context_save(el3_state_t *regs); |
| 313 | void el3_sysregs_context_restore(el3_state_t *regs); |
| 314 | void el1_sysregs_context_save(el1_sys_regs_t *regs); |
| 315 | void el1_sysregs_context_restore(el1_sys_regs_t *regs); |
| 316 | void fpregs_context_save(fp_regs_t *regs); |
| 317 | void fpregs_context_restore(fp_regs_t *regs); |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 318 | |
| 319 | #undef CTX_SYSREG_ALL |
| 320 | #undef CTX_FP_ALL |
Achin Gupta | 07f4e07 | 2014-02-02 12:02:23 +0000 | [diff] [blame] | 321 | #undef CTX_GPREG_ALL |
Achin Gupta | 9ac63c5 | 2014-01-16 12:08:03 +0000 | [diff] [blame] | 322 | #undef CTX_EL3STATE_ALL |
| 323 | |
| 324 | #endif /* __ASSEMBLY__ */ |
| 325 | |
| 326 | #endif /* __CONTEXT_H__ */ |