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Achin Gupta9ac63c52014-01-16 12:08:03 +00001/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __CONTEXT_H__
32#define __CONTEXT_H__
33
Achin Gupta9ac63c52014-01-16 12:08:03 +000034/*******************************************************************************
Achin Gupta07f4e072014-02-02 12:02:23 +000035 * Constants that allow assembler code to access members of and the 'gp_regs'
36 * structure at their correct offsets.
37 ******************************************************************************/
38#define CTX_GPREGS_OFFSET 0x0
39#define CTX_GPREG_X0 0x0
40#define CTX_GPREG_X1 0x8
41#define CTX_GPREG_X2 0x10
42#define CTX_GPREG_X3 0x18
43#define CTX_GPREG_X4 0x20
44#define CTX_GPREG_X5 0x28
45#define CTX_GPREG_X6 0x30
46#define CTX_GPREG_X7 0x38
47#define CTX_GPREG_X8 0x40
48#define CTX_GPREG_X9 0x48
49#define CTX_GPREG_X10 0x50
50#define CTX_GPREG_X11 0x58
51#define CTX_GPREG_X12 0x60
52#define CTX_GPREG_X13 0x68
53#define CTX_GPREG_X14 0x70
54#define CTX_GPREG_X15 0x78
55#define CTX_GPREG_X16 0x80
56#define CTX_GPREG_X17 0x88
57#define CTX_GPREG_X18 0x90
Soby Mathew6c5192a2014-04-30 15:36:37 +010058#define CTX_GPREG_X19 0x98
59#define CTX_GPREG_X20 0xa0
60#define CTX_GPREG_X21 0xa8
61#define CTX_GPREG_X22 0xb0
62#define CTX_GPREG_X23 0xb8
63#define CTX_GPREG_X24 0xc0
64#define CTX_GPREG_X25 0xc8
65#define CTX_GPREG_X26 0xd0
66#define CTX_GPREG_X27 0xd8
67#define CTX_GPREG_X28 0xe0
68#define CTX_GPREG_X29 0xe8
69#define CTX_GPREG_LR 0xf0
70#define CTX_GPREG_SP_EL0 0xf8
71#define CTX_GPREGS_END 0x100
Achin Gupta07f4e072014-02-02 12:02:23 +000072
73/*******************************************************************************
Achin Gupta9ac63c52014-01-16 12:08:03 +000074 * Constants that allow assembler code to access members of and the 'el3_state'
75 * structure at their correct offsets. Note that some of the registers are only
76 * 32-bits wide but are stored as 64-bit values for convenience
77 ******************************************************************************/
Achin Gupta07f4e072014-02-02 12:02:23 +000078#define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END)
Soby Mathew5e5c2072014-04-07 15:28:55 +010079#define CTX_VBAR_EL3 0x0 /* Currently unused */
Achin Gupta07f4e072014-02-02 12:02:23 +000080#define CTX_RUNTIME_SP 0x8
Achin Gupta9ac63c52014-01-16 12:08:03 +000081#define CTX_SPSR_EL3 0x10
82#define CTX_ELR_EL3 0x18
83#define CTX_SCR_EL3 0x20
84#define CTX_SCTLR_EL3 0x28
85#define CTX_CPTR_EL3 0x30
86/* Unused space to allow registers to be stored as pairs */
87#define CTX_CNTFRQ_EL0 0x40
88#define CTX_MAIR_EL3 0x48
89#define CTX_TCR_EL3 0x50
90#define CTX_TTBR0_EL3 0x58
91#define CTX_DAIF_EL3 0x60
Soby Mathew5e5c2072014-04-07 15:28:55 +010092/* Unused space to honour alignment requirements */
Achin Gupta9ac63c52014-01-16 12:08:03 +000093#define CTX_EL3STATE_END 0x70
94
95/*******************************************************************************
96 * Constants that allow assembler code to access members of and the
97 * 'el1_sys_regs' structure at their correct offsets. Note that some of the
98 * registers are only 32-bits wide but are stored as 64-bit values for
99 * convenience
100 ******************************************************************************/
101#define CTX_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END)
102#define CTX_SPSR_EL1 0x0
103#define CTX_ELR_EL1 0x8
104#define CTX_SPSR_ABT 0x10
105#define CTX_SPSR_UND 0x18
106#define CTX_SPSR_IRQ 0x20
107#define CTX_SPSR_FIQ 0x28
108#define CTX_SCTLR_EL1 0x30
109#define CTX_ACTLR_EL1 0x38
110#define CTX_CPACR_EL1 0x40
111#define CTX_CSSELR_EL1 0x48
112#define CTX_SP_EL1 0x50
113#define CTX_ESR_EL1 0x58
114#define CTX_TTBR0_EL1 0x60
115#define CTX_TTBR1_EL1 0x68
116#define CTX_MAIR_EL1 0x70
117#define CTX_AMAIR_EL1 0x78
118#define CTX_TCR_EL1 0x80
119#define CTX_TPIDR_EL1 0x88
120#define CTX_TPIDR_EL0 0x90
121#define CTX_TPIDRRO_EL0 0x98
122#define CTX_DACR32_EL2 0xa0
123#define CTX_IFSR32_EL2 0xa8
124#define CTX_PAR_EL1 0xb0
125#define CTX_FAR_EL1 0xb8
126#define CTX_AFSR0_EL1 0xc0
127#define CTX_AFSR1_EL1 0xc8
128#define CTX_CONTEXTIDR_EL1 0xd0
129#define CTX_VBAR_EL1 0xd8
Jeenu Viswambharand1b60152014-05-12 15:28:47 +0100130/*
131 * If the timer registers aren't saved and restored, we don't have to reserve
132 * space for them in the context
133 */
134#if NS_TIMER_SWITCH
Achin Gupta9ac63c52014-01-16 12:08:03 +0000135#define CTX_CNTP_CTL_EL0 0xe0
136#define CTX_CNTP_CVAL_EL0 0xe8
137#define CTX_CNTV_CTL_EL0 0xf0
138#define CTX_CNTV_CVAL_EL0 0xf8
139#define CTX_CNTKCTL_EL1 0x100
140#define CTX_FP_FPEXC32_EL2 0x108
141#define CTX_SYSREGS_END 0x110
Jeenu Viswambharand1b60152014-05-12 15:28:47 +0100142#else
143#define CTX_FP_FPEXC32_EL2 0xe0
144#define CTX_SYSREGS_END 0xf0
145#endif
Achin Gupta9ac63c52014-01-16 12:08:03 +0000146
147/*******************************************************************************
148 * Constants that allow assembler code to access members of and the 'fp_regs'
149 * structure at their correct offsets.
150 ******************************************************************************/
151#define CTX_FPREGS_OFFSET (CTX_SYSREGS_OFFSET + CTX_SYSREGS_END)
152#define CTX_FP_Q0 0x0
153#define CTX_FP_Q1 0x10
154#define CTX_FP_Q2 0x20
155#define CTX_FP_Q3 0x30
156#define CTX_FP_Q4 0x40
157#define CTX_FP_Q5 0x50
158#define CTX_FP_Q6 0x60
159#define CTX_FP_Q7 0x70
160#define CTX_FP_Q8 0x80
161#define CTX_FP_Q9 0x90
162#define CTX_FP_Q10 0xa0
163#define CTX_FP_Q11 0xb0
164#define CTX_FP_Q12 0xc0
165#define CTX_FP_Q13 0xd0
166#define CTX_FP_Q14 0xe0
167#define CTX_FP_Q15 0xf0
168#define CTX_FP_Q16 0x100
169#define CTX_FP_Q17 0x110
170#define CTX_FP_Q18 0x120
171#define CTX_FP_Q19 0x130
172#define CTX_FP_Q20 0x140
173#define CTX_FP_Q21 0x150
174#define CTX_FP_Q22 0x160
175#define CTX_FP_Q23 0x170
176#define CTX_FP_Q24 0x180
177#define CTX_FP_Q25 0x190
178#define CTX_FP_Q26 0x1a0
179#define CTX_FP_Q27 0x1b0
180#define CTX_FP_Q28 0x1c0
181#define CTX_FP_Q29 0x1d0
182#define CTX_FP_Q30 0x1e0
183#define CTX_FP_Q31 0x1f0
184#define CTX_FP_FPSR 0x200
185#define CTX_FP_FPCR 0x208
186#define CTX_FPREGS_END 0x210
187
Soby Mathew5e5c2072014-04-07 15:28:55 +0100188/******************************************************************************
189 * Offsets for the per cpu cache implementation
190 ******************************************************************************/
191#define PTR_CACHE_CRASH_STACK_OFFSET 0x0
192
Achin Gupta9ac63c52014-01-16 12:08:03 +0000193#ifndef __ASSEMBLY__
194
Dan Handley2bd4ef22014-04-09 13:14:54 +0100195#include <cassert.h>
196#include <stdint.h>
197
Achin Gupta9ac63c52014-01-16 12:08:03 +0000198/*
199 * Common constants to help define the 'cpu_context' structure and its
200 * members below.
201 */
202#define DWORD_SHIFT 3
203#define DEFINE_REG_STRUCT(name, num_regs) \
Dan Handleye2712bc2014-04-10 15:37:22 +0100204 typedef struct name { \
Achin Gupta9ac63c52014-01-16 12:08:03 +0000205 uint64_t _regs[num_regs]; \
Dan Handleye2712bc2014-04-10 15:37:22 +0100206 } __aligned(16) name##_t
Achin Gupta9ac63c52014-01-16 12:08:03 +0000207
208/* Constants to determine the size of individual context structures */
Achin Gupta07f4e072014-02-02 12:02:23 +0000209#define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT)
Achin Gupta9ac63c52014-01-16 12:08:03 +0000210#define CTX_SYSREG_ALL (CTX_SYSREGS_END >> DWORD_SHIFT)
211#define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT)
212#define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT)
213
214/*
Soby Mathew6c5192a2014-04-30 15:36:37 +0100215 * AArch64 general purpose register context structure. Usually x0-x18,
216 * lr are saved as the compiler is expected to preserve the remaining
Achin Gupta07f4e072014-02-02 12:02:23 +0000217 * callee saved registers if used by the C runtime and the assembler
Soby Mathew6c5192a2014-04-30 15:36:37 +0100218 * does not touch the remaining. But in case of world switch during
219 * exception handling, we need to save the callee registers too.
Achin Gupta07f4e072014-02-02 12:02:23 +0000220 */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000221DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL);
Achin Gupta07f4e072014-02-02 12:02:23 +0000222
223/*
Achin Gupta9ac63c52014-01-16 12:08:03 +0000224 * AArch64 EL1 system register context structure for preserving the
225 * architectural state during switches from one security state to
226 * another in EL1.
227 */
228DEFINE_REG_STRUCT(el1_sys_regs, CTX_SYSREG_ALL);
229
230/*
231 * AArch64 floating point register context structure for preserving
232 * the floating point state during switches from one security state to
233 * another.
234 */
235DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL);
236
237/*
238 * Miscellaneous registers used by EL3 firmware to maintain its state
239 * across exception entries and exits
240 */
241DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL);
242
243/*
244 * Macros to access members of any of the above structures using their
245 * offsets
246 */
247#define read_ctx_reg(ctx, offset) ((ctx)->_regs[offset >> DWORD_SHIFT])
248#define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[offset >> DWORD_SHIFT]) \
249 = val)
250
251/*
252 * Top-level context structure which is used by EL3 firmware to
253 * preserve the state of a core at EL1 in one of the two security
254 * states and save enough EL3 meta data to be able to return to that
255 * EL and security state. The context management library will be used
256 * to ensure that SP_EL3 always points to an instance of this
257 * structure at exception entry and exit. Each instance will
258 * correspond to either the secure or the non-secure state.
259 */
Dan Handleye2712bc2014-04-10 15:37:22 +0100260typedef struct cpu_context {
261 gp_regs_t gpregs_ctx;
262 el3_state_t el3state_ctx;
263 el1_sys_regs_t sysregs_ctx;
264 fp_regs_t fpregs_ctx;
265} cpu_context_t;
Achin Gupta9ac63c52014-01-16 12:08:03 +0000266
Dan Handleye2712bc2014-04-10 15:37:22 +0100267/* Macros to access members of the 'cpu_context_t' structure */
268#define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx)
269#define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx)
270#define get_sysregs_ctx(h) (&((cpu_context_t *) h)->sysregs_ctx)
271#define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx)
Achin Gupta9ac63c52014-01-16 12:08:03 +0000272
273/*
274 * Compile time assertions related to the 'cpu_context' structure to
275 * ensure that the assembler and the compiler view of the offsets of
276 * the structure members is the same.
277 */
Dan Handleye2712bc2014-04-10 15:37:22 +0100278CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \
Achin Gupta07f4e072014-02-02 12:02:23 +0000279 assert_core_context_gp_offset_mismatch);
Dan Handleye2712bc2014-04-10 15:37:22 +0100280CASSERT(CTX_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, sysregs_ctx), \
Achin Gupta9ac63c52014-01-16 12:08:03 +0000281 assert_core_context_sys_offset_mismatch);
Dan Handleye2712bc2014-04-10 15:37:22 +0100282CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), \
Achin Gupta9ac63c52014-01-16 12:08:03 +0000283 assert_core_context_fp_offset_mismatch);
Dan Handleye2712bc2014-04-10 15:37:22 +0100284CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), \
Achin Gupta9ac63c52014-01-16 12:08:03 +0000285 assert_core_context_el3state_offset_mismatch);
286
Achin Gupta607084e2014-02-09 18:24:19 +0000287/*
288 * Helper macro to set the general purpose registers that correspond to
289 * parameters in an aapcs_64 call i.e. x0-x7
290 */
291#define set_aapcs_args0(ctx, x0) do { \
292 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \
293 } while (0);
294#define set_aapcs_args1(ctx, x0, x1) do { \
295 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \
296 set_aapcs_args0(ctx, x0); \
297 } while (0);
298#define set_aapcs_args2(ctx, x0, x1, x2) do { \
299 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \
300 set_aapcs_args1(ctx, x0, x1); \
301 } while (0);
302#define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \
303 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \
304 set_aapcs_args2(ctx, x0, x1, x2); \
305 } while (0);
306#define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \
307 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \
308 set_aapcs_args3(ctx, x0, x1, x2, x3); \
309 } while (0);
310#define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \
311 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \
312 set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \
313 } while (0);
314#define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \
315 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \
316 set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \
317 } while (0);
318#define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \
319 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \
320 set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \
321 } while (0);
322
Achin Gupta9ac63c52014-01-16 12:08:03 +0000323/*******************************************************************************
324 * Function prototypes
325 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +0100326void el3_sysregs_context_save(el3_state_t *regs);
327void el3_sysregs_context_restore(el3_state_t *regs);
328void el1_sysregs_context_save(el1_sys_regs_t *regs);
329void el1_sysregs_context_restore(el1_sys_regs_t *regs);
330void fpregs_context_save(fp_regs_t *regs);
331void fpregs_context_restore(fp_regs_t *regs);
Achin Gupta9ac63c52014-01-16 12:08:03 +0000332
Soby Mathew5e5c2072014-04-07 15:28:55 +0100333
334/* Per-CPU pointer cache of recently used pointers and also the crash stack
335 * TODO: Add other commonly used variables to this (tf_issues#90)
336 */
337typedef struct per_cpu_ptr_cache {
338 uint64_t crash_stack;
339} per_cpu_ptr_cache_t;
340
341CASSERT(PTR_CACHE_CRASH_STACK_OFFSET == __builtin_offsetof\
342 (per_cpu_ptr_cache_t, crash_stack), \
343 assert_per_cpu_ptr_cache_crash_stack_offset_mismatch);
344
Achin Gupta9ac63c52014-01-16 12:08:03 +0000345#undef CTX_SYSREG_ALL
346#undef CTX_FP_ALL
Achin Gupta07f4e072014-02-02 12:02:23 +0000347#undef CTX_GPREG_ALL
Achin Gupta9ac63c52014-01-16 12:08:03 +0000348#undef CTX_EL3STATE_ALL
349
350#endif /* __ASSEMBLY__ */
351
352#endif /* __CONTEXT_H__ */