Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Sandrine Bailleux | 3fa9847 | 2014-03-31 11:25:18 +0100 | [diff] [blame] | 31 | #include <arch.h> |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 32 | #include <assert.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 33 | #include <bl_common.h> |
| 34 | #include <bl31.h> |
Vikram Kanigiri | 3ff77de | 2014-03-25 17:35:26 +0000 | [diff] [blame] | 35 | #include <console.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 36 | #include <mmio.h> |
| 37 | #include <platform.h> |
| 38 | #include <stddef.h> |
Dan Handley | 4d2e49d | 2014-04-11 11:52:12 +0100 | [diff] [blame] | 39 | #include "drivers/pwrc/fvp_pwrc.h" |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 40 | |
| 41 | /******************************************************************************* |
| 42 | * Declarations of linker defined symbols which will help us find the layout |
| 43 | * of trusted SRAM |
| 44 | ******************************************************************************/ |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 45 | extern unsigned long __RO_START__; |
| 46 | extern unsigned long __RO_END__; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 47 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 48 | extern unsigned long __COHERENT_RAM_START__; |
| 49 | extern unsigned long __COHERENT_RAM_END__; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 50 | |
Sandrine Bailleux | 8d69a03 | 2013-11-27 09:38:52 +0000 | [diff] [blame] | 51 | /* |
| 52 | * The next 2 constants identify the extents of the code & RO data region. |
| 53 | * These addresses are used by the MMU setup code and therefore they must be |
| 54 | * page-aligned. It is the responsibility of the linker script to ensure that |
| 55 | * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. |
| 56 | */ |
| 57 | #define BL31_RO_BASE (unsigned long)(&__RO_START__) |
| 58 | #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) |
| 59 | |
| 60 | /* |
| 61 | * The next 2 constants identify the extents of the coherent memory region. |
| 62 | * These addresses are used by the MMU setup code and therefore they must be |
| 63 | * page-aligned. It is the responsibility of the linker script to ensure that |
| 64 | * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols |
| 65 | * refer to page-aligned addresses. |
| 66 | */ |
| 67 | #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) |
| 68 | #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 69 | |
| 70 | /******************************************************************************* |
Achin Gupta | e4d084e | 2014-02-19 17:18:23 +0000 | [diff] [blame] | 71 | * Reference to structure which holds the arguments that have been passed to |
| 72 | * BL31 from BL2. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 73 | ******************************************************************************/ |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 74 | static bl31_params_t *bl2_to_bl31_params; |
Achin Gupta | 35ca351 | 2014-02-19 17:58:33 +0000 | [diff] [blame] | 75 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 76 | /******************************************************************************* |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 77 | * Return a pointer to the 'entry_point_info' structure of the next image for the |
Achin Gupta | 35ca351 | 2014-02-19 17:58:33 +0000 | [diff] [blame] | 78 | * security state specified. BL33 corresponds to the non-secure image type |
| 79 | * while BL32 corresponds to the secure image type. A NULL pointer is returned |
| 80 | * if the image does not exist. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 81 | ******************************************************************************/ |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 82 | entry_point_info_t *bl31_get_next_image_info(uint32_t type) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 83 | { |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 84 | entry_point_info_t *next_image_info; |
Achin Gupta | 35ca351 | 2014-02-19 17:58:33 +0000 | [diff] [blame] | 85 | |
| 86 | next_image_info = (type == NON_SECURE) ? |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 87 | bl2_to_bl31_params->bl33_ep_info : |
| 88 | bl2_to_bl31_params->bl32_ep_info; |
Achin Gupta | 35ca351 | 2014-02-19 17:58:33 +0000 | [diff] [blame] | 89 | |
| 90 | /* None of the images on this platform can have 0x0 as the entrypoint */ |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 91 | if (next_image_info->pc) |
Achin Gupta | 35ca351 | 2014-02-19 17:58:33 +0000 | [diff] [blame] | 92 | return next_image_info; |
| 93 | else |
| 94 | return NULL; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 95 | } |
| 96 | |
| 97 | /******************************************************************************* |
Achin Gupta | e4d084e | 2014-02-19 17:18:23 +0000 | [diff] [blame] | 98 | * Perform any BL31 specific platform actions. Here is an opportunity to copy |
| 99 | * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they |
| 100 | * are lost (potentially). This needs to be done before the MMU is initialized |
| 101 | * so that the memory layout can be used while creating page tables. On the FVP |
| 102 | * we know that BL2 has populated the parameters in secure DRAM. So we just use |
| 103 | * the reference passed in 'from_bl2' instead of copying. The 'data' parameter |
| 104 | * is not used since all the information is contained in 'from_bl2'. Also, BL2 |
| 105 | * has flushed this information to memory, so we are guaranteed to pick up good |
| 106 | * data |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 107 | ******************************************************************************/ |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 108 | void bl31_early_platform_setup(bl31_params_t *from_bl2, |
Vikram Kanigiri | d8c9d26 | 2014-05-16 18:48:12 +0100 | [diff] [blame^] | 109 | void *plat_params_from_bl2) |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 110 | { |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 111 | assert(from_bl2->h.type == PARAM_BL31); |
| 112 | assert(from_bl2->h.version >= VERSION_1); |
| 113 | |
| 114 | bl2_to_bl31_params = from_bl2; |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 115 | |
Vikram Kanigiri | 3684abf | 2014-03-27 14:33:15 +0000 | [diff] [blame] | 116 | /* Initialize the console to provide early debug support */ |
| 117 | console_init(PL011_UART0_BASE); |
| 118 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 119 | /* Initialize the platform config for future decision making */ |
| 120 | platform_config_setup(); |
| 121 | } |
| 122 | |
| 123 | /******************************************************************************* |
| 124 | * Initialize the gic, configure the CLCD and zero out variables needed by the |
| 125 | * secondaries to boot up correctly. |
| 126 | ******************************************************************************/ |
| 127 | void bl31_platform_setup() |
| 128 | { |
| 129 | unsigned int reg_val; |
| 130 | |
Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 131 | /* Initialize the gic cpu and distributor interfaces */ |
| 132 | gic_setup(); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 133 | |
| 134 | /* |
| 135 | * TODO: Configure the CLCD before handing control to |
| 136 | * linux. Need to see if a separate driver is needed |
| 137 | * instead. |
| 138 | */ |
| 139 | mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGDATA, 0); |
| 140 | mmio_write_32(VE_SYSREGS_BASE + V2M_SYS_CFGCTRL, |
| 141 | (1ull << 31) | (1 << 30) | (7 << 20) | (0 << 16)); |
| 142 | |
Sandrine Bailleux | 3fa9847 | 2014-03-31 11:25:18 +0100 | [diff] [blame] | 143 | /* Enable and initialize the System level generic timer */ |
| 144 | mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN); |
| 145 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 146 | /* Allow access to the System counter timer module */ |
| 147 | reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); |
| 148 | reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); |
| 149 | reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); |
| 150 | mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(0), reg_val); |
| 151 | mmio_write_32(SYS_TIMCTL_BASE + CNTACR_BASE(1), reg_val); |
| 152 | |
| 153 | reg_val = (1 << CNTNSAR_NS_SHIFT(0)) | (1 << CNTNSAR_NS_SHIFT(1)); |
| 154 | mmio_write_32(SYS_TIMCTL_BASE + CNTNSAR, reg_val); |
| 155 | |
| 156 | /* Intialize the power controller */ |
| 157 | fvp_pwrc_setup(); |
| 158 | |
Ian Spray | 8468739 | 2014-01-02 16:57:12 +0000 | [diff] [blame] | 159 | /* Topologies are best known to the platform. */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 160 | plat_setup_topology(); |
| 161 | } |
| 162 | |
| 163 | /******************************************************************************* |
| 164 | * Perform the very early platform specific architectural setup here. At the |
| 165 | * moment this is only intializes the mmu in a quick and dirty way. |
| 166 | ******************************************************************************/ |
| 167 | void bl31_plat_arch_setup() |
| 168 | { |
Vikram Kanigiri | d8c9d26 | 2014-05-16 18:48:12 +0100 | [diff] [blame^] | 169 | configure_mmu_el3(TZRAM_BASE, |
| 170 | TZRAM_SIZE, |
Sandrine Bailleux | 74a62b3 | 2014-05-09 11:35:36 +0100 | [diff] [blame] | 171 | BL31_RO_BASE, |
| 172 | BL31_RO_LIMIT, |
| 173 | BL31_COHERENT_RAM_BASE, |
| 174 | BL31_COHERENT_RAM_LIMIT); |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 175 | } |