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Hadi Asyrafi616da772019-06-27 11:34:03 +08001/*
Chee Hong Ang2382b112020-04-24 21:51:00 +08002 * Copyright (c) 2019-2020, ARM Limited and Contributors. All rights reserved.
Abdul Halim, Muhammad Hadi Asyrafi2f94ca42020-08-05 22:40:46 +08003 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
Hadi Asyrafi616da772019-06-27 11:34:03 +08004 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include <arch.h>
9#include <arch_helpers.h>
10#include <assert.h>
11#include <common/bl_common.h>
12#include <drivers/arm/gicv2.h>
13#include <drivers/ti/uart/uart_16550.h>
Hadi Asyrafi218d8fe2020-01-14 10:51:31 +080014#include <lib/mmio.h>
Hadi Asyrafi616da772019-06-27 11:34:03 +080015#include <lib/xlat_tables/xlat_tables.h>
Hadi Asyrafi616da772019-06-27 11:34:03 +080016
Abdul Halim, Muhammad Hadi Asyrafi2f94ca42020-08-05 22:40:46 +080017#include "ccu/ncore_ccu.h"
Hadi Asyrafi593c4c52019-12-17 19:22:17 +080018#include "socfpga_mailbox.h"
Hadi Asyrafi218d8fe2020-01-14 10:51:31 +080019#include "socfpga_private.h"
Sieu Mun Tangbd8da632022-09-28 15:58:28 +080020#include "socfpga_sip_svc.h"
Hadi Asyrafi616da772019-06-27 11:34:03 +080021
22static entry_point_info_t bl32_image_ep_info;
23static entry_point_info_t bl33_image_ep_info;
24
25entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
26{
27 entry_point_info_t *next_image_info;
28
29 next_image_info = (type == NON_SECURE) ?
30 &bl33_image_ep_info : &bl32_image_ep_info;
31
32 /* None of the images on this platform can have 0x0 as the entrypoint */
33 if (next_image_info->pc)
34 return next_image_info;
35 else
36 return NULL;
37}
38
Sieu Mun Tangbd8da632022-09-28 15:58:28 +080039void setup_smmu_secure_context(void)
40{
41 /*
42 * Program SCR0 register (0xFA000000)
43 * to set SMCFCFG bit[21] to 0x1 which raise stream match conflict fault
44 * to set CLIENTPD bit[0] to 0x0 which enables SMMU for secure context
45 */
46 mmio_write_32(0xFA000000, 0x00200000);
47
48 /*
49 * Program SCR1 register (0xFA000004)
50 * to set NSNUMSMRGO bit[14:8] to 0x4 which stream mapping register
51 * for non-secure context and the rest will be secure context
52 * to set NSNUMCBO bit[5:0] to 0x4 which allocate context bank
53 * for non-secure context and the rest will be secure context
54 */
55 mmio_write_32(0xFA000004, 0x00000404);
56}
57
Hadi Asyrafi616da772019-06-27 11:34:03 +080058void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
59 u_register_t arg2, u_register_t arg3)
60{
Andre Przywara98b5a112020-01-25 00:58:35 +000061 static console_t console;
Hadi Asyrafi616da772019-06-27 11:34:03 +080062
Chee Hong Ang2382b112020-04-24 21:51:00 +080063 mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY);
64
Boon Khai Ngb19ac612021-08-06 01:16:46 +080065 console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
66 PLAT_BAUDRATE, &console);
Hadi Asyrafi616da772019-06-27 11:34:03 +080067 /*
68 * Check params passed from BL31 should not be NULL,
69 */
70 void *from_bl2 = (void *) arg0;
71
72 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
Hadi Asyrafi616da772019-06-27 11:34:03 +080073 assert(params_from_bl2 != NULL);
Hadi Asyrafi616da772019-06-27 11:34:03 +080074
75 /*
76 * Copy BL32 (if populated by BL31) and BL33 entry point information.
77 * They are stored in Secure RAM, in BL31's address space.
78 */
79
Hadi Asyrafi218d8fe2020-01-14 10:51:31 +080080 if (params_from_bl2->h.type == PARAM_BL_PARAMS &&
81 params_from_bl2->h.version >= VERSION_2) {
82
83 bl_params_node_t *bl_params = params_from_bl2->head;
Hadi Asyrafi616da772019-06-27 11:34:03 +080084
Hadi Asyrafi218d8fe2020-01-14 10:51:31 +080085 while (bl_params) {
86 if (bl_params->image_id == BL33_IMAGE_ID)
87 bl33_image_ep_info = *bl_params->ep_info;
Hadi Asyrafi616da772019-06-27 11:34:03 +080088
Hadi Asyrafi218d8fe2020-01-14 10:51:31 +080089 bl_params = bl_params->next_params_info;
90 }
91 } else {
92 struct socfpga_bl31_params *arg_from_bl2 =
93 (struct socfpga_bl31_params *) from_bl2;
94
95 assert(arg_from_bl2->h.type == PARAM_BL31);
96 assert(arg_from_bl2->h.version >= VERSION_1);
97
98 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
99 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
Hadi Asyrafi616da772019-06-27 11:34:03 +0800100 }
101 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
102}
103
104static const interrupt_prop_t s10_interrupt_props[] = {
Hadi Asyrafi9f5dfc92019-10-23 16:26:53 +0800105 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
106 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
Hadi Asyrafi616da772019-06-27 11:34:03 +0800107};
108
109static unsigned int target_mask_array[PLATFORM_CORE_COUNT];
110
111static const gicv2_driver_data_t plat_gicv2_gic_data = {
Hadi Asyrafi9f5dfc92019-10-23 16:26:53 +0800112 .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE,
113 .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE,
Hadi Asyrafi616da772019-06-27 11:34:03 +0800114 .interrupt_props = s10_interrupt_props,
115 .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props),
116 .target_masks = target_mask_array,
117 .target_masks_num = ARRAY_SIZE(target_mask_array),
118};
119
120/*******************************************************************************
121 * Perform any BL3-1 platform setup code
122 ******************************************************************************/
123void bl31_platform_setup(void)
124{
Chee Hong Ang64740962020-05-11 00:55:01 +0800125 socfpga_delay_timer_init();
126
Hadi Asyrafi616da772019-06-27 11:34:03 +0800127 /* Initialize the gic cpu and distributor interfaces */
128 gicv2_driver_init(&plat_gicv2_gic_data);
129 gicv2_distif_init();
130 gicv2_pcpu_distif_init();
131 gicv2_cpuif_enable();
Sieu Mun Tangbd8da632022-09-28 15:58:28 +0800132 setup_smmu_secure_context();
Hadi Asyrafi218d8fe2020-01-14 10:51:31 +0800133
134 /* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */
135 mmio_write_64(PLAT_CPU_RELEASE_ADDR,
136 (uint64_t)plat_secondary_cpus_bl31_entry);
Hadi Asyrafi593c4c52019-12-17 19:22:17 +0800137
138 mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
Hadi Asyrafi616da772019-06-27 11:34:03 +0800139}
140
141const mmap_region_t plat_agilex_mmap[] = {
142 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
143 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS),
Hadi Asyrafie944d222019-07-30 10:56:38 +0800144 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
Hadi Asyrafi616da772019-06-27 11:34:03 +0800145 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
146 MT_NON_CACHEABLE | MT_RW | MT_SECURE),
147 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
148 MT_DEVICE | MT_RW | MT_SECURE),
149 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS),
150 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS),
Hadi Asyrafi5ae876f2019-10-23 17:58:06 +0800151 {0}
Hadi Asyrafi616da772019-06-27 11:34:03 +0800152};
153
154/*******************************************************************************
155 * Perform the very early platform specific architectural setup here. At the
Elyes Haouas2be03c02023-02-13 09:14:48 +0100156 * moment this is only initializes the mmu in a quick and dirty way.
Hadi Asyrafi616da772019-06-27 11:34:03 +0800157 ******************************************************************************/
158void bl31_plat_arch_setup(void)
159{
160 const mmap_region_t bl_regions[] = {
161 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE,
162 MT_MEMORY | MT_RW | MT_SECURE),
163 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE,
164 MT_CODE | MT_SECURE),
165 MAP_REGION_FLAT(BL_RO_DATA_BASE,
166 BL_RO_DATA_END - BL_RO_DATA_BASE,
167 MT_RO_DATA | MT_SECURE),
168#if USE_COHERENT_MEM
169 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE,
170 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
171 MT_DEVICE | MT_RW | MT_SECURE),
172#endif
Hadi Asyrafi5ae876f2019-10-23 17:58:06 +0800173 {0}
Hadi Asyrafi616da772019-06-27 11:34:03 +0800174 };
175
176 setup_page_tables(bl_regions, plat_agilex_mmap);
177 enable_mmu_el3(0);
178}
179