Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved. |
| 3 | * Copyright (c) 2019, Intel Corporation. All rights reserved. |
| 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #include <arch.h> |
| 9 | #include <arch_helpers.h> |
| 10 | #include <assert.h> |
| 11 | #include <common/bl_common.h> |
| 12 | #include <drivers/arm/gicv2.h> |
| 13 | #include <drivers/ti/uart/uart_16550.h> |
Hadi Asyrafi | 218d8fe | 2020-01-14 10:51:31 +0800 | [diff] [blame] | 14 | #include <lib/mmio.h> |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 15 | #include <lib/xlat_tables/xlat_tables.h> |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 16 | |
Hadi Asyrafi | 593c4c5 | 2019-12-17 19:22:17 +0800 | [diff] [blame^] | 17 | #include "socfpga_mailbox.h" |
Hadi Asyrafi | 218d8fe | 2020-01-14 10:51:31 +0800 | [diff] [blame] | 18 | #include "socfpga_private.h" |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 19 | |
| 20 | static entry_point_info_t bl32_image_ep_info; |
| 21 | static entry_point_info_t bl33_image_ep_info; |
| 22 | |
| 23 | entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) |
| 24 | { |
| 25 | entry_point_info_t *next_image_info; |
| 26 | |
| 27 | next_image_info = (type == NON_SECURE) ? |
| 28 | &bl33_image_ep_info : &bl32_image_ep_info; |
| 29 | |
| 30 | /* None of the images on this platform can have 0x0 as the entrypoint */ |
| 31 | if (next_image_info->pc) |
| 32 | return next_image_info; |
| 33 | else |
| 34 | return NULL; |
| 35 | } |
| 36 | |
| 37 | void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, |
| 38 | u_register_t arg2, u_register_t arg3) |
| 39 | { |
| 40 | static console_16550_t console; |
| 41 | |
| 42 | console_16550_register(PLAT_UART0_BASE, PLAT_UART_CLOCK, PLAT_BAUDRATE, |
| 43 | &console); |
| 44 | /* |
| 45 | * Check params passed from BL31 should not be NULL, |
| 46 | */ |
| 47 | void *from_bl2 = (void *) arg0; |
| 48 | |
| 49 | bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 50 | assert(params_from_bl2 != NULL); |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 51 | |
| 52 | /* |
| 53 | * Copy BL32 (if populated by BL31) and BL33 entry point information. |
| 54 | * They are stored in Secure RAM, in BL31's address space. |
| 55 | */ |
| 56 | |
Hadi Asyrafi | 218d8fe | 2020-01-14 10:51:31 +0800 | [diff] [blame] | 57 | if (params_from_bl2->h.type == PARAM_BL_PARAMS && |
| 58 | params_from_bl2->h.version >= VERSION_2) { |
| 59 | |
| 60 | bl_params_node_t *bl_params = params_from_bl2->head; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 61 | |
Hadi Asyrafi | 218d8fe | 2020-01-14 10:51:31 +0800 | [diff] [blame] | 62 | while (bl_params) { |
| 63 | if (bl_params->image_id == BL33_IMAGE_ID) |
| 64 | bl33_image_ep_info = *bl_params->ep_info; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 65 | |
Hadi Asyrafi | 218d8fe | 2020-01-14 10:51:31 +0800 | [diff] [blame] | 66 | bl_params = bl_params->next_params_info; |
| 67 | } |
| 68 | } else { |
| 69 | struct socfpga_bl31_params *arg_from_bl2 = |
| 70 | (struct socfpga_bl31_params *) from_bl2; |
| 71 | |
| 72 | assert(arg_from_bl2->h.type == PARAM_BL31); |
| 73 | assert(arg_from_bl2->h.version >= VERSION_1); |
| 74 | |
| 75 | bl32_image_ep_info = *arg_from_bl2->bl32_ep_info; |
| 76 | bl33_image_ep_info = *arg_from_bl2->bl33_ep_info; |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 77 | } |
| 78 | SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); |
| 79 | } |
| 80 | |
| 81 | static const interrupt_prop_t s10_interrupt_props[] = { |
Hadi Asyrafi | 9f5dfc9 | 2019-10-23 16:26:53 +0800 | [diff] [blame] | 82 | PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0), |
| 83 | PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0) |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 84 | }; |
| 85 | |
| 86 | static unsigned int target_mask_array[PLATFORM_CORE_COUNT]; |
| 87 | |
| 88 | static const gicv2_driver_data_t plat_gicv2_gic_data = { |
Hadi Asyrafi | 9f5dfc9 | 2019-10-23 16:26:53 +0800 | [diff] [blame] | 89 | .gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE, |
| 90 | .gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE, |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 91 | .interrupt_props = s10_interrupt_props, |
| 92 | .interrupt_props_num = ARRAY_SIZE(s10_interrupt_props), |
| 93 | .target_masks = target_mask_array, |
| 94 | .target_masks_num = ARRAY_SIZE(target_mask_array), |
| 95 | }; |
| 96 | |
| 97 | /******************************************************************************* |
| 98 | * Perform any BL3-1 platform setup code |
| 99 | ******************************************************************************/ |
| 100 | void bl31_platform_setup(void) |
| 101 | { |
| 102 | /* Initialize the gic cpu and distributor interfaces */ |
| 103 | gicv2_driver_init(&plat_gicv2_gic_data); |
| 104 | gicv2_distif_init(); |
| 105 | gicv2_pcpu_distif_init(); |
| 106 | gicv2_cpuif_enable(); |
Hadi Asyrafi | 218d8fe | 2020-01-14 10:51:31 +0800 | [diff] [blame] | 107 | |
| 108 | /* Signal secondary CPUs to jump to BL31 (BL2 = U-boot SPL) */ |
| 109 | mmio_write_64(PLAT_CPU_RELEASE_ADDR, |
| 110 | (uint64_t)plat_secondary_cpus_bl31_entry); |
Hadi Asyrafi | 593c4c5 | 2019-12-17 19:22:17 +0800 | [diff] [blame^] | 111 | |
| 112 | mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL); |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 113 | } |
| 114 | |
| 115 | const mmap_region_t plat_agilex_mmap[] = { |
| 116 | MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS), |
| 117 | MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW | MT_NS), |
Hadi Asyrafi | e944d22 | 2019-07-30 10:56:38 +0800 | [diff] [blame] | 118 | MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW | MT_SECURE), |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 119 | MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, |
| 120 | MT_NON_CACHEABLE | MT_RW | MT_SECURE), |
| 121 | MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE, |
| 122 | MT_DEVICE | MT_RW | MT_SECURE), |
| 123 | MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS), |
| 124 | MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE, MT_DEVICE | MT_RW | MT_NS), |
Hadi Asyrafi | 5ae876f | 2019-10-23 17:58:06 +0800 | [diff] [blame] | 125 | {0} |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 126 | }; |
| 127 | |
| 128 | /******************************************************************************* |
| 129 | * Perform the very early platform specific architectural setup here. At the |
| 130 | * moment this is only intializes the mmu in a quick and dirty way. |
| 131 | ******************************************************************************/ |
| 132 | void bl31_plat_arch_setup(void) |
| 133 | { |
| 134 | const mmap_region_t bl_regions[] = { |
| 135 | MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, |
| 136 | MT_MEMORY | MT_RW | MT_SECURE), |
| 137 | MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, |
| 138 | MT_CODE | MT_SECURE), |
| 139 | MAP_REGION_FLAT(BL_RO_DATA_BASE, |
| 140 | BL_RO_DATA_END - BL_RO_DATA_BASE, |
| 141 | MT_RO_DATA | MT_SECURE), |
| 142 | #if USE_COHERENT_MEM |
| 143 | MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, |
| 144 | BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, |
| 145 | MT_DEVICE | MT_RW | MT_SECURE), |
| 146 | #endif |
Hadi Asyrafi | 5ae876f | 2019-10-23 17:58:06 +0800 | [diff] [blame] | 147 | {0} |
Hadi Asyrafi | 616da77 | 2019-06-27 11:34:03 +0800 | [diff] [blame] | 148 | }; |
| 149 | |
| 150 | setup_page_tables(bl_regions, plat_agilex_mmap); |
| 151 | enable_mmu_el3(0); |
| 152 | } |
| 153 | |