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Jimmy Brisson958a0b12020-09-30 15:28:03 -05001/*
Govindraj Rajaeee28e72023-08-01 15:52:40 -05002 * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
Jimmy Brisson958a0b12020-09-30 15:28:03 -05003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef NEOVERSE_V1_H
8#define NEOVERSE_V1_H
9
10#define NEOVERSE_V1_MIDR U(0x410FD400)
11
Bipin Ravi86499742022-01-18 01:59:06 -060012/* Neoverse V1 loop count for CVE-2022-23960 mitigation */
13#define NEOVERSE_V1_BHB_LOOP_COUNT U(32)
14
Jimmy Brisson958a0b12020-09-30 15:28:03 -050015/*******************************************************************************
16 * CPU Extended Control register specific definitions.
17 ******************************************************************************/
18#define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4
Juan Pablo Conde31c93372022-02-28 14:14:44 -050019#define NEOVERSE_V1_CPUPSELR_EL3 S3_6_C15_C8_0
20#define NEOVERSE_V1_CPUPOR_EL3 S3_6_C15_C8_2
21#define NEOVERSE_V1_CPUPMR_EL3 S3_6_C15_C8_3
22#define NEOVERSE_V1_CPUPCR_EL3 S3_6_C15_C8_1
laurenw-arm6b56f962021-08-02 15:00:15 -050023#define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
laurenw-arm3c86d832021-08-02 13:22:32 -050024#define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
nayanpatel-armfc26ffe2021-09-28 13:41:03 -070025#define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3)
26#define CPUECTLR_EL1_PF_MODE_LSB U(6)
27#define CPUECTLR_EL1_PF_MODE_WIDTH U(2)
Jimmy Brisson958a0b12020-09-30 15:28:03 -050028
29/*******************************************************************************
30 * CPU Power Control register specific definitions
31 ******************************************************************************/
32#define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
33#define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
34
johpow01c73b03c2021-05-03 15:33:39 -050035/*******************************************************************************
36 * CPU Auxiliary Control register specific definitions.
37 ******************************************************************************/
38#define NEOVERSE_V1_ACTLR2_EL1 S3_0_C15_C1_1
Bipin Ravi971938f2022-06-08 16:28:46 -050039#define NEOVERSE_V1_ACTLR2_EL1_BIT_0 ULL(1)
johpow01c73b03c2021-05-03 15:33:39 -050040#define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
laurenw-armb1923e92021-08-02 14:40:08 -050041#define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28)
Bipin Ravib4cb31f2022-06-14 17:09:23 -050042#define NEOVERSE_V1_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
johpow01c73b03c2021-05-03 15:33:39 -050043
Sona Mathewfe405d02023-01-11 17:04:24 -060044#define NEOVERSE_V1_ACTLR3_EL1 S3_0_C15_C1_2
Arvind Ram Prakash29cbe722023-07-21 16:01:22 -050045#define NEOVERSE_V1_ACTLR3_EL1_BIT_47 (ULL(1) << 47)
Sona Mathewfe405d02023-01-11 17:04:24 -060046
Sona Mathew2ef5db72023-03-02 15:07:55 -060047#define NEOVERSE_V1_ACTLR5_EL1 S3_0_C15_C9_0
Arvind Ram Prakash29cbe722023-07-21 16:01:22 -050048#define NEOVERSE_V1_ACTLR5_EL1_BIT_55 (ULL(1) << 55)
49#define NEOVERSE_V1_ACTLR5_EL1_BIT_56 (ULL(1) << 56)
Sona Mathewc54b3ef2023-11-07 13:46:15 -060050#define NEOVERSE_V1_ACTLR5_EL1_BIT_61 (ULL(1) << 61)
Sona Mathew2ef5db72023-03-02 15:07:55 -060051
Jimmy Brisson958a0b12020-09-30 15:28:03 -050052#endif /* NEOVERSE_V1_H */