| Jimmy Brisson | 958a0b1 | 2020-09-30 15:28:03 -0500 | [diff] [blame] | 1 | /* |
| Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame^] | 2 | * Copyright (c) 2019-2022, ARM Limited. All rights reserved. |
| Jimmy Brisson | 958a0b1 | 2020-09-30 15:28:03 -0500 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef NEOVERSE_V1_H |
| 8 | #define NEOVERSE_V1_H |
| 9 | |
| 10 | #define NEOVERSE_V1_MIDR U(0x410FD400) |
| 11 | |
| Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame^] | 12 | /* Neoverse V1 loop count for CVE-2022-23960 mitigation */ |
| 13 | #define NEOVERSE_V1_BHB_LOOP_COUNT U(32) |
| 14 | |
| Jimmy Brisson | 958a0b1 | 2020-09-30 15:28:03 -0500 | [diff] [blame] | 15 | /******************************************************************************* |
| 16 | * CPU Extended Control register specific definitions. |
| 17 | ******************************************************************************/ |
| 18 | #define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4 |
| laurenw-arm | 6b56f96 | 2021-08-02 15:00:15 -0500 | [diff] [blame] | 19 | #define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) |
| laurenw-arm | 3c86d83 | 2021-08-02 13:22:32 -0500 | [diff] [blame] | 20 | #define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) |
| nayanpatel-arm | fc26ffe | 2021-09-28 13:41:03 -0700 | [diff] [blame] | 21 | #define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3) |
| 22 | #define CPUECTLR_EL1_PF_MODE_LSB U(6) |
| 23 | #define CPUECTLR_EL1_PF_MODE_WIDTH U(2) |
| Jimmy Brisson | 958a0b1 | 2020-09-30 15:28:03 -0500 | [diff] [blame] | 24 | |
| 25 | /******************************************************************************* |
| 26 | * CPU Power Control register specific definitions |
| 27 | ******************************************************************************/ |
| 28 | #define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 29 | #define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) |
| 30 | |
| johpow01 | c73b03c | 2021-05-03 15:33:39 -0500 | [diff] [blame] | 31 | /******************************************************************************* |
| 32 | * CPU Auxiliary Control register specific definitions. |
| 33 | ******************************************************************************/ |
| 34 | #define NEOVERSE_V1_ACTLR2_EL1 S3_0_C15_C1_1 |
| 35 | #define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2) |
| laurenw-arm | b1923e9 | 2021-08-02 14:40:08 -0500 | [diff] [blame] | 36 | #define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28) |
| johpow01 | c73b03c | 2021-05-03 15:33:39 -0500 | [diff] [blame] | 37 | |
| Jimmy Brisson | 958a0b1 | 2020-09-30 15:28:03 -0500 | [diff] [blame] | 38 | #endif /* NEOVERSE_V1_H */ |