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Jimmy Brisson958a0b12020-09-30 15:28:03 -05001/*
johpow01c73b03c2021-05-03 15:33:39 -05002 * Copyright (c) 2019-2021, ARM Limited. All rights reserved.
Jimmy Brisson958a0b12020-09-30 15:28:03 -05003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef NEOVERSE_V1_H
8#define NEOVERSE_V1_H
9
10#define NEOVERSE_V1_MIDR U(0x410FD400)
11
12/*******************************************************************************
13 * CPU Extended Control register specific definitions.
14 ******************************************************************************/
15#define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4
laurenw-arm6b56f962021-08-02 15:00:15 -050016#define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
laurenw-arm3c86d832021-08-02 13:22:32 -050017#define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
Jimmy Brisson958a0b12020-09-30 15:28:03 -050018
19/*******************************************************************************
20 * CPU Power Control register specific definitions
21 ******************************************************************************/
22#define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
23#define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
24
johpow01c73b03c2021-05-03 15:33:39 -050025/*******************************************************************************
26 * CPU Auxiliary Control register specific definitions.
27 ******************************************************************************/
28#define NEOVERSE_V1_ACTLR2_EL1 S3_0_C15_C1_1
29#define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
laurenw-armb1923e92021-08-02 14:40:08 -050030#define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28)
johpow01c73b03c2021-05-03 15:33:39 -050031
Jimmy Brisson958a0b12020-09-30 15:28:03 -050032#endif /* NEOVERSE_V1_H */