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Achin Gupta9ac63c52014-01-16 12:08:03 +00001/*
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +00002 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
Achin Gupta9ac63c52014-01-16 12:08:03 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta9ac63c52014-01-16 12:08:03 +00005 */
6
Dan Handley2bd4ef22014-04-09 13:14:54 +01007#include <arch.h>
Andrew Thoelke38bde412014-03-18 13:46:55 +00008#include <asm_macros.S>
Jan Dabrosfa015982019-12-02 13:30:03 +01009#include <assert_macros.S>
Dan Handley2bd4ef22014-04-09 13:14:54 +010010#include <context.h>
Manish V Badarkhee07e8082020-07-23 12:43:25 +010011#include <el3_common_macros.S>
Achin Gupta9ac63c52014-01-16 12:08:03 +000012
Max Shvetsovbdf502d2020-02-25 13:56:19 +000013#if CTX_INCLUDE_EL2_REGS
Zelalem Aweke5362beb2022-04-04 17:42:48 -050014 .global el2_sysregs_context_save_common
15 .global el2_sysregs_context_restore_common
16#if ENABLE_SPE_FOR_LOWER_ELS
17 .global el2_sysregs_context_save_spe
18 .global el2_sysregs_context_restore_spe
19#endif /* ENABLE_SPE_FOR_LOWER_ELS */
20#if CTX_INCLUDE_MTE_REGS
21 .global el2_sysregs_context_save_mte
22 .global el2_sysregs_context_restore_mte
23#endif /* CTX_INCLUDE_MTE_REGS */
24#if ENABLE_MPAM_FOR_LOWER_ELS
25 .global el2_sysregs_context_save_mpam
26 .global el2_sysregs_context_restore_mpam
27#endif /* ENABLE_MPAM_FOR_LOWER_ELS */
28#if ENABLE_FEAT_FGT
29 .global el2_sysregs_context_save_fgt
30 .global el2_sysregs_context_restore_fgt
31#endif /* ENABLE_FEAT_FGT */
32#if ENABLE_FEAT_ECV
33 .global el2_sysregs_context_save_ecv
34 .global el2_sysregs_context_restore_ecv
35#endif /* ENABLE_FEAT_ECV */
36#if ENABLE_FEAT_VHE
37 .global el2_sysregs_context_save_vhe
38 .global el2_sysregs_context_restore_vhe
39#endif /* ENABLE_FEAT_VHE */
40#if RAS_EXTENSION
41 .global el2_sysregs_context_save_ras
42 .global el2_sysregs_context_restore_ras
43#endif /* RAS_EXTENSION */
44#if CTX_INCLUDE_NEVE_REGS
45 .global el2_sysregs_context_save_nv2
46 .global el2_sysregs_context_restore_nv2
47#endif /* CTX_INCLUDE_NEVE_REGS */
48#if ENABLE_TRF_FOR_NS
49 .global el2_sysregs_context_save_trf
50 .global el2_sysregs_context_restore_trf
51#endif /* ENABLE_TRF_FOR_NS */
52#if ENABLE_FEAT_CSV2_2
53 .global el2_sysregs_context_save_csv2
54 .global el2_sysregs_context_restore_csv2
55#endif /* ENABLE_FEAT_CSV2_2 */
56#if ENABLE_FEAT_HCX
57 .global el2_sysregs_context_save_hcx
58 .global el2_sysregs_context_restore_hcx
59#endif /* ENABLE_FEAT_HCX */
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +000060#endif /* CTX_INCLUDE_EL2_REGS */
Max Shvetsovbdf502d2020-02-25 13:56:19 +000061
Yatharth Kochar6c0566c2015-10-02 17:56:48 +010062 .global el1_sysregs_context_save
63 .global el1_sysregs_context_restore
64#if CTX_INCLUDE_FPREGS
65 .global fpregs_context_save
66 .global fpregs_context_restore
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +000067#endif /* CTX_INCLUDE_FPREGS */
Daniel Boulby95fb1aa2022-01-19 11:20:05 +000068 .global prepare_el3_entry
Alexei Fedorovf41355c2019-09-13 14:11:59 +010069 .global restore_gp_pmcr_pauth_regs
Manish V Badarkhee07e8082020-07-23 12:43:25 +010070 .global save_and_update_ptw_el1_sys_regs
Yatharth Kochar6c0566c2015-10-02 17:56:48 +010071 .global el3_exit
72
Max Shvetsovbdf502d2020-02-25 13:56:19 +000073#if CTX_INCLUDE_EL2_REGS
74
75/* -----------------------------------------------------
Zelalem Aweke5362beb2022-04-04 17:42:48 -050076 * The following functions strictly follow the AArch64
Max Shvetsovcf784f72021-03-31 19:00:38 +010077 * PCS to use x9-x16 (temporary caller-saved registers)
Zelalem Aweke5362beb2022-04-04 17:42:48 -050078 * to save/restore EL2 system register context.
79 * el2_sysregs_context_save/restore_common functions
80 * save and restore registers that are common to all
81 * configurations. The rest of the functions save and
82 * restore EL2 system registers that are present when a
83 * particular feature is enabled. All functions assume
84 * that 'x0' is pointing to a 'el2_sys_regs' structure
85 * where the register context will be saved/restored.
Max Shvetsovc9e2c922020-02-17 16:15:47 +000086 *
87 * The following registers are not added.
88 * AMEVCNTVOFF0<n>_EL2
89 * AMEVCNTVOFF1<n>_EL2
90 * ICH_AP0R<n>_EL2
91 * ICH_AP1R<n>_EL2
92 * ICH_LR<n>_EL2
Max Shvetsovbdf502d2020-02-25 13:56:19 +000093 * -----------------------------------------------------
94 */
Zelalem Aweke5362beb2022-04-04 17:42:48 -050095func el2_sysregs_context_save_common
Max Shvetsovbdf502d2020-02-25 13:56:19 +000096 mrs x9, actlr_el2
Max Shvetsovc9e2c922020-02-17 16:15:47 +000097 mrs x10, afsr0_el2
98 stp x9, x10, [x0, #CTX_ACTLR_EL2]
Max Shvetsovbdf502d2020-02-25 13:56:19 +000099
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000100 mrs x11, afsr1_el2
101 mrs x12, amair_el2
102 stp x11, x12, [x0, #CTX_AFSR1_EL2]
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000103
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000104 mrs x13, cnthctl_el2
Max Shvetsovcf784f72021-03-31 19:00:38 +0100105 mrs x14, cntvoff_el2
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000106 stp x13, x14, [x0, #CTX_CNTHCTL_EL2]
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000107
Max Shvetsovcf784f72021-03-31 19:00:38 +0100108 mrs x15, cptr_el2
109 str x15, [x0, #CTX_CPTR_EL2]
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000110
Arunachalam Ganapathydca591b2020-05-26 11:32:35 +0100111#if CTX_INCLUDE_AARCH32_REGS
Max Shvetsovcf784f72021-03-31 19:00:38 +0100112 mrs x16, dbgvcr32_el2
113 str x16, [x0, #CTX_DBGVCR32_EL2]
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000114#endif /* CTX_INCLUDE_AARCH32_REGS */
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000115
Max Shvetsovcf784f72021-03-31 19:00:38 +0100116 mrs x9, elr_el2
117 mrs x10, esr_el2
118 stp x9, x10, [x0, #CTX_ELR_EL2]
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000119
Max Shvetsovcf784f72021-03-31 19:00:38 +0100120 mrs x11, far_el2
121 mrs x12, hacr_el2
122 stp x11, x12, [x0, #CTX_FAR_EL2]
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000123
Max Shvetsovcf784f72021-03-31 19:00:38 +0100124 mrs x13, hcr_el2
125 mrs x14, hpfar_el2
126 stp x13, x14, [x0, #CTX_HCR_EL2]
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000127
Max Shvetsovcf784f72021-03-31 19:00:38 +0100128 mrs x15, hstr_el2
129 mrs x16, ICC_SRE_EL2
130 stp x15, x16, [x0, #CTX_HSTR_EL2]
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000131
Max Shvetsovcf784f72021-03-31 19:00:38 +0100132 mrs x9, ICH_HCR_EL2
133 mrs x10, ICH_VMCR_EL2
134 stp x9, x10, [x0, #CTX_ICH_HCR_EL2]
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000135
Max Shvetsovcf784f72021-03-31 19:00:38 +0100136 mrs x11, mair_el2
137 mrs x12, mdcr_el2
138 stp x11, x12, [x0, #CTX_MAIR_EL2]
139
Max Shvetsovcf784f72021-03-31 19:00:38 +0100140 mrs x14, sctlr_el2
141 str x14, [x0, #CTX_SCTLR_EL2]
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000142
Max Shvetsovcf784f72021-03-31 19:00:38 +0100143 mrs x15, spsr_el2
144 mrs x16, sp_el2
145 stp x15, x16, [x0, #CTX_SPSR_EL2]
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000146
Max Shvetsovcf784f72021-03-31 19:00:38 +0100147 mrs x9, tcr_el2
148 mrs x10, tpidr_el2
149 stp x9, x10, [x0, #CTX_TCR_EL2]
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000150
Max Shvetsovcf784f72021-03-31 19:00:38 +0100151 mrs x11, ttbr0_el2
152 mrs x12, vbar_el2
153 stp x11, x12, [x0, #CTX_TTBR0_EL2]
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000154
Max Shvetsovcf784f72021-03-31 19:00:38 +0100155 mrs x13, vmpidr_el2
156 mrs x14, vpidr_el2
157 stp x13, x14, [x0, #CTX_VMPIDR_EL2]
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000158
Max Shvetsovcf784f72021-03-31 19:00:38 +0100159 mrs x15, vtcr_el2
160 mrs x16, vttbr_el2
161 stp x15, x16, [x0, #CTX_VTCR_EL2]
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000162 ret
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500163endfunc el2_sysregs_context_save_common
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000164
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500165func el2_sysregs_context_restore_common
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000166 ldp x9, x10, [x0, #CTX_ACTLR_EL2]
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000167 msr actlr_el2, x9
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000168 msr afsr0_el2, x10
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000169
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000170 ldp x11, x12, [x0, #CTX_AFSR1_EL2]
171 msr afsr1_el2, x11
172 msr amair_el2, x12
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000173
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000174 ldp x13, x14, [x0, #CTX_CNTHCTL_EL2]
175 msr cnthctl_el2, x13
Max Shvetsovcf784f72021-03-31 19:00:38 +0100176 msr cntvoff_el2, x14
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000177
Max Shvetsovcf784f72021-03-31 19:00:38 +0100178 ldr x15, [x0, #CTX_CPTR_EL2]
179 msr cptr_el2, x15
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000180
Arunachalam Ganapathydca591b2020-05-26 11:32:35 +0100181#if CTX_INCLUDE_AARCH32_REGS
Max Shvetsovcf784f72021-03-31 19:00:38 +0100182 ldr x16, [x0, #CTX_DBGVCR32_EL2]
183 msr dbgvcr32_el2, x16
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000184#endif /* CTX_INCLUDE_AARCH32_REGS */
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000185
Max Shvetsovcf784f72021-03-31 19:00:38 +0100186 ldp x9, x10, [x0, #CTX_ELR_EL2]
187 msr elr_el2, x9
188 msr esr_el2, x10
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000189
Max Shvetsovcf784f72021-03-31 19:00:38 +0100190 ldp x11, x12, [x0, #CTX_FAR_EL2]
191 msr far_el2, x11
192 msr hacr_el2, x12
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000193
Max Shvetsovcf784f72021-03-31 19:00:38 +0100194 ldp x13, x14, [x0, #CTX_HCR_EL2]
195 msr hcr_el2, x13
196 msr hpfar_el2, x14
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000197
Max Shvetsovcf784f72021-03-31 19:00:38 +0100198 ldp x15, x16, [x0, #CTX_HSTR_EL2]
199 msr hstr_el2, x15
200 msr ICC_SRE_EL2, x16
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000201
Max Shvetsovcf784f72021-03-31 19:00:38 +0100202 ldp x9, x10, [x0, #CTX_ICH_HCR_EL2]
203 msr ICH_HCR_EL2, x9
204 msr ICH_VMCR_EL2, x10
205
206 ldp x11, x12, [x0, #CTX_MAIR_EL2]
207 msr mair_el2, x11
208 msr mdcr_el2, x12
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000209
Max Shvetsovcf784f72021-03-31 19:00:38 +0100210 ldr x14, [x0, #CTX_SCTLR_EL2]
211 msr sctlr_el2, x14
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000212
Max Shvetsovcf784f72021-03-31 19:00:38 +0100213 ldp x15, x16, [x0, #CTX_SPSR_EL2]
214 msr spsr_el2, x15
215 msr sp_el2, x16
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000216
Max Shvetsovcf784f72021-03-31 19:00:38 +0100217 ldp x9, x10, [x0, #CTX_TCR_EL2]
218 msr tcr_el2, x9
219 msr tpidr_el2, x10
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000220
Max Shvetsovcf784f72021-03-31 19:00:38 +0100221 ldp x11, x12, [x0, #CTX_TTBR0_EL2]
222 msr ttbr0_el2, x11
223 msr vbar_el2, x12
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000224
Max Shvetsovcf784f72021-03-31 19:00:38 +0100225 ldp x13, x14, [x0, #CTX_VMPIDR_EL2]
226 msr vmpidr_el2, x13
227 msr vpidr_el2, x14
Manish V Badarkhed73c1ba2020-07-28 07:12:56 +0100228
Max Shvetsovcf784f72021-03-31 19:00:38 +0100229 ldp x15, x16, [x0, #CTX_VTCR_EL2]
230 msr vtcr_el2, x15
231 msr vttbr_el2, x16
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500232 ret
233endfunc el2_sysregs_context_restore_common
234
235#if ENABLE_SPE_FOR_LOWER_ELS
236func el2_sysregs_context_save_spe
237 mrs x13, PMSCR_EL2
238 str x13, [x0, #CTX_PMSCR_EL2]
239 ret
240endfunc el2_sysregs_context_save_spe
241
242func el2_sysregs_context_restore_spe
243 ldr x13, [x0, #CTX_PMSCR_EL2]
244 msr PMSCR_EL2, x13
245 ret
246endfunc el2_sysregs_context_restore_spe
247#endif /* ENABLE_SPE_FOR_LOWER_ELS */
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000248
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000249#if CTX_INCLUDE_MTE_REGS
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500250func el2_sysregs_context_save_mte
251 mrs x9, TFSR_EL2
252 str x9, [x0, #CTX_TFSR_EL2]
253 ret
254endfunc el2_sysregs_context_save_mte
255
256func el2_sysregs_context_restore_mte
Manish V Badarkhed73c1ba2020-07-28 07:12:56 +0100257 ldr x9, [x0, #CTX_TFSR_EL2]
258 msr TFSR_EL2, x9
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500259 ret
260endfunc el2_sysregs_context_restore_mte
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000261#endif /* CTX_INCLUDE_MTE_REGS */
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000262
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000263#if ENABLE_MPAM_FOR_LOWER_ELS
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500264func el2_sysregs_context_save_mpam
265 mrs x10, MPAM2_EL2
266 str x10, [x0, #CTX_MPAM2_EL2]
267
268 mrs x11, MPAMHCR_EL2
269 mrs x12, MPAMVPM0_EL2
270 stp x11, x12, [x0, #CTX_MPAMHCR_EL2]
271
272 mrs x13, MPAMVPM1_EL2
273 mrs x14, MPAMVPM2_EL2
274 stp x13, x14, [x0, #CTX_MPAMVPM1_EL2]
275
276 mrs x15, MPAMVPM3_EL2
277 mrs x16, MPAMVPM4_EL2
278 stp x15, x16, [x0, #CTX_MPAMVPM3_EL2]
279
280 mrs x9, MPAMVPM5_EL2
281 mrs x10, MPAMVPM6_EL2
282 stp x9, x10, [x0, #CTX_MPAMVPM5_EL2]
283
284 mrs x11, MPAMVPM7_EL2
285 mrs x12, MPAMVPMV_EL2
286 stp x11, x12, [x0, #CTX_MPAMVPM7_EL2]
287 ret
288endfunc func el2_sysregs_context_save_mpam
289
290func el2_sysregs_context_restore_mpam
Max Shvetsovcf784f72021-03-31 19:00:38 +0100291 ldr x10, [x0, #CTX_MPAM2_EL2]
Manish V Badarkhed73c1ba2020-07-28 07:12:56 +0100292 msr MPAM2_EL2, x10
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000293
Max Shvetsovcf784f72021-03-31 19:00:38 +0100294 ldp x11, x12, [x0, #CTX_MPAMHCR_EL2]
295 msr MPAMHCR_EL2, x11
Manish V Badarkhed73c1ba2020-07-28 07:12:56 +0100296 msr MPAMVPM0_EL2, x12
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000297
Max Shvetsovcf784f72021-03-31 19:00:38 +0100298 ldp x13, x14, [x0, #CTX_MPAMVPM1_EL2]
299 msr MPAMVPM1_EL2, x13
Manish V Badarkhed73c1ba2020-07-28 07:12:56 +0100300 msr MPAMVPM2_EL2, x14
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000301
Max Shvetsovcf784f72021-03-31 19:00:38 +0100302 ldp x15, x16, [x0, #CTX_MPAMVPM3_EL2]
303 msr MPAMVPM3_EL2, x15
Manish V Badarkhed73c1ba2020-07-28 07:12:56 +0100304 msr MPAMVPM4_EL2, x16
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000305
Max Shvetsovcf784f72021-03-31 19:00:38 +0100306 ldp x9, x10, [x0, #CTX_MPAMVPM5_EL2]
307 msr MPAMVPM5_EL2, x9
308 msr MPAMVPM6_EL2, x10
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000309
Max Shvetsovcf784f72021-03-31 19:00:38 +0100310 ldp x11, x12, [x0, #CTX_MPAMVPM7_EL2]
311 msr MPAMVPM7_EL2, x11
312 msr MPAMVPMV_EL2, x12
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500313 ret
314endfunc el2_sysregs_context_restore_mpam
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000315#endif /* ENABLE_MPAM_FOR_LOWER_ELS */
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000316
Jayanth Dodderi Chidanand13ae0f42021-11-25 14:59:30 +0000317#if ENABLE_FEAT_FGT
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500318func el2_sysregs_context_save_fgt
319 mrs x13, HDFGRTR_EL2
Jayanth Dodderi Chidanand13ae0f42021-11-25 14:59:30 +0000320#if ENABLE_FEAT_AMUv1
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500321 mrs x14, HAFGRTR_EL2
322 stp x13, x14, [x0, #CTX_HDFGRTR_EL2]
323#else
324 str x13, [x0, #CTX_HDFGRTR_EL2]
325#endif /* ENABLE_FEAT_AMUv1 */
326 mrs x15, HDFGWTR_EL2
327 mrs x16, HFGITR_EL2
328 stp x15, x16, [x0, #CTX_HDFGWTR_EL2]
329
330 mrs x9, HFGRTR_EL2
331 mrs x10, HFGWTR_EL2
332 stp x9, x10, [x0, #CTX_HFGRTR_EL2]
333 ret
334endfunc el2_sysregs_context_save_fgt
335
336func el2_sysregs_context_restore_fgt
337 #if ENABLE_FEAT_AMUv1
Jayanth Dodderi Chidanand13ae0f42021-11-25 14:59:30 +0000338 ldp x13, x14, [x0, #CTX_HDFGRTR_EL2]
339 msr HAFGRTR_EL2, x14
340#else
341 ldr x13, [x0, #CTX_HDFGRTR_EL2]
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000342#endif /* ENABLE_FEAT_AMUv1 */
Jayanth Dodderi Chidanand13ae0f42021-11-25 14:59:30 +0000343 msr HDFGRTR_EL2, x13
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000344
Max Shvetsovcf784f72021-03-31 19:00:38 +0100345 ldp x15, x16, [x0, #CTX_HDFGWTR_EL2]
346 msr HDFGWTR_EL2, x15
347 msr HFGITR_EL2, x16
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000348
Max Shvetsovcf784f72021-03-31 19:00:38 +0100349 ldp x9, x10, [x0, #CTX_HFGRTR_EL2]
350 msr HFGRTR_EL2, x9
351 msr HFGWTR_EL2, x10
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500352 ret
353endfunc el2_sysregs_context_restore_fgt
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000354#endif /* ENABLE_FEAT_FGT */
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000355
Jayanth Dodderi Chidanand13ae0f42021-11-25 14:59:30 +0000356#if ENABLE_FEAT_ECV
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500357func el2_sysregs_context_save_ecv
358 mrs x11, CNTPOFF_EL2
359 str x11, [x0, #CTX_CNTPOFF_EL2]
360 ret
361endfunc el2_sysregs_context_save_ecv
362
363func el2_sysregs_context_restore_ecv
Max Shvetsovcf784f72021-03-31 19:00:38 +0100364 ldr x11, [x0, #CTX_CNTPOFF_EL2]
365 msr CNTPOFF_EL2, x11
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500366 ret
367endfunc el2_sysregs_context_restore_ecv
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000368#endif /* ENABLE_FEAT_ECV */
369
370#if ENABLE_FEAT_VHE
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500371func el2_sysregs_context_save_vhe
372 /*
373 * CONTEXTIDR_EL2 register is saved only when FEAT_VHE or
374 * FEAT_Debugv8p2 (currently not in TF-A) is supported.
375 */
376 mrs x9, contextidr_el2
377 mrs x10, ttbr1_el2
378 stp x9, x10, [x0, #CTX_CONTEXTIDR_EL2]
379 ret
380endfunc el2_sysregs_context_save_vhe
381
382func el2_sysregs_context_restore_vhe
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000383 /*
384 * CONTEXTIDR_EL2 register is restored only when FEAT_VHE or
385 * FEAT_Debugv8p2 (currently not in TF-A) is supported.
386 */
387 ldp x9, x10, [x0, #CTX_CONTEXTIDR_EL2]
388 msr contextidr_el2, x9
389 msr ttbr1_el2, x10
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500390 ret
391endfunc el2_sysregs_context_restore_vhe
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000392#endif /* ENABLE_FEAT_VHE */
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000393
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000394#if RAS_EXTENSION
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500395func el2_sysregs_context_save_ras
396 /*
397 * VDISR_EL2 and VSESR_EL2 registers are saved only when
398 * FEAT_RAS is supported.
399 */
400 mrs x11, vdisr_el2
401 mrs x12, vsesr_el2
402 stp x11, x12, [x0, #CTX_VDISR_EL2]
403 ret
404endfunc el2_sysregs_context_save_ras
405
406func el2_sysregs_context_restore_ras
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000407 /*
408 * VDISR_EL2 and VSESR_EL2 registers are restored only when FEAT_RAS
409 * is supported.
410 */
411 ldp x11, x12, [x0, #CTX_VDISR_EL2]
412 msr vdisr_el2, x11
413 msr vsesr_el2, x12
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500414 ret
415endfunc el2_sysregs_context_restore_ras
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000416#endif /* RAS_EXTENSION */
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000417
Arunachalam Ganapathydd3ec7e2020-05-28 11:57:09 +0100418#if CTX_INCLUDE_NEVE_REGS
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500419func el2_sysregs_context_save_nv2
420 /*
421 * VNCR_EL2 register is saved only when FEAT_NV2 is supported.
422 */
423 mrs x16, vncr_el2
424 str x16, [x0, #CTX_VNCR_EL2]
425 ret
426endfunc el2_sysregs_context_save_nv2
427
428func el2_sysregs_context_restore_nv2
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000429 /*
430 * VNCR_EL2 register is restored only when FEAT_NV2 is supported.
431 */
Max Shvetsovcf784f72021-03-31 19:00:38 +0100432 ldr x16, [x0, #CTX_VNCR_EL2]
433 msr vncr_el2, x16
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500434 ret
435endfunc el2_sysregs_context_restore_nv2
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000436#endif /* CTX_INCLUDE_NEVE_REGS */
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000437
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000438#if ENABLE_TRF_FOR_NS
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500439func el2_sysregs_context_save_trf
440 /*
441 * TRFCR_EL2 register is saved only when FEAT_TRF is supported.
442 */
443 mrs x12, TRFCR_EL2
444 str x12, [x0, #CTX_TRFCR_EL2]
445 ret
446endfunc el2_sysregs_context_save_trf
447
448func el2_sysregs_context_restore_trf
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000449 /*
450 * TRFCR_EL2 register is restored only when FEAT_TRF is supported.
451 */
452 ldr x12, [x0, #CTX_TRFCR_EL2]
Max Shvetsovcf784f72021-03-31 19:00:38 +0100453 msr TRFCR_EL2, x12
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500454 ret
455endfunc el2_sysregs_context_restore_trf
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000456#endif /* ENABLE_TRF_FOR_NS */
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000457
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000458#if ENABLE_FEAT_CSV2_2
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500459func el2_sysregs_context_save_csv2
460 /*
461 * SCXTNUM_EL2 register is saved only when FEAT_CSV2_2 is supported.
462 */
463 mrs x13, scxtnum_el2
464 str x13, [x0, #CTX_SCXTNUM_EL2]
465 ret
466endfunc el2_sysregs_context_save_csv2
467
468func el2_sysregs_context_restore_csv2
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000469 /*
470 * SCXTNUM_EL2 register is restored only when FEAT_CSV2_2 is supported.
471 */
Max Shvetsovcf784f72021-03-31 19:00:38 +0100472 ldr x13, [x0, #CTX_SCXTNUM_EL2]
473 msr scxtnum_el2, x13
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500474 ret
475endfunc el2_sysregs_context_restore_csv2
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000476#endif /* ENABLE_FEAT_CSV2_2 */
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000477
johpow01f91e59f2021-08-04 19:38:18 -0500478#if ENABLE_FEAT_HCX
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500479func el2_sysregs_context_save_hcx
480 mrs x14, hcrx_el2
481 str x14, [x0, #CTX_HCRX_EL2]
482 ret
483endfunc el2_sysregs_context_save_hcx
484
485func el2_sysregs_context_restore_hcx
johpow01f91e59f2021-08-04 19:38:18 -0500486 ldr x14, [x0, #CTX_HCRX_EL2]
487 msr hcrx_el2, x14
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000488 ret
Zelalem Aweke5362beb2022-04-04 17:42:48 -0500489endfunc el2_sysregs_context_restore_hcx
490#endif /* ENABLE_FEAT_HCX */
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000491#endif /* CTX_INCLUDE_EL2_REGS */
492
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100493/* ------------------------------------------------------------------
494 * The following function strictly follows the AArch64 PCS to use
495 * x9-x17 (temporary caller-saved registers) to save EL1 system
496 * register context. It assumes that 'x0' is pointing to a
497 * 'el1_sys_regs' structure where the register context will be saved.
498 * ------------------------------------------------------------------
Achin Gupta9ac63c52014-01-16 12:08:03 +0000499 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000500func el1_sysregs_context_save
Achin Gupta9ac63c52014-01-16 12:08:03 +0000501
502 mrs x9, spsr_el1
503 mrs x10, elr_el1
504 stp x9, x10, [x0, #CTX_SPSR_EL1]
505
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100506#if !ERRATA_SPECULATIVE_AT
Achin Gupta9ac63c52014-01-16 12:08:03 +0000507 mrs x15, sctlr_el1
Manish V Badarkhe2b0ee972020-07-28 07:22:30 +0100508 mrs x16, tcr_el1
Achin Gupta9ac63c52014-01-16 12:08:03 +0000509 stp x15, x16, [x0, #CTX_SCTLR_EL1]
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000510#endif /* ERRATA_SPECULATIVE_AT */
Achin Gupta9ac63c52014-01-16 12:08:03 +0000511
512 mrs x17, cpacr_el1
513 mrs x9, csselr_el1
514 stp x17, x9, [x0, #CTX_CPACR_EL1]
515
516 mrs x10, sp_el1
517 mrs x11, esr_el1
518 stp x10, x11, [x0, #CTX_SP_EL1]
519
520 mrs x12, ttbr0_el1
521 mrs x13, ttbr1_el1
522 stp x12, x13, [x0, #CTX_TTBR0_EL1]
523
524 mrs x14, mair_el1
525 mrs x15, amair_el1
526 stp x14, x15, [x0, #CTX_MAIR_EL1]
527
Manish V Badarkhe2b0ee972020-07-28 07:22:30 +0100528 mrs x16, actlr_el1
Achin Gupta9ac63c52014-01-16 12:08:03 +0000529 mrs x17, tpidr_el1
Manish V Badarkhe2b0ee972020-07-28 07:22:30 +0100530 stp x16, x17, [x0, #CTX_ACTLR_EL1]
Achin Gupta9ac63c52014-01-16 12:08:03 +0000531
532 mrs x9, tpidr_el0
533 mrs x10, tpidrro_el0
534 stp x9, x10, [x0, #CTX_TPIDR_EL0]
535
Achin Gupta9ac63c52014-01-16 12:08:03 +0000536 mrs x13, par_el1
537 mrs x14, far_el1
538 stp x13, x14, [x0, #CTX_PAR_EL1]
539
540 mrs x15, afsr0_el1
541 mrs x16, afsr1_el1
542 stp x15, x16, [x0, #CTX_AFSR0_EL1]
543
544 mrs x17, contextidr_el1
545 mrs x9, vbar_el1
546 stp x17, x9, [x0, #CTX_CONTEXTIDR_EL1]
547
Soby Mathewd75d2ba2016-05-17 14:01:32 +0100548 /* Save AArch32 system registers if the build has instructed so */
549#if CTX_INCLUDE_AARCH32_REGS
550 mrs x11, spsr_abt
551 mrs x12, spsr_und
552 stp x11, x12, [x0, #CTX_SPSR_ABT]
553
554 mrs x13, spsr_irq
555 mrs x14, spsr_fiq
556 stp x13, x14, [x0, #CTX_SPSR_IRQ]
557
558 mrs x15, dacr32_el2
559 mrs x16, ifsr32_el2
560 stp x15, x16, [x0, #CTX_DACR32_EL2]
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000561#endif /* CTX_INCLUDE_AARCH32_REGS */
Soby Mathewd75d2ba2016-05-17 14:01:32 +0100562
Jeenu Viswambharand1b60152014-05-12 15:28:47 +0100563 /* Save NS timer registers if the build has instructed so */
564#if NS_TIMER_SWITCH
Achin Gupta9ac63c52014-01-16 12:08:03 +0000565 mrs x10, cntp_ctl_el0
566 mrs x11, cntp_cval_el0
567 stp x10, x11, [x0, #CTX_CNTP_CTL_EL0]
568
569 mrs x12, cntv_ctl_el0
570 mrs x13, cntv_cval_el0
571 stp x12, x13, [x0, #CTX_CNTV_CTL_EL0]
572
573 mrs x14, cntkctl_el1
Jeenu Viswambharand1b60152014-05-12 15:28:47 +0100574 str x14, [x0, #CTX_CNTKCTL_EL1]
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000575#endif /* NS_TIMER_SWITCH */
Jeenu Viswambharand1b60152014-05-12 15:28:47 +0100576
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100577 /* Save MTE system registers if the build has instructed so */
578#if CTX_INCLUDE_MTE_REGS
579 mrs x15, TFSRE0_EL1
580 mrs x16, TFSR_EL1
581 stp x15, x16, [x0, #CTX_TFSRE0_EL1]
582
583 mrs x9, RGSR_EL1
584 mrs x10, GCR_EL1
585 stp x9, x10, [x0, #CTX_RGSR_EL1]
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000586#endif /* CTX_INCLUDE_MTE_REGS */
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100587
Achin Gupta9ac63c52014-01-16 12:08:03 +0000588 ret
Kévin Petita877c252015-03-24 14:03:57 +0000589endfunc el1_sysregs_context_save
Achin Gupta9ac63c52014-01-16 12:08:03 +0000590
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100591/* ------------------------------------------------------------------
592 * The following function strictly follows the AArch64 PCS to use
593 * x9-x17 (temporary caller-saved registers) to restore EL1 system
594 * register context. It assumes that 'x0' is pointing to a
595 * 'el1_sys_regs' structure from where the register context will be
596 * restored
597 * ------------------------------------------------------------------
Achin Gupta9ac63c52014-01-16 12:08:03 +0000598 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000599func el1_sysregs_context_restore
Achin Gupta9ac63c52014-01-16 12:08:03 +0000600
601 ldp x9, x10, [x0, #CTX_SPSR_EL1]
602 msr spsr_el1, x9
603 msr elr_el1, x10
604
Manish V Badarkhee07e8082020-07-23 12:43:25 +0100605#if !ERRATA_SPECULATIVE_AT
Manish V Badarkhed73c1ba2020-07-28 07:12:56 +0100606 ldp x15, x16, [x0, #CTX_SCTLR_EL1]
607 msr sctlr_el1, x15
Manish V Badarkhe2b0ee972020-07-28 07:22:30 +0100608 msr tcr_el1, x16
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000609#endif /* ERRATA_SPECULATIVE_AT */
Achin Gupta9ac63c52014-01-16 12:08:03 +0000610
611 ldp x17, x9, [x0, #CTX_CPACR_EL1]
612 msr cpacr_el1, x17
613 msr csselr_el1, x9
614
615 ldp x10, x11, [x0, #CTX_SP_EL1]
616 msr sp_el1, x10
617 msr esr_el1, x11
618
619 ldp x12, x13, [x0, #CTX_TTBR0_EL1]
620 msr ttbr0_el1, x12
621 msr ttbr1_el1, x13
622
623 ldp x14, x15, [x0, #CTX_MAIR_EL1]
624 msr mair_el1, x14
625 msr amair_el1, x15
626
Manish V Badarkhe2b0ee972020-07-28 07:22:30 +0100627 ldp x16, x17, [x0, #CTX_ACTLR_EL1]
628 msr actlr_el1, x16
Manish V Badarkhed73c1ba2020-07-28 07:12:56 +0100629 msr tpidr_el1, x17
Achin Gupta9ac63c52014-01-16 12:08:03 +0000630
631 ldp x9, x10, [x0, #CTX_TPIDR_EL0]
632 msr tpidr_el0, x9
633 msr tpidrro_el0, x10
634
Achin Gupta9ac63c52014-01-16 12:08:03 +0000635 ldp x13, x14, [x0, #CTX_PAR_EL1]
636 msr par_el1, x13
637 msr far_el1, x14
638
639 ldp x15, x16, [x0, #CTX_AFSR0_EL1]
640 msr afsr0_el1, x15
641 msr afsr1_el1, x16
642
643 ldp x17, x9, [x0, #CTX_CONTEXTIDR_EL1]
644 msr contextidr_el1, x17
645 msr vbar_el1, x9
646
Soby Mathewd75d2ba2016-05-17 14:01:32 +0100647 /* Restore AArch32 system registers if the build has instructed so */
648#if CTX_INCLUDE_AARCH32_REGS
649 ldp x11, x12, [x0, #CTX_SPSR_ABT]
650 msr spsr_abt, x11
651 msr spsr_und, x12
652
653 ldp x13, x14, [x0, #CTX_SPSR_IRQ]
654 msr spsr_irq, x13
655 msr spsr_fiq, x14
656
657 ldp x15, x16, [x0, #CTX_DACR32_EL2]
658 msr dacr32_el2, x15
659 msr ifsr32_el2, x16
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000660#endif /* CTX_INCLUDE_AARCH32_REGS */
661
Jeenu Viswambharand1b60152014-05-12 15:28:47 +0100662 /* Restore NS timer registers if the build has instructed so */
663#if NS_TIMER_SWITCH
Achin Gupta9ac63c52014-01-16 12:08:03 +0000664 ldp x10, x11, [x0, #CTX_CNTP_CTL_EL0]
665 msr cntp_ctl_el0, x10
666 msr cntp_cval_el0, x11
667
668 ldp x12, x13, [x0, #CTX_CNTV_CTL_EL0]
669 msr cntv_ctl_el0, x12
670 msr cntv_cval_el0, x13
671
Jeenu Viswambharand1b60152014-05-12 15:28:47 +0100672 ldr x14, [x0, #CTX_CNTKCTL_EL1]
Achin Gupta9ac63c52014-01-16 12:08:03 +0000673 msr cntkctl_el1, x14
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000674#endif /* NS_TIMER_SWITCH */
675
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100676 /* Restore MTE system registers if the build has instructed so */
677#if CTX_INCLUDE_MTE_REGS
678 ldp x11, x12, [x0, #CTX_TFSRE0_EL1]
679 msr TFSRE0_EL1, x11
680 msr TFSR_EL1, x12
681
682 ldp x13, x14, [x0, #CTX_RGSR_EL1]
683 msr RGSR_EL1, x13
684 msr GCR_EL1, x14
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000685#endif /* CTX_INCLUDE_MTE_REGS */
Jeenu Viswambharand1b60152014-05-12 15:28:47 +0100686
Achin Gupta9ac63c52014-01-16 12:08:03 +0000687 /* No explict ISB required here as ERET covers it */
Achin Gupta9ac63c52014-01-16 12:08:03 +0000688 ret
Kévin Petita877c252015-03-24 14:03:57 +0000689endfunc el1_sysregs_context_restore
Achin Gupta9ac63c52014-01-16 12:08:03 +0000690
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100691/* ------------------------------------------------------------------
692 * The following function follows the aapcs_64 strictly to use
693 * x9-x17 (temporary caller-saved registers according to AArch64 PCS)
694 * to save floating point register context. It assumes that 'x0' is
695 * pointing to a 'fp_regs' structure where the register context will
Achin Gupta9ac63c52014-01-16 12:08:03 +0000696 * be saved.
697 *
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100698 * Access to VFP registers will trap if CPTR_EL3.TFP is set.
699 * However currently we don't use VFP registers nor set traps in
700 * Trusted Firmware, and assume it's cleared.
Achin Gupta9ac63c52014-01-16 12:08:03 +0000701 *
702 * TODO: Revisit when VFP is used in secure world
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100703 * ------------------------------------------------------------------
Achin Gupta9ac63c52014-01-16 12:08:03 +0000704 */
Juan Castillo258e94f2014-06-25 17:26:36 +0100705#if CTX_INCLUDE_FPREGS
Andrew Thoelke38bde412014-03-18 13:46:55 +0000706func fpregs_context_save
Achin Gupta9ac63c52014-01-16 12:08:03 +0000707 stp q0, q1, [x0, #CTX_FP_Q0]
708 stp q2, q3, [x0, #CTX_FP_Q2]
709 stp q4, q5, [x0, #CTX_FP_Q4]
710 stp q6, q7, [x0, #CTX_FP_Q6]
711 stp q8, q9, [x0, #CTX_FP_Q8]
712 stp q10, q11, [x0, #CTX_FP_Q10]
713 stp q12, q13, [x0, #CTX_FP_Q12]
714 stp q14, q15, [x0, #CTX_FP_Q14]
715 stp q16, q17, [x0, #CTX_FP_Q16]
716 stp q18, q19, [x0, #CTX_FP_Q18]
717 stp q20, q21, [x0, #CTX_FP_Q20]
718 stp q22, q23, [x0, #CTX_FP_Q22]
719 stp q24, q25, [x0, #CTX_FP_Q24]
720 stp q26, q27, [x0, #CTX_FP_Q26]
721 stp q28, q29, [x0, #CTX_FP_Q28]
722 stp q30, q31, [x0, #CTX_FP_Q30]
723
724 mrs x9, fpsr
725 str x9, [x0, #CTX_FP_FPSR]
726
727 mrs x10, fpcr
728 str x10, [x0, #CTX_FP_FPCR]
729
David Cunadod1a1fd42017-10-20 11:30:57 +0100730#if CTX_INCLUDE_AARCH32_REGS
731 mrs x11, fpexc32_el2
732 str x11, [x0, #CTX_FP_FPEXC32_EL2]
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000733#endif /* CTX_INCLUDE_AARCH32_REGS */
Achin Gupta9ac63c52014-01-16 12:08:03 +0000734 ret
Kévin Petita877c252015-03-24 14:03:57 +0000735endfunc fpregs_context_save
Achin Gupta9ac63c52014-01-16 12:08:03 +0000736
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100737/* ------------------------------------------------------------------
738 * The following function follows the aapcs_64 strictly to use x9-x17
739 * (temporary caller-saved registers according to AArch64 PCS) to
740 * restore floating point register context. It assumes that 'x0' is
741 * pointing to a 'fp_regs' structure from where the register context
Achin Gupta9ac63c52014-01-16 12:08:03 +0000742 * will be restored.
743 *
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100744 * Access to VFP registers will trap if CPTR_EL3.TFP is set.
745 * However currently we don't use VFP registers nor set traps in
746 * Trusted Firmware, and assume it's cleared.
Achin Gupta9ac63c52014-01-16 12:08:03 +0000747 *
748 * TODO: Revisit when VFP is used in secure world
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100749 * ------------------------------------------------------------------
Achin Gupta9ac63c52014-01-16 12:08:03 +0000750 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000751func fpregs_context_restore
Achin Gupta9ac63c52014-01-16 12:08:03 +0000752 ldp q0, q1, [x0, #CTX_FP_Q0]
753 ldp q2, q3, [x0, #CTX_FP_Q2]
754 ldp q4, q5, [x0, #CTX_FP_Q4]
755 ldp q6, q7, [x0, #CTX_FP_Q6]
756 ldp q8, q9, [x0, #CTX_FP_Q8]
757 ldp q10, q11, [x0, #CTX_FP_Q10]
758 ldp q12, q13, [x0, #CTX_FP_Q12]
759 ldp q14, q15, [x0, #CTX_FP_Q14]
760 ldp q16, q17, [x0, #CTX_FP_Q16]
761 ldp q18, q19, [x0, #CTX_FP_Q18]
762 ldp q20, q21, [x0, #CTX_FP_Q20]
763 ldp q22, q23, [x0, #CTX_FP_Q22]
764 ldp q24, q25, [x0, #CTX_FP_Q24]
765 ldp q26, q27, [x0, #CTX_FP_Q26]
766 ldp q28, q29, [x0, #CTX_FP_Q28]
767 ldp q30, q31, [x0, #CTX_FP_Q30]
768
769 ldr x9, [x0, #CTX_FP_FPSR]
770 msr fpsr, x9
771
Soby Mathewe77e1162015-12-03 09:42:50 +0000772 ldr x10, [x0, #CTX_FP_FPCR]
Achin Gupta9ac63c52014-01-16 12:08:03 +0000773 msr fpcr, x10
774
David Cunadod1a1fd42017-10-20 11:30:57 +0100775#if CTX_INCLUDE_AARCH32_REGS
776 ldr x11, [x0, #CTX_FP_FPEXC32_EL2]
777 msr fpexc32_el2, x11
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000778#endif /* CTX_INCLUDE_AARCH32_REGS */
779
Achin Gupta9ac63c52014-01-16 12:08:03 +0000780 /*
781 * No explict ISB required here as ERET to
Sandrine Bailleuxf4119ec2015-12-17 13:58:58 +0000782 * switch to secure EL1 or non-secure world
Achin Gupta9ac63c52014-01-16 12:08:03 +0000783 * covers it
784 */
785
786 ret
Kévin Petita877c252015-03-24 14:03:57 +0000787endfunc fpregs_context_restore
Juan Castillo258e94f2014-06-25 17:26:36 +0100788#endif /* CTX_INCLUDE_FPREGS */
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100789
Daniel Boulby928747f2021-05-25 18:09:34 +0100790 /*
791 * Set the PSTATE bits not set when the exception was taken as
792 * described in the AArch64.TakeException() pseudocode function
793 * in ARM DDI 0487F.c page J1-7635 to a default value.
794 */
795 .macro set_unset_pstate_bits
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000796 /*
797 * If Data Independent Timing (DIT) functionality is implemented,
798 * always enable DIT in EL3
799 */
Daniel Boulby928747f2021-05-25 18:09:34 +0100800#if ENABLE_FEAT_DIT
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +0000801 mov x8, #DIT_BIT
802 msr DIT, x8
Daniel Boulby928747f2021-05-25 18:09:34 +0100803#endif /* ENABLE_FEAT_DIT */
804 .endm /* set_unset_pstate_bits */
805
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100806/* ------------------------------------------------------------------
Daniel Boulby95fb1aa2022-01-19 11:20:05 +0000807 * The following macro is used to save and restore all the general
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100808 * purpose and ARMv8.3-PAuth (if enabled) registers.
Jayanth Dodderi Chidanand4ec78ad2022-09-19 23:32:08 +0100809 * It also checks if the Secure Cycle Counter (PMCCNTR_EL0)
810 * is disabled in EL3/Secure (ARMv8.5-PMU), wherein PMCCNTR_EL0
811 * needs not to be saved/restored during world switch.
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100812 *
813 * Ideally we would only save and restore the callee saved registers
814 * when a world switch occurs but that type of implementation is more
815 * complex. So currently we will always save and restore these
816 * registers on entry and exit of EL3.
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100817 * clobbers: x18
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100818 * ------------------------------------------------------------------
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100819 */
Daniel Boulby95fb1aa2022-01-19 11:20:05 +0000820 .macro save_gp_pmcr_pauth_regs
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100821 stp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
822 stp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
823 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
824 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
825 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
826 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
827 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
828 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
829 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
830 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
831 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
832 stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
833 stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
834 stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
835 stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
836 mrs x18, sp_el0
837 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100838
839 /* ----------------------------------------------------------
Jayanth Dodderi Chidanand4ec78ad2022-09-19 23:32:08 +0100840 * Check if earlier initialization of MDCR_EL3.SCCD/MCCD to 1
841 * has failed.
842 *
843 * MDCR_EL3:
844 * MCCD bit set, Prohibits the Cycle Counter PMCCNTR_EL0 from
845 * counting at EL3.
846 * SCCD bit set, Secure Cycle Counter Disable. Prohibits PMCCNTR_EL0
847 * from counting in Secure state.
848 * If these bits are not set, meaning that FEAT_PMUv3p5/7 is
849 * not implemented and PMCR_EL0 should be saved in non-secure
850 * context.
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100851 * ----------------------------------------------------------
852 */
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100853 mov_imm x10, (MDCR_SCCD_BIT | MDCR_MCCD_BIT)
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100854 mrs x9, mdcr_el3
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100855 tst x9, x10
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100856 bne 1f
857
Jayanth Dodderi Chidanand4ec78ad2022-09-19 23:32:08 +0100858 /* ----------------------------------------------------------
859 * If control reaches here, it ensures the Secure Cycle
860 * Counter (PMCCNTR_EL0) is not prohibited from counting at
861 * EL3 and in secure states.
862 * Henceforth, PMCR_EL0 to be saved before world switch.
863 * ----------------------------------------------------------
864 */
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100865 mrs x9, pmcr_el0
866
867 /* Check caller's security state */
868 mrs x10, scr_el3
869 tst x10, #SCR_NS_BIT
870 beq 2f
871
872 /* Save PMCR_EL0 if called from Non-secure state */
873 str x9, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
874
875 /* Disable cycle counter when event counting is prohibited */
8762: orr x9, x9, #PMCR_EL0_DP_BIT
877 msr pmcr_el0, x9
878 isb
8791:
880#if CTX_INCLUDE_PAUTH_REGS
881 /* ----------------------------------------------------------
882 * Save the ARMv8.3-PAuth keys as they are not banked
883 * by exception level
884 * ----------------------------------------------------------
885 */
886 add x19, sp, #CTX_PAUTH_REGS_OFFSET
887
888 mrs x20, APIAKeyLo_EL1 /* x21:x20 = APIAKey */
889 mrs x21, APIAKeyHi_EL1
890 mrs x22, APIBKeyLo_EL1 /* x23:x22 = APIBKey */
891 mrs x23, APIBKeyHi_EL1
892 mrs x24, APDAKeyLo_EL1 /* x25:x24 = APDAKey */
893 mrs x25, APDAKeyHi_EL1
894 mrs x26, APDBKeyLo_EL1 /* x27:x26 = APDBKey */
895 mrs x27, APDBKeyHi_EL1
896 mrs x28, APGAKeyLo_EL1 /* x29:x28 = APGAKey */
897 mrs x29, APGAKeyHi_EL1
898
899 stp x20, x21, [x19, #CTX_PACIAKEY_LO]
900 stp x22, x23, [x19, #CTX_PACIBKEY_LO]
901 stp x24, x25, [x19, #CTX_PACDAKEY_LO]
902 stp x26, x27, [x19, #CTX_PACDBKEY_LO]
903 stp x28, x29, [x19, #CTX_PACGAKEY_LO]
904#endif /* CTX_INCLUDE_PAUTH_REGS */
Daniel Boulby95fb1aa2022-01-19 11:20:05 +0000905 .endm /* save_gp_pmcr_pauth_regs */
906
907/* -----------------------------------------------------------------
Daniel Boulby928747f2021-05-25 18:09:34 +0100908 * This function saves the context and sets the PSTATE to a known
909 * state, preparing entry to el3.
Daniel Boulby95fb1aa2022-01-19 11:20:05 +0000910 * Save all the general purpose and ARMv8.3-PAuth (if enabled)
911 * registers.
Daniel Boulby928747f2021-05-25 18:09:34 +0100912 * Then set any of the PSTATE bits that are not set by hardware
913 * according to the Aarch64.TakeException pseudocode in the Arm
914 * Architecture Reference Manual to a default value for EL3.
915 * clobbers: x17
Daniel Boulby95fb1aa2022-01-19 11:20:05 +0000916 * -----------------------------------------------------------------
917 */
918func prepare_el3_entry
919 save_gp_pmcr_pauth_regs
Daniel Boulby928747f2021-05-25 18:09:34 +0100920 /*
921 * Set the PSTATE bits not described in the Aarch64.TakeException
922 * pseudocode to their default values.
923 */
924 set_unset_pstate_bits
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100925 ret
Daniel Boulby95fb1aa2022-01-19 11:20:05 +0000926endfunc prepare_el3_entry
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100927
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100928/* ------------------------------------------------------------------
929 * This function restores ARMv8.3-PAuth (if enabled) and all general
930 * purpose registers except x30 from the CPU context.
931 * x30 register must be explicitly restored by the caller.
932 * ------------------------------------------------------------------
Jeenu Viswambharan23d05a82017-11-29 16:59:34 +0000933 */
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100934func restore_gp_pmcr_pauth_regs
935#if CTX_INCLUDE_PAUTH_REGS
936 /* Restore the ARMv8.3 PAuth keys */
937 add x10, sp, #CTX_PAUTH_REGS_OFFSET
938
939 ldp x0, x1, [x10, #CTX_PACIAKEY_LO] /* x1:x0 = APIAKey */
940 ldp x2, x3, [x10, #CTX_PACIBKEY_LO] /* x3:x2 = APIBKey */
941 ldp x4, x5, [x10, #CTX_PACDAKEY_LO] /* x5:x4 = APDAKey */
942 ldp x6, x7, [x10, #CTX_PACDBKEY_LO] /* x7:x6 = APDBKey */
943 ldp x8, x9, [x10, #CTX_PACGAKEY_LO] /* x9:x8 = APGAKey */
944
945 msr APIAKeyLo_EL1, x0
946 msr APIAKeyHi_EL1, x1
947 msr APIBKeyLo_EL1, x2
948 msr APIBKeyHi_EL1, x3
949 msr APDAKeyLo_EL1, x4
950 msr APDAKeyHi_EL1, x5
951 msr APDBKeyLo_EL1, x6
952 msr APDBKeyHi_EL1, x7
953 msr APGAKeyLo_EL1, x8
954 msr APGAKeyHi_EL1, x9
955#endif /* CTX_INCLUDE_PAUTH_REGS */
956
957 /* ----------------------------------------------------------
958 * Restore PMCR_EL0 when returning to Non-secure state if
959 * Secure Cycle Counter is not disabled in MDCR_EL3 when
960 * ARMv8.5-PMU is implemented.
961 * ----------------------------------------------------------
962 */
963 mrs x0, scr_el3
964 tst x0, #SCR_NS_BIT
965 beq 2f
966
967 /* ----------------------------------------------------------
968 * Back to Non-secure state.
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100969 * Check if earlier initialization MDCR_EL3.SCCD/MCCD to 1
970 * failed, meaning that FEAT_PMUv3p5/7 is not implemented and
971 * PMCR_EL0 should be restored from non-secure context.
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100972 * ----------------------------------------------------------
973 */
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100974 mov_imm x1, (MDCR_SCCD_BIT | MDCR_MCCD_BIT)
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100975 mrs x0, mdcr_el3
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100976 tst x0, x1
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100977 bne 2f
978 ldr x0, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0]
979 msr pmcr_el0, x0
9802:
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100981 ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
982 ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100983 ldp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4]
984 ldp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6]
985 ldp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8]
986 ldp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10]
987 ldp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12]
988 ldp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14]
Jeenu Viswambharan23d05a82017-11-29 16:59:34 +0000989 ldp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16]
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100990 ldp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18]
991 ldp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20]
992 ldp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22]
993 ldp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24]
994 ldp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26]
Jeenu Viswambharan23d05a82017-11-29 16:59:34 +0000995 ldr x28, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0]
996 msr sp_el0, x28
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100997 ldp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28]
Jeenu Viswambharan23d05a82017-11-29 16:59:34 +0000998 ret
Alexei Fedorovf41355c2019-09-13 14:11:59 +0100999endfunc restore_gp_pmcr_pauth_regs
Jeenu Viswambharan23d05a82017-11-29 16:59:34 +00001000
Manish V Badarkhee07e8082020-07-23 12:43:25 +01001001/*
1002 * In case of ERRATA_SPECULATIVE_AT, save SCTLR_EL1 and TCR_EL1
1003 * registers and update EL1 registers to disable stage1 and stage2
1004 * page table walk
1005 */
1006func save_and_update_ptw_el1_sys_regs
1007 /* ----------------------------------------------------------
1008 * Save only sctlr_el1 and tcr_el1 registers
1009 * ----------------------------------------------------------
1010 */
1011 mrs x29, sctlr_el1
1012 str x29, [sp, #(CTX_EL1_SYSREGS_OFFSET + CTX_SCTLR_EL1)]
1013 mrs x29, tcr_el1
1014 str x29, [sp, #(CTX_EL1_SYSREGS_OFFSET + CTX_TCR_EL1)]
1015
1016 /* ------------------------------------------------------------
1017 * Must follow below order in order to disable page table
1018 * walk for lower ELs (EL1 and EL0). First step ensures that
1019 * page table walk is disabled for stage1 and second step
1020 * ensures that page table walker should use TCR_EL1.EPDx
1021 * bits to perform address translation. ISB ensures that CPU
1022 * does these 2 steps in order.
1023 *
1024 * 1. Update TCR_EL1.EPDx bits to disable page table walk by
1025 * stage1.
1026 * 2. Enable MMU bit to avoid identity mapping via stage2
1027 * and force TCR_EL1.EPDx to be used by the page table
1028 * walker.
1029 * ------------------------------------------------------------
1030 */
1031 orr x29, x29, #(TCR_EPD0_BIT)
1032 orr x29, x29, #(TCR_EPD1_BIT)
1033 msr tcr_el1, x29
1034 isb
1035 mrs x29, sctlr_el1
1036 orr x29, x29, #SCTLR_M_BIT
1037 msr sctlr_el1, x29
1038 isb
1039
1040 ret
1041endfunc save_and_update_ptw_el1_sys_regs
1042
Alexei Fedorovf41355c2019-09-13 14:11:59 +01001043/* ------------------------------------------------------------------
1044 * This routine assumes that the SP_EL3 is pointing to a valid
1045 * context structure from where the gp regs and other special
1046 * registers can be retrieved.
1047 * ------------------------------------------------------------------
Antonio Nino Diaz13adfb12019-01-30 20:41:31 +00001048 */
Yatharth Kochar6c0566c2015-10-02 17:56:48 +01001049func el3_exit
Jan Dabrosfa015982019-12-02 13:30:03 +01001050#if ENABLE_ASSERTIONS
1051 /* el3_exit assumes SP_EL0 on entry */
1052 mrs x17, spsel
1053 cmp x17, #MODE_SP_EL0
1054 ASM_ASSERT(eq)
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +00001055#endif /* ENABLE_ASSERTIONS */
Jan Dabrosfa015982019-12-02 13:30:03 +01001056
Alexei Fedorovf41355c2019-09-13 14:11:59 +01001057 /* ----------------------------------------------------------
1058 * Save the current SP_EL0 i.e. the EL3 runtime stack which
1059 * will be used for handling the next SMC.
1060 * Then switch to SP_EL3.
1061 * ----------------------------------------------------------
Yatharth Kochar6c0566c2015-10-02 17:56:48 +01001062 */
1063 mov x17, sp
Alexei Fedorovf41355c2019-09-13 14:11:59 +01001064 msr spsel, #MODE_SP_ELX
Yatharth Kochar6c0566c2015-10-02 17:56:48 +01001065 str x17, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
1066
Alexei Fedorovf41355c2019-09-13 14:11:59 +01001067 /* ----------------------------------------------------------
Yatharth Kochar6c0566c2015-10-02 17:56:48 +01001068 * Restore SPSR_EL3, ELR_EL3 and SCR_EL3 prior to ERET
Alexei Fedorovf41355c2019-09-13 14:11:59 +01001069 * ----------------------------------------------------------
Yatharth Kochar6c0566c2015-10-02 17:56:48 +01001070 */
1071 ldr x18, [sp, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
1072 ldp x16, x17, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
1073 msr scr_el3, x18
1074 msr spsr_el3, x16
1075 msr elr_el3, x17
1076
Max Shvetsovc4502772021-03-22 11:59:37 +00001077#if IMAGE_BL31
1078 /* ----------------------------------------------------------
Arunachalam Ganapathycac7d162021-07-08 09:35:57 +01001079 * Restore CPTR_EL3.
Max Shvetsovc4502772021-03-22 11:59:37 +00001080 * ZCR is only restored if SVE is supported and enabled.
1081 * Synchronization is required before zcr_el3 is addressed.
1082 * ----------------------------------------------------------
1083 */
Max Shvetsovc4502772021-03-22 11:59:37 +00001084 ldp x19, x20, [sp, #CTX_EL3STATE_OFFSET + CTX_CPTR_EL3]
1085 msr cptr_el3, x19
1086
1087 ands x19, x19, #CPTR_EZ_BIT
1088 beq sve_not_enabled
1089
1090 isb
1091 msr S3_6_C1_C2_0, x20 /* zcr_el3 */
1092sve_not_enabled:
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +00001093#endif /* IMAGE_BL31 */
Max Shvetsovc4502772021-03-22 11:59:37 +00001094
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +01001095#if IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639
Alexei Fedorovf41355c2019-09-13 14:11:59 +01001096 /* ----------------------------------------------------------
1097 * Restore mitigation state as it was on entry to EL3
1098 * ----------------------------------------------------------
1099 */
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +01001100 ldr x17, [sp, #CTX_CVE_2018_3639_OFFSET + CTX_CVE_2018_3639_DISABLE]
Alexei Fedorovf41355c2019-09-13 14:11:59 +01001101 cbz x17, 1f
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +01001102 blr x17
Antonio Nino Diaz13adfb12019-01-30 20:41:31 +000011031:
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +00001104#endif /* IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 */
1105
Manish V Badarkhee07e8082020-07-23 12:43:25 +01001106 restore_ptw_el1_sys_regs
1107
Alexei Fedorovf41355c2019-09-13 14:11:59 +01001108 /* ----------------------------------------------------------
1109 * Restore general purpose (including x30), PMCR_EL0 and
1110 * ARMv8.3-PAuth registers.
1111 * Exit EL3 via ERET to a lower exception level.
1112 * ----------------------------------------------------------
1113 */
1114 bl restore_gp_pmcr_pauth_regs
1115 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +01001116
Alexei Fedorovf41355c2019-09-13 14:11:59 +01001117#if IMAGE_BL31 && RAS_EXTENSION
1118 /* ----------------------------------------------------------
1119 * Issue Error Synchronization Barrier to synchronize SErrors
1120 * before exiting EL3. We're running with EAs unmasked, so
1121 * any synchronized errors would be taken immediately;
1122 * therefore no need to inspect DISR_EL1 register.
1123 * ----------------------------------------------------------
1124 */
1125 esb
Madhukar Pappireddyfba25722020-07-24 03:27:12 -05001126#else
1127 dsb sy
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +00001128#endif /* IMAGE_BL31 && RAS_EXTENSION */
1129
Madhukar Pappireddyfba25722020-07-24 03:27:12 -05001130#ifdef IMAGE_BL31
1131 str xzr, [sp, #CTX_EL3STATE_OFFSET + CTX_IS_IN_EL3]
Jayanth Dodderi Chidanand72b69b82022-01-26 17:14:43 +00001132#endif /* IMAGE_BL31 */
1133
Anthony Steinhauser0f7e6012020-01-07 15:44:06 -08001134 exception_return
Antonio Nino Diaz594811b2019-01-31 11:58:00 +00001135
Yatharth Kochar6c0566c2015-10-02 17:56:48 +01001136endfunc el3_exit